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path: root/drivers/pwm
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2023-11-16treewide: use linux/time.h for time conversion definesIgor Prusov6-11/+6
Now that we have time conversion defines from in time.h there is no need for each driver to define their own version. Signed-off-by: Igor Prusov <ivprusov@salutedevices.com> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> #at91 Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> #qcom geni Reviewed-by: Stefan Bosch <stefan_b@posteo.net> #nanopi2 Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-03pwm: mtk: add support for MediaTek MT7988 SoCWeijie Gao1-0/+7
This patch adds PWM support for MediaTek MT7988 SoC. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2023-05-06drivers: use dev_read_addr_ptr when cast to pointerJohan Jonker1-1/+1
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use dev_read_addr_ptr instead of the dev_read_addr function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06rockchip: pwm: rk_pwm: use base variable with uintptr_t sizeJohan Jonker1-1/+1
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use a base variable with uintptr_t size in the rk_pwm.c file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-23ARM: tegra: Fix Tegra PWM parent clockSvyatoslav Ryhel1-4/+6
Default parent clock for the PWM on Tegra is a 32kHz clock and is unable to support the requested PWM period. Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by updating the parent clock for the PWM to be the PLL_P. This commit is equivalent to Linux kernel commit: https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/ Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2022-12-23global: Migrate CONFIG_IMX6_PWM_PER_CLK to CFGTom Rini1-1/+1
Perform a simple rename of CONFIG_IMX6_PWM_PER_CLK to CFG_IMX6_PWM_PER_CLK Signed-off-by: Tom Rini <trini@konsulko.com>
2022-09-23pwm: mtk: add support for MediaTek MT7981 SoCWeijie Gao1-2/+32
This patch adds PWM support for MediaTek MT7981 SoC. MT7981 uses a different register offset so we have to add a version field to indicate the IP core version. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23pwm: mtk: add support for MediaTek MT7986 SoCWeijie Gao1-0/+6
This patch adds PWM support for MediaTek MT7986 SoC. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-08-04pwm: aspeed: Select SYSCON to get parent detail.Billy Tsai1-0/+1
To work correctly, this driver depends on SYSCON to get the base address from the parent dts node. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-07-05Rename CONFIG_PWM to CONFIG_PWM_S5P and move to KconfigTom Rini1-0/+5
We rename the S5P specific "CONFIG_PWM" to CONFIG_PWM_S5P and move it to Kconfig. Given the usage of CONFIG_PWM_NX, we have that select this new symbol. Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-04-12driver: pwm: pwm-imx: separe dm from non dm implementationTommaso Merciai1-12/+13
Separe dm implementation from non dm implementation of pwm-imx driver using CONFIG_DM_PWM Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
2022-04-12drivers: pwm: pwm-imx: move pwm-imx-util into pwm-imxTommaso Merciai4-97/+67
Move pwm_imx_get_parms, pwm_id_to_reg functions into pwm-imx.c and drop off pwm-imx-util.c Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
2022-04-12driver: pwm: pwm-imx: introduce pwm_dm_imx_get_parmsTommaso Merciai1-1/+31
Introduce pwm_dm_imx_get_parms, dm version of pwm_imx_get_parms. This function get clock rate using clk dm api Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
2022-04-12driver: pwm: pwm-imx: get and enable per/ipg clock using dmTommaso Merciai1-0/+31
Get and enable ipg/per pwms clocks using dm api into imx_pwm_of_to_plat and imx_pwm_probe driver function Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
2022-04-05Merge tag 'xilinx-for-v2022.07-rc1-v2' of ↵Tom Rini3-0/+269
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.07-rc1 v2 xilinx: - Allow booting bigger kernels till 100MB zynqmp: - DT updates (reset IDs) - Remove unneeded low level uart initialization from psu_init* - Enable PWM features - Add support for 1EG device serial_zynq: - Change fifo behavior in DEBUG mode zynq_sdhci: - Fix BASECLK setting calculation clk_zynqmp: - Add support for showing video clock gpio: - Update slg driver to handle DT flags net: - Update ethernet_id code to support also DM_ETH_PHY - Add support for DM_ETH_PHY in gem driver - Enable dynamic mode for SGMII config in gem driver pwm: - Add driver for cadence PWM versal: - Add support for reserved memory firmware: - Handle PD enabling for SPL - Add support for IOUSLCR SGMII configurations include: - Sync phy.h with Linux - Update xilinx power domain dt binding headers
2022-04-05Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini1-11/+0
A big part is the DM pinctrl driver, which allows us to get rid of quite some custom pinmux code and make the whole port much more robust. Many thanks to Samuel for that nice contribution! There are some more or less cosmetic warnings about missing clocks right now, I will send the trivial fixes for that later. Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0 (secure images) support. Both features are unused at the moment, but I have an always-secure board that will use that once the DT lands in the kernel. On top of those big things we have some smaller fixes, improving the I2C DM support, fixing some H6/H616 early clock setup and improving the eMMC boot partition support. The gitlab CI completed successfully, including the build test for all 161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100 board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
2022-04-04pwm: sunxi: Remove non-DM pin setupSamuel Holland1-11/+0
This is now handled automatically by the pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-30pwm: Add driver for cadence TTCMichal Simek3-0/+269
TTC has three modes of operations. Timer, PWM and input counters. There is already driver for timer under CADENCE_TTC_TIMER which is used for ZynqMP R5 configuration. This driver is targeting PWM which is for example configuration which can be used for fan control. The driver has been tested on Xilinx Kria SOM platform where fan is connected to one PL pin. When TTC output is connected via EMIO to PL pin TTC pwm can be configured and tested for example like this: pwm config 0 0 10000 1200 pwm enable 0 0 pwm config 0 0 10000 1400 pwm config 0 0 10000 1600 Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com> Link: https://lore.kernel.org/r/915a662ddb88f7a958ca1f307e8fea59af9d7feb.1634303847.git.michal.simek@xilinx.com
2022-03-25pwm: Add Aspeed ast2600 PWM supportBilly Tsai3-0/+260
This patch add the support of PWM controller which can be found at aspeed ast2600 soc. The pwm supoorts up to 16 channels and it's part function of multi-function device "pwm-tach controller". Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-09exynos: pwm: Deal with a PWM at 100%Simon Glass1-0/+4
At present the counter never hits the comparitor in this case. Add a special case. This ensures that the snow backlight works when at full brightness. Fixes: 76c2ff3e5fd video: backlight: fix pwm's duty cycle calculation Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2021-10-12pwm: Add PWM driver for SAMA5D2Dan Sneddon3-0/+214
Add support for the PWM found on the SAMA5D2 family of devices. Signed-off-by: Dan Sneddon <dan.sneddon@microchip.com>
2021-09-30WS cleanup: remove SPACE(s) followed by TABWolfgang Denk1-1/+1
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-07-06dm: define LOG_CATEGORY for all uclassPatrick Delaunay1-0/+2
Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-05pwm: cros_ec: Rename "priv_auto_alloc_size" to "priv_auto"Alper Nebi Yasak1-1/+1
With commit 41575d8e4c33 ("dm: treewide: Rename auto_alloc_size members to be shorter") "priv_auto_alloc_size" was renamed to "priv_auto". This driver was sent to the mailing list before that change, merged after it, and still has the old form. Apply the rename here as well. Fixes: 1b9ee2882e6b ("pwm: Add a driver for Chrome OS EC PWM") Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-14pwm: sifive: make set_config() and set_enable() work properlyVincent Chen1-10/+11
The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work properly due to the wrong implementations. It will cause the u-boot PWM command to not work as expected. The bugs will be resolved in this patch. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-04-10pwm: Add a driver for Chrome OS EC PWMAlper Nebi Yasak3-0/+94
This PWM is used in rk3399-gru-bob and rk3399-gru-kevin to control the display brightness. We can only change the duty cycle, so on set_config() we just try to match the duty cycle that dividing duty_ns by period_ns gives us. To disable, we set the duty cycle to zero while keeping the old value for when we want to re-enable it. The cros_ec_set_pwm_duty() function is taken from Depthcharge's cros_ec_set_bl_pwm_duty() but modified to use the generic pwm type. The driver itself is very loosely based on rk_pwm.c for the general pwm driver structure. The devicetree binding file is from Linux, before it was converted to YAML at 5df5a577a6b4 ("dt-bindings: pwm: Convert google,cros-ec-pwm.txt to YAML format") in their repo. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-10video: backlight: Support PWMs without a known period_nsAlper Nebi Yasak1-2/+9
The PWM device provided by Chrome OS EC doesn't really support anything other than setting a relative duty cycle. To support it as a backlight, this patch makes the PWM period optional in the device tree and pretends the valid brightness range is its period_ns. Also adds a sandbox test for a PWM channel that has a fixed period, checking that the resulting duty_cycle matches on a set_config() even if the requested period_ns can't be set. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-10rockchip: pwm: Fix default polarityArnaud Patard (Rtp)1-1/+1
In the code, the default polarity is set to positive/positive, which is neither normal polarity or inverted polarity. It's only the hardware default. This leads to booting linux with wrong polarity setting. Update the code to use PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE by default instead. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Tested-by: Peter Robinson <pbrobinson@gmail.com>
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass3-0/+3
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-15dm: fix build errors generated by last mergesDario Binacchi1-1/+1
Something was wrong in the merge process into the mainline. Some added patches access driver structure fields and functions that have been modified by previous patches. The patch renames: - dev_get_platdata to dev_get_plat - dev_get_uclass_platdata to dev_get_uclass_plat - ofdata_to_platdata to of_to_plat - plat_data_alloc_size to plat_auto - priv_auto_alloc_size to priv_auto - video_uc_platdata to video_uc_plat Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-12pwm: ti: am33xx: add enhanced pwm driverDario Binacchi3-0/+476
Enhanced high resolution PWM module (EHRPWM) hardware can be used to generate PWM output over 2 channels. This commit adds PWM driver support for EHRPWM device present on AM33XX SOC. The code is based on the drivers/pwm/pwm-tiehrpwm.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-05dm: core: Access device ofnode through functionsSimon Glass1-3/+6
At present ofnode is present in the device even if it is never used. With of-platdata this field is not used, so can be removed. In preparation for this, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass7-14/+14
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass9-9/+9
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-05pwm: Add driver for Amlogic Meson PWM controllerNeil Armstrong3-0/+536
This adds the driver for the PWM controller found in the Amlogic SoCs. This PWM is only a set of Gates, Dividers and Counters: PWM output is achieved by calculating a clock that permits calculating two periods (low and high). The counter then has to be set to switch after N cycles for the first half period. The hardware has no "polarity" setting. This driver reverses the period cycles (the low length is inverted with the high length) for PWM_POLARITY_INVERSED. Disabling the PWM stops the output immediately (without waiting for the current period to complete first). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-07-25treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr()Masahiro Yamada4-4/+4
Use the _ptr suffixed variant instead of casting. Also, convert it to dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE. One curious part is an error check like follows in drivers/watchdog/omap_wdt.c: priv->regs = (struct wd_timer *)devfdt_get_addr(dev); if (!priv->regs) return -EINVAL; devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error. So, this code does not catch any error in DT parsing. dev_read_addr_ptr() returns NULL on error, so this error check will work. I generated this commit by the following command: $ find . -name .git -prune -o -name '*.[ch]' -type f -print | \ xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/' I manually fixed drivers/usb/host/ehci-mx6.c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-24Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini4-4/+4
This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-20treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr()Masahiro Yamada4-4/+4
Use the _ptr suffixed variant instead of casting. Also, convert it to dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE. One curious part is an error check like follows in drivers/watchdog/omap_wdt.c: priv->regs = (struct wd_timer *)devfdt_get_addr(dev); if (!priv->regs) return -EINVAL; devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error. So, this code does not catch any error in DT parsing. dev_read_addr_ptr() returns NULL on error, so this error check will work. I generated this commit by the following command: $ find . -name .git -prune -o -name '*.[ch]' -type f -print | \ xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/' I manually fixed drivers/usb/host/ehci-mx6.c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-09pwm: Add PWM driver for SiFive SoCYash Shah3-0/+179
Adds a PWM driver for PWM chip present in SiFive's HiFive Unleashed SoC This driver is simple port of Linux pwm sifive driver from Linux v5.6 commit: 9e37a53eb051 ("pwm: sifive: Add a driver for SiFive SoC PWM") Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop log.h from common headerSimon Glass5-0/+5
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-17mediatek: pwm: add pwm driver for MediaTek SoCsSam Shih3-0/+196
This driver support the standard PWM API for MediaTek MT7623, MT7622 and MT7629 SoCs Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2019-12-06pwm: rk_pwm: Make PWM driver to support all Rockchip SocsDavid Wu1-19/+119
This PWM driver can be used to support pwm functions for on all Rockchip Socs. The previous chips than RK3288 did not support polarity, and register layout was different from the RK3288 PWM. The RK3288 keep the current functions. RK3328 and the chips after it, which can support hardware lock, configure duty, period and polarity at next same period, to prevent the intermediate temporary state. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19pwm: imx: add DM_PWM supportHeiko Schocher1-9/+101
add DM support for pwm-imx driver. Signed-off-by: Heiko Schocher <hs@denx.de>
2019-07-19pwm: imx: add Kconfig supportHeiko Schocher1-0/+5
add Kconfig support for this driver. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Martyn Welch <martyn.welch@collabora.co.uk>
2019-05-01rockchip: use 'arch-rockchip' as header file pathKever Yang1-1/+1
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-24pwm: sunxi: choose best prescaler to improve PWM resolutionVasily Khoruzhick1-13/+19
Choose best prescaler to improve PWM resolution. Without this change driver chooses first prescaler that gives us period value within range, but it could be not the best one. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Tested-by: Vagrant Cascadian <vagrant@debian.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-24pwm: sunxi: use new prescaler when configuring PWMVasily Khoruzhick1-1/+1
Looks like old prescaler was used when configuring PWM, fix it. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-24pwm: sunxi: fix off-by-one that prevented PWM to use prescaler bypassVasily Khoruzhick1-1/+1
Fix off-by-one that prevented PWM driver to use prescaler bypass. Without this change prescaler is always enabled. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-09test: panel: Add a test for the panel uclassSimon Glass1-0/+25
At present this uclass has no tests. Add a simple one which checks the PWM configuration, regulator and GPIO. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 09:39:49 +0000