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path: root/drivers/pci
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2019-09-02pci: sh7751: Convert to DM and DT probingMarek Vasut1-58/+106
Convert the SH7751 PCI driver to DM and add DT probing. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2019-08-28dm: pcie_fsl: Add MPC8548 PCIe supportHou Zhiqiang1-0/+1
Add compatible string for MPC8548 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P5040 PCIe supportHou Zhiqiang1-0/+1
Add compatible string for P5040 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P4080 PCIe supportHou Zhiqiang1-0/+1
Add compatible string for P4080 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P3041 PCIe supportHou Zhiqiang1-0/+1
Add compatible string for P3041 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P2041 PCIe supportHou Zhiqiang1-0/+7
Add compatible string for P2041 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCsHou Zhiqiang1-0/+7
Add compatible string for PCIe of P1020, P1021, P1024, P1025 and P2020 SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add T104x PCIe supportHou Zhiqiang1-0/+1
Add compatible string for T104x PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add T102x PCIe supportHou Zhiqiang1-0/+1
Add compatible string for T102x PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add T4240 PCIe supportHou Zhiqiang1-0/+1
Add compatible string for T4240 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Fix the calculation of controller indexHou Zhiqiang2-2/+19
The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Fix the Class Code fixup functionHou Zhiqiang2-4/+16
The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Convert IS_ENABLED() run-time checking to #ifdefHou Zhiqiang1-33/+36
This can avoid build error: The macro in brackets of the IS_ENABLED(CONFIG_FOO) is only defined on the platforms that select the CONFIG_FOO, while it's not defined on platforms that do not select the CONFIG_FOO. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-12Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini1-4/+4
- Various improvements to Keymile boards - mostly DT conversation (Pascal & Holger) - Removal of now unsupported Keymile boards (Pascal & Holger) - Small MVEBU PCI fix (Marek) - Turris Omnia defconfig update (Marek) - Misc Allied Telesis defconfig updates (Chris)
2019-08-12Merge branch '2019-08-11-ti-imports'Tom Rini3-0/+732
- More DaVinci updates and fixes - PCIe support on am65x - Watchdog converted to DM - Assorted other bugfixes
2019-08-12pcie: ti: add driver for AM65x PCIe RCSekhar Nori3-0/+732
Add driver supporting PCIe root-complex available on TI's AM65x SoC. Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12pci: pci_mvebu: set BAR0 after memory space is setMarek Behún1-4/+4
The non-DM version of this driver used to set BAR0 register after the calls to pci_set_region. I found out that for some strange reason the ath10k driver in kernel fails to work if this is done the other way around. I know that Linux's driver should not depend on how U-Boot does things, but for some strange reason it does and this seems to be the simplest solution. Fix it since it caused regressions on Omnia. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: VlaoMao <vlaomao@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-11env: Move env_get() to env.hSimon Glass3-0/+3
Move env_get() over to the new header file. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11pci: intel: Fix configuration type based on secondary numberLey Foon Tan1-4/+6
This fix issue when access config from PCIe switch. The PCIe controller need to send Type 0 config TLP if the targeting bus matches with the secondary bus number, which is when the TLP is targeting the immediate device on the link. The PCIe controller send Type 1 config TLP if the targeting bus is larger than the secondary bus, which is when the TLP is targeting the device not immediate on the link. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-08-11pci: intel: Fix error when enumerating multi-function PCIe deviceLey Foon Tan1-2/+4
Hardware return completion status non-zero when read from non exist function in multi-function PCIe device. Return error will cause PCIe enumeration fail. Change it to return 0 and return value 0xffffffff when error. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-08-11pci: intel: Increase TLP polling counterLey Foon Tan1-1/+1
Some PCIe devices require longer time to response. Increase polling counter to 20000 (~100ms). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-07-12pci: ensure enumeration of all devices in pci_initMarek Behún1-2/+2
Use the uclass_first_device_check and uclass_next_device_check functions instead of uclass_first_device and uclass_next_device in pci_init. This ensures that all PCI devices are tried to be probed. Currently if a device fails to probe, the enumeration stops and the devices which come after the failed device are not probed. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Anton Schubert <anton.schubert@gmx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: VlaoMao <vlaomao@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-10drivers: pci: add API to issue FLR on a PCI function if supportedAlex Marginean1-0/+24
Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-10drivers: pci: add map_bar support for Enhanced AllocationAlex Marginean1-0/+46
Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-21pci: Avoid assigning PCI resources that are below 0x1000Bin Meng1-2/+3
commit b7598a43f2b4 ("[PATCH] Avoid assigning PCI resources from zero address") only moved the bus lower address to 0x1000 if the given bus start address is zero. The comment said 0x1000 is a reasonable starting value, hence we'd better apply the same adjustment when the given bus start address is below 0x1000. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2019-06-20dm: pci: add Freescale PowerPC PCIe driverHou Zhiqiang5-0/+725
Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-11pci: imx: Add DM and DT supportMarek Vasut1-6/+105
Add DM support and support for probing the iMX PCI driver from DT. The legacy non-DM support is retained, however shall be removed once DM PCI is the only option remaining. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11pci: imx: Pass driver private data aroundMarek Vasut1-19/+25
Pass the driver private data around the driver as much as possible, instead of having it as a static global variable. This is done in preparation for the DM conversion, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11pci: imx: Fix potential 64bit memory access clampingMarek Vasut1-9/+11
The driver limits the config space base to 32bit, however it can be 64bit on 64bit iMX hardware too. Remove that limitation. This patch has no impact on the iMX6, which is the only SoC currently supported by this driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11pci: imx: Factor out hard-coded register base addressesMarek Vasut1-31/+44
Pull out hard-coded register base addresses into driver private structure in preparation for DM conversion. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-26Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini3-0/+420
- Gen3 PCIe driver + enablement on Salvator-X platforms. - Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon. - SDHI HS400 fixes ported from latest BSP and datasheet.
2019-05-22pci: ls_pcie_g4: add device tree fixups for PCI Stream IDsHou Zhiqiang3-6/+251
Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCsHou Zhiqiang4-0/+850
Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-21pci: renesas: Add RCar Gen3 PCIe controller driverMarek Vasut3-0/+420
Add driver for the Renesas RCar PCIe controller present on Gen3 SoCs. The PCIe on Gen3 is used both to connect external PCIe peripherals. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-20mpc83xx: Make distinct caddy2 configMario Six2-2/+4
vme8349.h contains two separate boards: The vme8349 itself, and the caddy2 board. The caddy2 board is chosen by setting certain config variables. Create a proper config file for the caddy2 board to make Kconfig migration easier. Furthermore, simplify the vme8349 and caddy2 configs by keeping only the options necessary for each board. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20vme8349: Migrate to CONFIG_TARGET_VME8349Mario Six2-2/+2
CONFIG_TARGET_VME8349 can replace CONFIG_VME8349. Hence, replace CONFIG_VME8349 with CONFIG_TARGET_VME8349, and remove CONFIG_VME8349. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20mpc83xx: Introduce ARCH_MPC834*Mario Six2-2/+2
Replace CONFIG_MPC834* with proper CONFIG_ARCH_MPC834* Kconfig options. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-08x86: Support PCI VGA ROM when TPL is usedSimon Glass1-1/+1
When TPL is in use, U-Boot proper should support initing the VGA ROM even though the 32-bit init portion is in SPL. Update the condition to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-23pci: Add boundary check for hose->regionsThierry Reding1-0/+5
Make sure that we don't overflow the hose->regions array, otherwise we would end up overwriting the hose->region_count field and cause mayhem to ensue. Also print an error message when we'd be overflowing because it indicates that there aren't enough regions available and the number needs to be increased. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-19pci: pci_mvebu: Add comment about missing of_n_addr_cells() callStefan Roese1-0/+6
This patch adds a comment to explain the use of the hardcoded value for the number of address cells in mvebu_get_tgt_attr(). This should help to rework this function, once CONFIG_OF_LIVE is enabled for MVEBU in general. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-20pci: Don't export pci_hose_config_device()Simon Glass1-5/+2
This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-11pcie: designware: mvebu: fix reset release polarityBaruch Siach1-1/+3
The dm_gpio_set_value() routine sets signal logical level, with GPIO_ACTIVE_LOW/HIGH value taken into account. Reset active value is 1 (asserted), while reset inactive value is 0 (de-asserted). Fix the reset toggle code to set the correct reset logic value. Reported-by: Sven Auhagen <sven.auhagen@voleatech.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-05Merge git://git.denx.de/u-boot-marvellTom Rini3-207/+299
- Move Armada XP / 38x PCIe driver to DM_PCI from me - Move Armada XP / 38x LCD driver to DM_VIDEO from me - Add uDPU board (Armada-3720) from Vladimir [trini: Fix warning in pci-uclass.c by removing ret from pci_uclass_child_post_bind as it no longer calls functions with a return code to catch.] Signed-off-by: Tom Rini <trini@konsulko.com>II
2019-02-05pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfigStefan Roese2-197/+282
This patch adds DM_PCI support to the MVEBU PCIe driver. This is necessary, since all PCI drivers have to be moved to DM (driver model) until the v2019.07 release. To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU from config headers to the defconfig files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: Marek Behún <marek.behun@nic.cz> Cc: VlaoMao <vlaomao@gmail.com>
2019-02-05pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addrStefan Roese1-9/+19
This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-17pci: layerscape: Add the dts fixup for EP and RCXiaowei Bao1-2/+23
Add the dts fixup when PCI controller work diffferent mode. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17pci: layerscape: Do not scan when PEX work in EP modeXiaowei Bao1-0/+3
Don't scan the bus when the PEX work in EP mode. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17pci: layerscape: Modify the EP and RC mode judge methodXiaowei Bao2-10/+9
Modify the RC and EP mode judge method, save the mode as a variable, the variable will be used by other function. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-03video: Allow driver to specify the line lengthSimon Glass1-0/+1
At present line_length is always calculated in video_post_probe(). But some hardware may use a different line length, e.g. with a 1366-wide display. Allow the driver to set this value if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2018-11-20dm/pci: Change the first CFG read to Vendor ID in enumerationHou Zhiqiang1-4/+7
As the PCIe specification recommend reading the Vendor ID register to determine if a Function is present, read the Vendor ID of a non-existent Function must not result in system error, so we'd better make the first CFG read to Vendor ID instead of Header Type register in the PCIe enumeration. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 14:56:15 +0000