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2019-06-23mmc: fsl_esdhc_imx: drop useless codeYangbo Lu1-61/+4
Dropped useless code for i.MX eSDHC driver. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-06-23mmc: fsl_esdhc: drop i.MX codeYangbo Lu1-609/+16
Dropped i.MX code which couldn't be reused. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
2019-06-23mmc: split fsl_esdhc driver for i.MXYangbo Lu3-2/+1716
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX initially. The later QoriQ series PowerPC processors (which were evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and i.MX series processors were using this driver for their eSDHCs too. For the two series processors, the eSDHCs are becoming more and more different. We should have split it into two drivers, like them (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. This patch is just to create a fsl_esdhc_imx driver which is a copy of fsl_esdhc driver for i.MX processors. We will convert i.MX processors to use fsl_esdhc_imx, and clean up the two drivers separately in the future patches. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
2019-06-20Merge tag 'mmc-6-19' of https://github.com/MrVan/u-bootTom Rini1-2/+2
- Avoid HS400 mode when accessing boot partitions
2019-06-19mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabledYangbo Lu1-0/+29
u-boot is trying to make CONFIG_BLK as a hard requirement for DM_MMC. But now it's still not. config BLK bool "Support block devices" depends on DM default y if DM_MMC When fsl_esdhc driver was reworked for DM_MMC support, DM_MMC without CONFIG_BLK enabled wasn't considered. This patch is to fix probe issue without CONFIG_BLK enabled. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19mmc: Avoid HS400 mode when accessing boot partitionsMarek Vasut1-2/+2
U-Boot code currently only applies this restriction to HS200 mode, extend this to HS400 mode as well. Currently U-Boot code not support accessing boot partition in HS200/400 mode. This needs more check. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jean-Jacques Hiblot <jjhiblot@ti.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Peng Fan <peng.fan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-05-28dm: arm: bcmstb: Enable driver model MMC supportThomas Fitzsimmons1-18/+55
For bcm7445 and bcm7260, this patch enables CONFIG_DM_MMC and updates the bcmstb SDHCI driver to use the new driver model. This allows removal of SDHCI configuration handling from bcmstb.c, and eliminates a board removal compile warning. Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org> Reviewed-by: Stefan Roese <sr@denx.de>
2019-05-26Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2-13/+176
- Gen3 PCIe driver + enablement on Salvator-X platforms. - Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon. - SDHI HS400 fixes ported from latest BSP and datasheet.
2019-05-23driver: mmc: adopt 32 bit addr in fsl_esdhc for CONFIG_PPCYinbo Zhu1-1/+4
PowerPC supports 32 bit address. So adopt 32 bit addr in fsl_esdhc for CONFIG_PPC. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-23driver: mmc: set sdhc clock in fsl_esdhc for CONFIG_PPCYinbo Zhu1-0/+6
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-21mmc: tmio: sdhi: HS400 manual adjustmentMarek Vasut2-3/+166
Since Gen3 SDHI has an internal DS signal AC-spec violation in HS400 mode, CRC-error may occur in read command in HS400 mode. This phoenomenon occurs at low/high temperature. To fix this, after completion of HS400 tuning, enable manual calibration. However, Gen3 M3 Ver.1.2 or earlier and H3 1.x does not support HS400. These SoC forcibly use HS200 mode by SoC attribute. The DT adjustment of the tuning parameters is not supported until the DT property names become clear. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Adapted from a patch by Takeshi Saito <takeshi.saito.xv@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Peng Fan <peng.fan@nxp.com>
2019-05-21mmc: tmio: sdhi: Minor macro cleanupMarek Vasut1-10/+10
Clean up the whitespaces in macros, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Peng Fan <peng.fan@nxp.com>
2019-05-20Revert "mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue"Lukasz Majewski1-18/+5
This reverts commit 72a89e0da5ac6a4ab929b15a2b656f04f50767f6, which causes the imx53 HSC to hang as the eMMC is not working properly anymore. The exact error message: MMC write: dev # 0, block # 2, count 927 ... mmc write failed 0 blocks written: ERROR imx53 is not using the DDR mode. Debugging of pre_div and div generation showed that those values are generated in a way, which is not matching the ones from working setup. As the original patch was performing code refactoring, let's revert this change, so all imx53 boards would work again. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-05-04Merge tag 'mmc-2019-5-3' of https://github.com/MrVan/u-bootTom Rini3-54/+189
2019-05-04Convert CONFIG_SUPPORT_EMMC_BOOT to KconfigAlex Kiernan1-0/+6
This converts the following to Kconfig: CONFIG_SUPPORT_EMMC_BOOT As requested by Michal Simek <michal.simek@xilinx.com>, these boards have no eMMC so CONFIG_SUPPORT_EMMC_BOOT has not been migrated: xilinx_zynqmp_zc1275_revB xilinx_zynqmp_zc1751_xm018_dc4 xilinx_zynqmp_zc1751_xm019_dc5 xilinx_zynqmp_zcu100_revC xilinx_zynqmp_zcu102_rev1_0 xilinx_zynqmp_zcu102_revA xilinx_zynqmp_zcu102_revB xilinx_zynqmp_zcu104_revA xilinx_zynqmp_zcu104_revC xilinx_zynqmp_zcu106_revA xilinx_zynqmp_zcu111_revA Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Acked-by: Lukasz Majewski <lukma@denx.de> Acked-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2019-05-03Merge git://git.denx.de/u-boot-socfpgaTom Rini1-7/+31
- Misc MMC, FPGA bridge, general SoCFPGA fixes
2019-05-03mmc: sdhci: Add Support for ADMA2Faiz Abbas2-23/+129
The Standard Host Controller Interface (SDHCI) specification version 3.00 adds support for Advanced DMA (ADMA) for both 64 and 32 bit widths of DMA. ADMA2 uses a table of descriptors for aggregating DMA requests. This significantly improves read and write throughput. Add Support for the same. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-05-03mmc: sdhci: Move DMA handling to prepare_dma() functionFaiz Abbas1-42/+50
In preparation for addition of ADMA2 support, cleanup SDMA handling by moving it to a new sdhci_prepare_dma() function. Also add a flags field in sdhci_host to indicate if DMA is enabled. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-05-03mmc: fsl_esdhc: Fix wp_enable issueYe Li1-5/+13
The wp-gpios property is used for gpio, if this is set, the WP pin is muxed to gpio function, can't be used as internal WP checking. However the codes remain to use internal WP checking. This patch changes to examine the "fsl,wp-controller" for enabling internal WP checking, and "wp-gpios" for muxing to gpio. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-05-03mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issueYe Li1-5/+18
When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode, the output clock rate is half of the internal clock rate. This patch set the DDR_EN bit first for DDR mode, hardware divide the usdhc clock automatically, then follow the original sdr clock setting method. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
2019-05-01rockchip: use 'arch-rockchip' as header file pathKever Yang1-2/+2
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-04-29mmc: dw_mmc: Round up descriptor end to nearest multiple of cacheline sizeMarek Vasut1-2/+2
The driver currently calculates the end address of cache flush operation for the DMA descriptors by adding cacheline size to the start address of the last DMA descriptor. This is not safe, as the cacheline size may be, in some unlikely cases, smaller than the DMA descriptor size. Replace the addition with roundup() applied on the end address of the last DMA descriptor to round it up to the nearest cacheline size multiple. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org>
2019-04-29mmc: dw_mmc: Handle return value from bounce_buffer_start()Marek Vasut1-2/+8
The bounce_buffer_start() can return -ENOMEM in case memory allocation failed. However, in that case, the bounce buffer address is the same as the possibly unaligned input address, and the cache maintenance operations were not applied to this address. This could cause subtle problems. Add handling for the bounce_buffer_start() return value to prevent such a problem from happening. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org>
2019-04-29mmc: dw_mmc: Calculate timeout from transfer lengthMarek Vasut1-3/+21
The current 4-minute data transfer timeout is misleading and broken. Instead of such a long wait, calculate the timeout duration based on the length of the data transfer. The current formula is the transfer length in bits, divided by a multiplication of bus frequency in Hz, bus width, DDR mode and converted the mSec. The value is bounded from the bottom to 1000 mSec. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org>
2019-04-26mmc: mv_sdhci: add driver model supportPierre Bourdon1-1/+66
The new DM implementation currently does not support the Sheeva 88SV331xV5 specific quirk present in the legacy implementation. The legacy code is thus kept for this SoC and others not yet migrated to DM_MMC. Signed-off-by: Pierre Bourdon <delroth@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-24Merge tag 'u-boot-stm32-mcu-20190423' of https://github.com/pchotard/u-bootTom Rini3-13/+71
STM32 MCUs update: - DT rework and alignment with DT kernel v4.20 - mmc: arm_pl180_mmci: Synchronize compatible with kernel v4.20 - mmc: stm32_sdmmc2: Synchronize properties with kernel v4.20 - configs: update for F746/769 boards
2019-04-23mmc: mtk-sd: fix configuration option checkFabien Parent1-4/+4
We either need to use IS_ENABLED(CONFIG_FOO) or CONFIG_IS_ENABLED(FOO). IS_ENABLE(FOO) will always return false. This commit fixes the comparison by using the CONFIG_IS_ENABLED(FOO) syntax. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2019-04-23mmc: mtk-sd: add support for MT8516Fabien Parent1-0/+10
Add config for handling MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23mmc: mtk-sd: add source_cg clock supportFabien Parent1-0/+5
Some MediaTek SoC need an additional clock "source_cg". Enable this new clock. We reuse the same clock name as in the kernel. Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23mmc: stm32_sdmmc2: Fix r1b timeout issueChristophe Kerello1-6/+55
On response type r1b, if DTIME is not defined or too short, the Datatimeout and DPSM flag occurs. Like the DPSM is activated all next data transfer will be frozen. To avoid this freeze: -The driver must define a DTIME on all r1b response type. -DTIME of SDMMC must be defined for alls stop transmission (for read and write request) even if MMC_RSP_BUSY is not set. -If busy timeout occur, an abort request must be sent to reinitialize the DPSM. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com>
2019-04-23mmc: stm32_sdmmc2: Update DT properties with v4.19 bindingsPatrick Delaunay1-3/+3
Some properties name has been updated: - st,dirpol becomes st,sig-dir - st,negedge becomes st,neg-edge - st,pin-ckin becomes st,use-ckin Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23mmc: arm_pl180_mmci: Sync compatible with kernelPatrice Chotard2-4/+13
Initially the compatible string was wrongly set to "st,stm32f4xx-sdio". Use compatible string used by kernel instead and identify mmci variant using "arm,primecell-periphid" property. Currently, the DM part of mmci driver is only used by STM32 SoCs, that's why the switch case gets only one entry. It will be populated easily with new variant in the future. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-18ARC: dwmmc: Adding DesignWare MMC driver support for ARC devboardsEugeniy Paltsev3-0/+210
Add the DM_MMC-compatible DesignWare MMC driver support for Synopsys ARC devboards. It is created to switch ARC devboards to use DM_MMC. It required information such as clocks (Bus Interface Unit clock, Card Interface Unit clock) and SDIO bus width. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-04-12mmc: omap_hsmmc: Set 3.3V for IO voltageFaiz Abbas1-11/+10
Pbias voltage should match the IO voltage set for the SD card. With the latest pbias change to 3.3V, update the capabilities and IO voltages settings to 3.3V. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-03-29mmc: correct the HS400 initialization processBOUGH CHEN1-2/+1
After the commit b9a2a0e2e9c0 ("mmc: Add support for downgrading HS200/HS400 to HS mode"), it add a parameter in mmc_set_card_speed() which indicates that the HS200/HS400 to HS downgrade is happening. During the HS400 initialization, first select to HS200, and config the related clock rate, then downgrade to HS mode. So here also need to config the downgrade value to be true for two reasons. First, make sure in the function mmc_set_card_speed(), after switch to HS mode, first config the clock rate, then read the EXT_CSD, avoid receiving data of EXT_CSD in HS mode at 200MHz. Second, after issue the MMC_CMD_SWITCH command, it need to wait a bit then switch bus properties. Test on i.MX8QM MEK board, some Micron eMMC will stuck in transfer mode in this case, and USDHC will never get data transfer complete status, cause the uboot hang. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
2019-03-26Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2-2/+5
- Various fixes for bugs found by u-boot test.py
2019-03-25mmc: tmio: Clamp SD_SECCNT to 16bit values on 16bit IPMarek Vasut1-1/+4
On 16bit variants of the TMIO SD IP, the SECCNT register can only be programmed to 16bit values, while on the 32bit and 64bit variants it can be programmed to 32bit values. The SECCNT register indicates the maximum number of blocks in a continuous transfer. Hence, limit the maximum continuous transfer block count to 65535 blocks on 16bit variants of the TMIO IP and to BIT(32)-1 blocks on 32bit and 64bit variants. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-03-25mmc: sh_mmcif: Set default MMCIF clock rateMarek Vasut1-1/+1
Set MMCIF clock rate to 97.5 MHz, which is the default according to Gen2 datasheet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2019-03-25mmc: Align MMC_TRACE with tiny printfMarek Vasut1-10/+10
The tiny printf implementation only supports %x format specifier, it does not support %X . Since it makes little difference whether the debug output prints hex numbers in capitals or not, change it to %x and make the MMC_TRACE output work with tiny printf too. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org>
2019-02-25mmc: renesas: Unconditionally set DTCNTL TAPNUM to 8Marek Vasut1-1/+1
According to latest specification rev.0026 and after confirmation with HW engineer, the DTCNTL register TAPNUM field must be set to 8 even on H3 ES2.0 SoC. Make it so. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-25mmc: tmio: Clear BUSWIDTH bit when WMODE bit is setMarek Vasut1-1/+1
According to latest specification rev.0026, when HOST_MODE bit 0 (WMODE) is not set, HOST_MODE bit 8 (BUSWIDTH) is ignored. Clear HOST_MODE bit 8 in such case and align the code with Linux and avoid possible unforeseen issues. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-18Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini1-0/+19
- Misc Gen5 fixes - stratix10 bugfix - dwmmc bugfix
2019-02-18mmc: dwmmc: Poll for iDMAC TX/RX interruptLey Foon Tan1-0/+19
Poll for iDMAC TX/RX interrupt before disable DMA. This to prevent disable DMA before data is transfer completed. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-02-16Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini4-3/+55
- Various MMC fixes
2019-02-16mmc: tmio: sdhi: Configure DT2FF register for HS400 modeMarek Vasut1-0/+3
The DT2FF register must be configured differently for HS400 mode and for HS200/SDR104 mode. Configure the DT2FF register according to the recommended datasheet settings for each mode. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-16mmc: tmio: Configure HOST_MODE WMODE according to bus widthMarek Vasut1-3/+7
Set the HOST_MODE register WMODE bit according to the SDHI bus width, that is 0 for 64bit bus and 1 for 16/32bit bus. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-16mmc: Downgrade SD/MMC from UHS/HS200/HS400 modes before bootMarek Vasut2-0/+45
Older kernel versions or systems which do not connect eMMC reset line properly may not be able to handle situations where either the eMMC is left in HS200/HS400 mode or SD card in UHS modes by the bootloader and may misbehave. Downgrade the eMMC to HS/HS52 mode and/or SD card to non-UHS mode before booting the kernel to allow such older kernels to work with modern U-Boot. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com>
2019-02-15mmc: fsl_esdhc: Fix DM_REGULATOR ifdefs for SPL buildsAbel Vesa1-4/+4
Since the fsl_esdhc will also be used by SPL, make the preprocessor switches more generic to allow any kind of build. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-10Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini5-13/+38
- SD/MMC fixes and ext4 memory leak fix
2019-02-10Merge tag 'dm-pull-10feb19' of git://git.denx.de/u-boot-dmTom Rini2-58/+8
Samsung sound patches (applied for Samsung maintainer) Common sound support buildman environment support of-platdata documentation improvements
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