summaryrefslogtreecommitdiff
path: root/drivers/gpio
AgeCommit message (Collapse)AuthorFilesLines
2022-02-05GPIO: fxl6408: Add support for FXL6408 GPIO expanderOleksandr Suvorov3-0/+388
Initial support for Fairchild's 8 bit I2C gpio expander FXL6408. The CONFIG_FXL6408_GPIO define enables support for such devices. Based on: https://patchwork.kernel.org/patch/9148419/ Signed-off-by: Oleksandr Suvorov <cryosay@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2022-01-30gpio: sunxi: Implement .set_flagsSamuel Holland1-35/+27
This, along with gpio_flags_xlate(), allows the GPIO driver to handle pull-up/down flags provided by consumer drivers or in the device tree. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-20Merge tag 'doc-2022-04-rc1' of ↵Tom Rini4-5/+5
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request doc-2022-04-rc1 Replace @return by Return: in code comments.
2022-01-19doc: replace @return by Return:Heinrich Schuchardt4-5/+5
Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-19Merge tag 'xilinx-for-v2022.04-rc1' of ↵Tom Rini3-0/+163
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.04-rc1 gpio: - Add modepin driver net: - Save random mac addresses to eth variable zynqmp gem: - Add support for mdio bus DT description - Add support for reset and SGMII phy configuration - Reduce timeout for MDIO accesses zynqmp clk: - Fix clock handling for gem and usb phy: - Add zynqmp phy/serdes driver serial: - Add one missing compatible string microblaze: - Symbol alignement - SPL fixups - Code cleanups zynqmp: - Various dt changes, DP pre-reloc, gem resets, gem clocks - Switch SOM to shared psu configuration - Move dcache handling to firmware driver - Workaround gmii2rgmii DT description issue - Enable broadcasts again - Change firmware enablement logic - Small adjustement in firmware driver versal: - Support new mmc@ DT nodes - Fix run time variable handling - Add missing I2C_PMC ID for power domain
2022-01-16gpio: da8xx_gpio: Fix gpio name with addresschao zeng1-0/+8
The GPIO bank numbers do not appear in the device tree, so make the gpio name based on the address (ie gpio@42110000_25 vs 25) Signed-off-by: chao zeng <chao.zeng@siemens.com>
2022-01-05zynqmp: gpio: Add support for zynqmp gpio modepin driverT Karthik Reddy3-0/+163
ZynqMP modepin driver has capability to get/set/check status of modepin gpios. These modepins are accessed using xilinx firmware. In modepin register, [3:0] bits set direction, [7:4] bits read IO, [11:8] bits set/clear IO. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/2d802d98fd56d95d764532a33e844d935e0cebb3.1635505900.git.michal.simek@xilinx.com
2021-12-27Convert CONFIG_KIRKWOOD_GPIO to KconfigTom Rini1-0/+5
This converts the following to Kconfig: CONFIG_KIRKWOOD_GPIO Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-10gpio: stm32: create include file for driver private dataPatrick Delaunay2-1/+88
The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-10-31SoC: exynos: add support for exynos 78x0Dzmitry Sankouski1-0/+1
Samsung Exynos 7880 \ 7870 - SoC for mainstream smartphones and tablets introduced on March 2017. Features: - 8 Cortex A53 cores - ARM Mali-T830 MP3 GPU - LTE Cat. 7 (7880) or 6 (7870) modem Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
2021-10-31pinctrl: qcom: add pinctrl and gpio drivers for SDM845 SoCDzmitry Sankouski2-3/+6
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephan Gerhold <stephan@gerhold.net> [trini: Add CONFIG_SDM845 around sdm845_data usage]
2021-10-20gpio: sifive: Fix -Wint-to-pointer-cast warningBin Meng1-4/+2
dev_read_addr() returns a value of type fdt_addr_t which is a 64-bit address and plat->base is a pointer. In a 32-bit build, this causes the following warning seen when building sifive-gpio.c: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Change to use dev_read_addr_ptr(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-19drivers/gpio: add support for MAX7320 i2c i/o expanderHannes Schmelzer3-0/+122
This commit adds support for the MAX7320 (and clones) gpio expander. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2021-10-11sunxi: gpio: Remove bank-specific size macrosSamuel Holland1-2/+0
Since the beginning, all banks have had space for 32 pins, even when not all pins were implemented. Let's use a single constant for the GPIO bank size here, like the GPIO driver is already doing. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11sunxi: Clean up inclusions of asm/arch/gpio.hSamuel Holland2-2/+0
As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11gpio: sunxi: Remove the sunxi_name_to_gpio_bank functionSamuel Holland1-14/+0
The only caller of this function was the MMC pinmux code, which used it to parse a string given from a Kconfig symbol. As the Kconfig symbol has been converted to a Boolean, this function is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-05gpio: Factor out DT flag translationSamuel Holland1-21/+29
The generic GPIO flags binding is shared across many drivers, some of which need their own xlate function. Factor out the flag translation code from gpio_xlate_offs_flags so it does not need to be duplicated. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05gpio: Verify validity of pin offsets from device treesSamuel Holland1-0/+4
Translation of an OF GPIO specifier should fail if the pin offset is larger than the number of pins in the GPIO bank. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05gpio: Verify validity of pin offsets when looking up namesSamuel Holland1-1/+2
Translation of a pin name to a device+offset should fail if the offset is larger than the number of pins in the GPIO bank. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-01arm: Remove zmx25 board and ARCH_MX25Tom Rini1-3/+3
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last ARCH_MX25 platform, remove those references as well. Cc: Matthias Weisser <weisserm@arcor.de> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-01arm: Remove aspenite boardTom Rini2-56/+0
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last armada100 platform, remove that support as well. Cc: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-30WS cleanup: remove excessive empty linesWolfgang Denk1-2/+0
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30WS cleanup: remove trailing empty linesWolfgang Denk1-2/+0
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-25dm: gpio: Add of-platdata supportSimon Glass4-8/+57
Add support for accessing GPIOs using of-plata. This uses the same mechanism as for clocks, but allows use of the xlate() method so that the driver can interpret the parameters. Update the condition for GPIO_HOG so that it is not built into SPL, since it needs SPL_OF_REAL which is not enabled in sandbox_spl. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25treewide: Use OF_REAL instead of !OF_PLATDATASimon Glass3-3/+3
Now that we have a 'positive' Kconfig option, use this instead of the negative one, which is harder to understand. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25treewide: Simply conditions with the new OF_REALSimon Glass2-3/+3
Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-16Merge tag 'v2021.10-rc4' into nextTom Rini1-1/+1
Prepare v2021.10-rc4 Signed-off-by: Tom Rini <trini@konsulko.com> # gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # board/Arcturus/ucp1020/spl.c # cmd/mvebu/Kconfig # common/Kconfig.boot # common/image-fit.c # configs/UCP1020_defconfig # configs/sifive_unmatched_defconfig # drivers/pci/Kconfig # include/configs/UCP1020.h # include/configs/sifive-unmatched.h # lib/Makefile # scripts/config_whitelist.txt
2021-09-13pci: Drop DM_PCISimon Glass1-1/+1
This option has not effect now. Drop it, using PCI instead where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-04gpio: Add a GPIO configSimon Glass1-2/+14
At present we have SPL_GPIO and TPL_GPIO but not piain GPIO. This works because there is a special build rule in Makefile that always includes the drivers/gpio directory. It is better to have all driver directories included by drivers/Makefile and there is already a rule in there for this purpose. It just needs a Kconfig for U-Boot proper, so add one. Enable the option always for now, since this mimics current behaviour. This can be updated once DM_GPIO is used everywhere. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-04tegra: gpio: Drop use of CONFIG_xxx variablesSimon Glass1-5/+5
It is not a good idea to use things called CONFIG_xxx in the source code since this prefix is reserved for use by Kconfig. Rename these variables. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-31Kconfig: Remove all default n/no optionsMichal Simek1-10/+0
default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@xilinx.com> [trini: Rework FSP_USE_UPD portion] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-22gpio: mcp230xx: Introduce new driverSebastian Reichel3-0/+246
Introduce driver for I2C based MCP230xx GPIO chips, which are quite common and already well supported by the Linux kernel. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02global: Convert simple_strtoul() with decimal to dectoul()Simon Glass3-5/+5
It is a pain to have to specify the value 10 in each call. Add a new dectoul() function and update the code to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02global: Convert simple_strtoul() with hex to hextoul()Simon Glass1-2/+2
It is a pain to have to specify the value 16 in each call. Add a new hextoul() function and update the code to use it. Add a proper comment to simple_strtoul() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-28Rename GPIO_SUPPORT to GPIOSimon Glass1-3/+3
Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-23i2c: pcf8575: Add support for 8 bit I2C IO expanders (like pca8574)Lukasz Majewski1-21/+19
This patch add support for using NXP's pca8574 I2C IO expander, which has only 8 IO lines. After this change the .data member's information from struct udevice_id are used to either sent one or two bytes. Moreover, the '_le16' suffix from pcf8575_i2c_{write|read}_le16() functions have been removed as now we also sent 8 bit data. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-23i2c: pcf8575: Remove not used members of pcf8575_chip structureLukasz Majewski1-3/+0
Those members are not used anymore as ones from gpio_dev_priv structure (when DM_GPIO support is enabled) are used instead. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-14gpio: Add driver for Nomadik GPIOStephan Gerhold3-0/+134
Nomadik GPIO is a fairly simple GPIO module used in the ST-Ericsson Ux500 SoCs (and some older Nomadik SoCs). It uses registers where each GPIO is represented as a single bit, plus "set" and "clear" registers that allow updating the state without having to read the existing state. The driver implements support for it for use together with DM_GPIO and the existing ste-dbx5x0.dtsi device tree. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-14gpio: Drop long unused DB8500 GPIO driverStephan Gerhold2-222/+0
The original U-Boot port for the ST-Ericsson U8500 SoC was dropped in commit 68282f55b846 ("arm: Remove unused ST-Ericsson u8500 arch"). Most of the drivers related to the old port were removed, but the db8500_gpio.c driver was forgotten for some reason. There is no way to select it and it does not compile anymore because of missing headers, so let's just remove it. The new port for U8500 introduced in commit 689088f9dae8 ("arm: Add support for ST-Ericsson U8500 SoC") fully embraces the new Driver Model and device trees where possible, so this is preparation to add a new, simplified GPIO driver based on DM_GPIO. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-07arm: Remove spear600 boards and the rest of SPEAr supportTom Rini2-90/+0
These boards have not been converted to CONFIG_DM_USB by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the last of the SPEAr platforms, so remove the rest of the remaining support as well. Cc: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-01Merge tag 'xilinx-for-v2021.10' of ↵Tom Rini1-1/+1
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.10 clk: - Add driver for Xilinx Clocking Wizard IP fdt: - Also record architecture in /fit-images net: - Fix plat/priv data handling in axi emac - Add support for 10G/25G speeds pca953x: - Add missing dependency on i2c serial: - Fix dependencies for DEBUG uart for pl010/pl011 - Add setconfig option for cadence serial driver watchdog: - Add cadence wdt expire now function zynq: - Update DT bindings to reflect the latest state and descriptions zynqmp: - Update DT bindings to reflect the latest state and descriptions - SPL: Add support for ECC DRAM initialization - Fix R5 core 1 handling logic - Enable firmware driver for mini configurations - Enable secure boot, regulators, wdt - Add support xck devices and 67dr - Add psu init for sm/smk-k26 SOMs - Add handling for MMC seq number via mmc_get_env_dev() - Handle reserved memory locations - Add support for u-boot.itb generation for secure OS - Handle BL32 handoffs for secure OS - Add support for 64bit addresses for u-boot.its generation - Change eeprom handling via nvmem aliases
2021-06-24gpio: renesas: Handle R8A779A0 V3U INEN registerMarek Vasut1-0/+14
The R8A779A0 V3U GPIO block has additional "General Input Enable" INEN register. Add new R8A779A0 compatible string with a new quirk and also a handler for this quirk which toggles the INEN register in the right place. INEN register handling is based on "gpio: renesas: Add R8A779A0 V3U support" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-23gpio: pca953x: Add missing i2c dependencyMichal Simek1-1/+1
pca953x also depends on i2c that's why add dependency to Kconfig. Where GPIO is enabled but I2C compilation error pops up. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-05-21gpio: renesas: Pass struct udevice to rcar_gpio_set_direction()Marek Vasut1-7/+6
Pass struct udevice to rcar_gpio_set_direction() in preparation of quirk handling in rcar_gpio_set_direction(). No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-04dm: gpio: Fix gpio_get_list_count failing with livetreeSean Anderson1-3/+3
of_parse_phandle_with_args (called by dev_read_phandle_with_args) does not support getting the length of a phandle list by using the index -1. Instead, use dev_count_phandle_with_args which supports exactly this use-case. Fixes: 8558217153 ("gpio: Convert to use APIs which support live DT") Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-19gpio: atmel_pio4: add support for sama7g5 pio4 version with 5 banksEugen Hristev1-0/+22
Add support for sama7g5 pinctrl variant, with 5 banks with a degraded 8 line only 5th bank. Based on Linux Kernel implementation. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-04-12gpio: Drop dm_gpio_set_dir()Simon Glass1-11/+0
This function is not used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-27x86: Probe device if needed in intel_gpio_xlate()Simon Glass1-1/+13
The Intel GPIO binding allows GPIOs to be globally numbered, so that it does not matter which GPIO bank is specified in the device tree. This is convenient and avoid confusion since the banks do not have the same number of GPIOs and the numbering is not sequential. The GPIO uclass ensures that the device mentioned in the devicetree binding is probed. It is fine for the driver to update gpio_desc to point to a different driver, but this may not have been probed. If it has not been, then it cannot be claimed since there is no uclass data. We could handle this in the GPIO uclass but so far it is an unusual situation so it is probably not worth the extra code. Handle this case in the GPIO driver by probing the selected device if necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-15Merge tag 'v2021.04-rc4' into nextTom Rini1-3/+4
Prepare v2021.04-rc4
2021-03-05gpio: mpc8xxx: Support controller register physical address beyond 32-bitBin Meng1-3/+4
dev_read_addr_size_index() returns fdt_addr_t which might be a 64-bit physical address. This might be true for some 85xx SoCs whose CCSBAR is mapped beyond 4 GiB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 22:04:33 +0000