platform/kernel/u-boot - Domain: System / Kernel;

Age	Commit message (Expand)	Author	Files	Lines
2019-07-16	sunxi: clocks: Add H6 USB clock gates and resets	Andre Przywara	1	-0/+29
2019-04-16	clk: sunxi: r40: Fix GMAC reset reg offset	Jagan Teki	1	-1/+2
2019-04-01	clk: sunxi: a10: Add CLK_AHB_GMAC	Jagan Teki	1	-0/+2
2019-03-09	clk: sunxi: h3: Implement EPHY CLK and RESET	Jagan Teki	1	-0/+4
2019-03-09	clk: sunxi: Implement EMAC, GMAC clocks, resets	Jagan Teki	6	-0/+15
2019-03-09	clk: sunxi: Implement A10 EMAC clocks	Jagan Teki	2	-0/+2
2019-03-04	clk: sunxi: Implement SPI clocks, resets	Jagan Teki	11	-0/+97
2019-01-30	sunxi: clk: enable clk and reset for CCU devices	Andre Przywara	1	-0/+12
2019-01-29	sunxi: clk: A80: add MMC clock support	Andre Przywara	1	-1/+27
2019-01-29	sunxi: clk: add MMC gates/resets	Andre Przywara	11	-0/+63
2019-01-18	clk: sunxi: Add Allwinner A80 CLK driver	Jagan Teki	3	-0/+65
2019-01-18	clk: sunxi: Add Allwinner H6 CLK driver	Jagan Teki	3	-0/+61
2019-01-18	clk: sunxi: Implement UART resets	Jagan Teki	7	-0/+43
2019-01-18	clk: sunxi: Implement UART clocks	Jagan Teki	9	-0/+57
2019-01-18	clk: sunxi: Add Allwinner V3S CLK driver	Jagan Teki	3	-0/+59
2019-01-18	clk: sunxi: Add Allwinner R40 CLK driver	Jagan Teki	3	-0/+78
2019-01-18	clk: sunxi: Add Allwinner A83T CLK driver	Jagan Teki	3	-0/+71
2019-01-18	clk: sunxi: Add Allwinner A23/A33 CLK driver	Jagan Teki	3	-0/+71
2019-01-18	clk: sunxi: Add Allwinner A31 CLK driver	Jagan Teki	3	-0/+76
2019-01-18	clk: sunxi: Add Allwinner A10s/A13 CLK driver	Jagan Teki	3	-0/+64
2019-01-18	clk: sunxi: Add Allwinner A10/A20 CLK driver	Jagan Teki	3	-0/+67
2019-01-18	clk: sunxi: Add Allwinner H3/H5 CLK driver	Jagan Teki	3	-0/+87
2019-01-18	reset: Add Allwinner RESET driver	Jagan Teki	2	-0/+21
2019-01-18	clk: Add Allwinner A64 CLK driver	Jagan Teki	4	-0/+147