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2023-08-02riscv: sifive: initialize PCI on UnmatchedHeinrich Schuchardt1-0/+1
The Unmatched board is typically booted from NVMe which requires PCI. When dropping to a console PCI is not initialized yet. 'pci enum' has to be called. Change the configuration to call pci_init() in board_init_r(). Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-08-02configs: starfive-jh7110: Add CONFIG_RTL8169Minda Chen1-0/+1
Add PCIe device rtl8169 net adapter driver support. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-02configs: starfive-jh7110: Add support for PCIe host driverMason Huo1-0/+7
Add PCIe host driver and nvme driver in configure file. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-01Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini1-0/+1
- i2c-gpio: Correctly handle new {sda, scl}-gpios bindings (Chris) - mvebu: x240: Use i2c-gpio instead of built in controller (Chris)
2023-07-31board: rockchip: Add Radxa E25 Carrier BoardJonas Karlman1-0/+94
Radxa E25 is a network application carrier board for the Radxa CM3I SoM with a RK3568 SoC. It features dual 2.5G ethernet, mini PCIe, M.2 B Key, USB3, eMMC, SD, nano SIM card slot and a 26-pin GPIO header. Features tested on a Radxa E25 v1.4: - SD-card boot - eMMC boot - USB host - PCIe/Ethernet adapters is detected - SATA Device tree is imported from linux next-20230728. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: FUKAUMI Naoki <naoki@radxa.com>
2023-07-31configs: rockchip: Enable USB2PHY for RK3328 boardsJagan Teki6-0/+6
Enable USB2PHY for all RK3328 boards. => usb start starting USB... Bus usb@ff5c0000: USB EHCI 1.00 Bus usb@ff5d0000: USB OHCI 1.0 Bus usb@ff600000: generic_phy_get_bulk : no phys property Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 Bus usb@ff580000: USB DWC2 scanning bus usb@ff5c0000 for devices... 2 USB Device(s) found scanning bus usb@ff5d0000 for devices... 1 USB Device(s) found scanning bus usb@ff600000 for devices... 2 USB Device(s) found scanning bus usb@ff580000 for devices... 2 USB Device(s) found scanning usb for storage devices... 2 Storage Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | u-boot EHCI Host Controller | +-2 Mass Storage (480 Mb/s, 500mA) TS-RDF5A Transcend 000000000009 1 Hub (12 Mb/s, 0mA) U-Boot Root Hub 1 Hub (5 Gb/s, 0mA) | U-Boot XHCI Host Controller | +-2 Mass Storage (5 Gb/s, 224mA) SanDisk Dual Drive 040130e3ee554b7078843f4eb331646 1 Hub (480 Mb/s, 0mA) | U-Boot Root Hub | +-2 Human Interface (12 Mb/s, 98mA) Logitech USB Receiver => dm tree -s Class Index Probed Driver Name ----------------------------------------------------------- syscon 1 [ + ] syscon |-- syscon@ff450000 phy 0 [ + ] rockchip_usb2phy | `-- usb2phy@100 clk 2 [ + ] rockchip_usb2phy_clo | |-- usb480m_phy phy 1 [ + ] rockchip_usb2phy_por | |-- otg-port phy 2 [ + ] rockchip_usb2phy_por | `-- host-port sysinfo 0 [ + ] sysinfo_smbios |-- smbios usb 3 [ + ] dwc2_usb |-- usb@ff580000 usb_hub 3 [ + ] usb_hub | `-- usb_hub usb_dev_ge 0 [ + ] usb_dev_generic_drv | `-- generic_bus_3_dev_2 usb 0 [ + ] ehci_generic |-- usb@ff5c0000 usb_hub 0 [ + ] usb_hub | `-- usb_hub usb_mass_s 0 [ + ] usb_mass_storage | `-- usb_mass_storage blk 2 [ + ] usb_storage_blk | |-- usb_mass_storage.lun0 partition 4 [ + ] blk_partition | | |-- usb_mass_storage.lun0:1 partition 5 [ + ] blk_partition | | `-- usb_mass_storage.lun0:2 bootdev 3 [ ] usb_bootdev | `-- usb_mass_storage.lun0.bootdev usb 1 [ + ] ohci_generic `-- usb@ff5d0000 usb_hub 1 [ + ] usb_hub `-- usb_hub Cc: Tianling Shen <cnsztl@gmail.com> Cc: David Bauer <mail@david-bauer.net> Cc: Loic Devulder <ldevulder@suse.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Banglang Huang <banglang.huang@foxmail.com> Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31configs: Enable DWC3 USB 3.0 on RK3328 boardsJagan Teki6-0/+12
Enable USB 3.0 in all RK3328 boards. => usb start starting USB... Bus usb@ff5c0000: ehci_generic usb@ff5c0000: Failed to get clocks (ret=-19) Port not available. Bus usb@ff5d0000: USB OHCI 1.0 Bus usb@ff600000: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 Bus usb@ff580000: 1 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found => usb tree USB device tree: 1 Hub (12 Mb/s, 0mA) U-Boot Root Hub 1 Hub (5 Gb/s, 0mA) | U-Boot XHCI Host Controller | +-2 Mass Storage (5 Gb/s, 224mA) SanDisk Dual Drive 040130e3ee554b7078843f4eb331646 1 Hub (480 Mb/s, 0mA) U-Boot Root Hub Cc: Tianling Shen <cnsztl@gmail.com> Cc: David Bauer <mail@david-bauer.net> Cc: Loic Devulder <ldevulder@suse.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Banglang Huang <banglang.huang@foxmail.com> Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31configs: Drop unused XHCI_DWC3 for RK3328 boardsJagan Teki6-6/+0
Driver support for rk3328 is not supported so drop this unused XHCI_DWC3. Cc: Tianling Shen <cnsztl@gmail.com> Cc: David Bauer <mail@david-bauer.net> Cc: Loic Devulder <ldevulder@suse.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Banglang Huang <banglang.huang@foxmail.com> Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31arm: mvebu: x240: Use i2c-gpio instead of built in controllerChris Packham1-0/+1
There is an Errata with the built-in I2C controller where various I2C hardware errors cause a complete lockup of the CPU (which eventually results in an watchdog reset). Put the I2C MPP pins into GPIO mode and use the i2c-gpio driver instead. This uses a bit-banged implementation of an I2C controller and avoids triggering the Errata. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-31board: rockchip: add Radxa ROCK5A Rk3588 boardEugen Hristev1-0/+72
ROCK 5A is a Rockchip RK3588S based SBC (Single Board Computer) by Radxa. There are tree variants depending on the DRAM size : 4G, 8G and 16G. Specifications: Rockchip Rk3588S SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 4/8/16GB memory LPDDR4x Mali G610MC4 GPU MIPI CSI 2 multiple lanes connector 4-lane MIPI DSI connector Audio – 3.5mm earphone jack eMMC module connector uSD slot (up to 128GB) 2x USB 2.0, 2x USB 3.0 2x micro HDMI 2.1 ports, one up to 8Kp60, the other up to 4Kp60 Gigabit Ethernet RJ45 with optional PoE support 40-pin IO header including UART, SPI, I2C and 5V DC power in USB PD over USB Type-C Size: 85mm x 56mm (Raspberry Pi 4 form factor) Kernel commits: d1824cf95799 ("arm64: dts: rockchip: Add rock-5a board") 991f136c9f8d ("arm64: dts: rockchip: Update sdhci alias for rock-5a") 304c8a759953 ("arm64: dts: rockchip: Remove empty line from rock-5a") cda0c2ea65a0 ("arm64: dts: rockchip: Fix RX delay for ethernet phy on rk3588s-rock5a") Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31rockchip: rk3588-rock-5b: Fix SPI Flash aliasJonas Karlman1-0/+3
The commit fd6e425be243 ("rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash") enabled SPI flash support by adding a spi0 alias. Correct this by adding spi0-spi5 aliases in rk3588s-u-boot.dtsi and SF_DEFAULT_BUS=5 and SPL_DM_SEQ_ALIAS=y in defconfig. Also enabled support for parsing and auto discovery of parameters, SFDP. Fixes: fd6e425be243 ("rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31rockchip: rk3568-rock-3a: Fix SPI Flash aliasJonas Karlman1-0/+3
The commit 64f79f88a751 ("rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash") enabled SPI flash support by overriding the spi0 alias. Correct this by adding a new spi4 alias in rk356x-u-boot.dtsi and SF_DEFAULT_BUS=4 and SPL_DM_SEQ_ALIAS=y in defconfig. Also enabled support for parsing and auto discovery of parameters, SFDP. Fixes: 64f79f88a751 ("rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31rockchip: rk3399-roc-pc: Fix SPL max size and SPI flash payload offsetJonas Karlman2-2/+6
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows for a payload of 3168 KB before env offset start to overlap. Also add CONFIG_ROCKCHIP_SPI_IMAGE=y to build a bootable SPI flash image, u-boot-rockchip-spi.bin. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31rockchip: rk3399-pinephone-pro: Fix SPL max size and SPI flash payload offsetJonas Karlman1-1/+3
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows for a payload of 3168 KB before env offset start to overlap. Also add CONFIG_ROCKCHIP_SPI_IMAGE=y to build a bootable SPI flash image, u-boot-rockchip-spi.bin. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31rockchip: rk3399-pinebook-pro: Fix SPL max size and SPI flash payload offsetJonas Karlman1-1/+3
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows for a payload of 3168 KB before env offset start to overlap. Also add CONFIG_ROCKCHIP_SPI_IMAGE=y to build a bootable SPI flash image, u-boot-rockchip-spi.bin. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31rockchip: rk3399-rockpro64: Fix SPL max size and SPI flash payload offsetJonas Karlman1-3/+2
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows for a payload of 3168 KB before env offset start to overlap. Also remove CONFIG_LTO=y now that there is sufficient space for SPL in SPI flash, and to fix a build issue reported by Peter Robinson. Fixes: 5713135ecc75 ("rockchip: rockpro64: Build u-boot-rockchip-spi.bin") Reported-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31board: rockchip: Add Pine64 SOQuartz on CM4-IOJonas Karlman1-0/+90
The Pine64 SOQuartz compute module is mostly pin-compatible with the RPi CM4 form factor. Therefore, it can slot into the official Raspberry Pi CM4 IO carrier board. Add this configuration to U-Boot. Features tested with a SOQuartz 4GB v1.1 2022-07-11: - SD-card boot - eMMC boot - USB host Device tree is imported from linux v6.4. Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31board: rockchip: Add Pine64 SOQuartz on BladeJonas Karlman1-0/+90
The Pine64 SOQuartz Blade board is a carrier board for the SOQuartz CM4-compatible compute module. It features PoE, an M.2 slot, an SD card slot, HDMI, USB, serial and ethernet. Features tested with a SOQuartz 4GB v1.1 2022-07-11: - SD-card boot - eMMC boot - PCIe/NVMe - USB host Device tree is imported from linux v6.4. Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31board: rockchip: Add Pine64 SOQuartz on Model AJonas Karlman1-0/+90
The Pine64 SOQuartz Model A board is a carrier board for the SOQuartz CM4-compatible compute module. It exposes PCIe, ethernet, USB, HDMI, CSI, DSI, eDP and a 40 pin GPIO header, and is powered by 12V DC. Features tested with a SOQuartz 4GB v1.1 2022-07-11: - SD-card boot - eMMC boot - PCIe/NVMe/AHCI - USB host Device tree is imported from linux v6.4. Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31board: rockchip: Add Pine64 Quartz64-B BoardJonas Karlman1-0/+106
The Pine64 Quartz64 Model B is a credit-card sized single-board computer based on the Rockchip RK3566 SoC. The board features an M.2 PCIe slot, USB3, USB2, eMMC, SD, ethernet, HDMI, analog audio out, a 40 pin GPIO header and a DSI and CSI port, as well as on-board Wi-Fi. Features tested on a Quartz64-B 4GB v1.4 2022-06-06: - SD-card boot - eMMC boot - SPI Flash boot - PCIe/NVMe - USB host Device tree is imported from linux v6.4. Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31board: rockchip: Add Pine64 Quartz64-A BoardJonas Karlman1-0/+110
The Pine64 Quartz64 Model A is a single-board computer based on the Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0, CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a 20 pin GPIO header. Features tested on a Quartz64-A 8GB v2.0 2021-04-27: - SD-card boot - eMMC boot - PCIe/NVMe/AHCI - USB host Device tree is imported from linux v6.4. Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31rockchip: rk3568: Use dwc3-generic driverJonas Karlman4-6/+4
Change RK3568 devices to use the newer dwc3-generic driver instead of the old xhci-dwc3 driver for USB 3.0 support. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31rockchip: chromebook_speedy: Enable soundAlper Nebi Yasak1-0/+5
Commit ec107f04b619 ("rockchip: chromebook_minnie: Enable sound") and commit 2d0c01b8f0ad ("sound: rockchip: Add sound support for jerry") enable audio support for chromebook_minnie and chromebook_jerry. Enable it for chromebook_speedy as well, but put the non-upstream sound node in the board -u-boot.dtsi instead. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31rockchip: chromebook_jerry: Re-enable MAX98090 codec driverAlper Nebi Yasak1-0/+1
Sound support for chromebook_jerry needs the MAX98090 codec driver. This was enabled in commit 2d0c01b8f0ad ("sound: rockchip: Add sound support for jerry"), but apparently lost in commit 7ae2729401bb ("configs: Resync with savedefconfig"). Enable it again. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook_jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31rockchip: veyron: Use TrueType fontsAlper Nebi Yasak2-0/+4
Commit 815ed79d8338 ("video: rockchip: Use TrueType fonts with jerry") enables makes chromebook_jerry use TrueType fonts. Make other veyron boards switch to it as well. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31rockchip: veyron: Add serial, logging, silent console supportAlper Nebi Yasak3-1/+6
Commit eba768c54587 ("rockchip: jerry: Add serial support") enables ROCKCHIP_SERIAL for chromebook_jerry to make the serial console work correctly. Enable it also for other veyron boards. Also enable logging and disable scrolling multiple lines at once as in chromebook_jerry, and enable silent console as chromebook_minnie does. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31rockchip: veyron: Enable RESET driverAlper Nebi Yasak3-0/+3
Commit 70e351bdfeee ("rockchip: jerry: Enable RESET driver") enables DM_RESET for chromebook_jerry to fix its display as required by changes to the Rockchip video drivers. Enable it for other veyron boards as well. Fixes: cd529f7ad62 ("rockchip: video: edp: Add missing reset support") Fixes: 9749d2ea29e ("rockchip: video: vop: Add reset support") Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook_jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31configs: rockchip: drop useless DEBUG_UART_SKIP_INITPegorer Massimo16-16/+0
DEBUG_UART_SKIP_INIT feature is implemented only by s5p (DEBUG_UART_S5P) and pl01x (DEBUG_UART_PL010 or DEBUG_UART_PL011) serial drivers, but all ARCH_ROCKCHIP configs rely on default DEBUG_UART_NS16550. The ns16550 serial driver does not depends on DEBUG_UART_SKIP_INIT, so drop it from rockchip configs. Signed-off-by: Massimo Pegorer <massimo.pegorer@vimar.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31rockchip: rk3308: no DEBUG_UART_BOARD_INIT for ROCK Pi SPegorer Massimo1-0/+1
Call to board_debug_uart_init() is useless, as mainline U-Boot can not build TPL for rk3308, and proprietary ddr.bin to be used as TPL is responsible to init debug uart. Moreover current implementation of board_debug_uart_init() is not compatible with ROCK Pi S, as it sets pins for UART2 channel 1 breaking access to sdmmc due to pinmux conflict. Debug uart for ROCK Pi S is UART0. Thus, avoid ROCKCHIP_RK3308 to select DEBUG_UART_BOARD_INIT and allow to deselct it in rock-pi-s-rk3308_defconfig. The DEBUG_UART_BOARD_INIT is already implied by ARCH_ROCKCHIP, therefore other boards based on rk3308 chip are not affected by change. Signed-off-by: Massimo Pegorer <massimo.pegorer@vimar.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28Merge branch '2023-07-27-TI-K2-K3-updates'Tom Rini11-160/+7
- Resync some of the K3 DTS files with the kernel, and pull in some required related updates to keep drivers in sync with the dts files now. Bring in some incremental fixes on top of one of the series I applied recently as well as updating the iot2050 platform. Also do a few small updates to the K2 platforms.
2023-07-28configs: keystone2: Unwind KERNEL_MTD_PARTS definitionAndrew Davis8-8/+0
This is more complex than it needs to be and makes converting these boards over to plain text env files more difficult. Remove setting mtdparts as the DTS already contain the partitions. While here also drop the conflicting definitions from the K2 defconfigs. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-07-28configs: am62x: add SPL_MAX_SIZE backManorit Chawdhry1-0/+1
This was regressed by the following commit and is required to build with additional configs enabled. Fixes: 14439cd71c1a ("configs: k3: make consistent bootcmd across all k3 socs") Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Tested-by: Nikhil M Jain <n-jain1@ti.com>
2023-07-28configs: iot2050: Enabled keyed autobootJan Kiszka1-0/+4
Only accept SPACE to stop autobooting. This is safer to avoid accidental interruptions on unattended devices. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2023-07-28boards: siemens: iot2050: Unify PG1 and PG2/M.2 configurations againJan Kiszka2-153/+1
This avoids having to maintain to defconfigs that are 99% equivalent. The approach is to use binman to generate two flash images, flash-pg1.bin and flash-pg2.bin. With the help of a template dtsi, we can avoid duplicating the common binman image definitions. Suggested-by: Andrew Davis <afd@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2023-07-28boards: siemens: iot2050: Fix boot configurationJan Kiszka2-0/+2
The common env bits now come via ti_armv7_common.env, include it. Furthermore restore the board-specific boot targets and their ordering that is now enforced k3-wide differently. Finally, enable CONFIG_LEGACY_IMAGE_FORMAT explicitly which got lost while turning FIT_SIGNATURE on by default for k3 devices. Fixes: 53873974 ("include: armv7: Enable distroboot across all configs") Fixes: 4ae1a247 ("env: Make common bootcmd across all k3 devices") Fixes: 86fab110 ("Kconfig: Enable FIT_SIGNATURE if ARM64") Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2023-07-28board: rockchip: Add Hardkernel ODROID-M1Jonas Karlman1-0/+111
Hardkernel ODROID-M1 is a single board computer with a RK3568B2 SoC, a slightly modified version of the RK3568 SoC. Features tested on a ODROID-M1 8GB v1.0 2022-06-13: - SD-card boot - eMMC boot - SPI Flash boot - PCIe/NVMe/AHCI - SATA port - USB host Device tree is imported from linux v6.4. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Stefan Agner <stefan@agner.ch> Tested-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: rk3568-rock-3a: Enable PCIe and NVMe supportJonas Karlman1-0/+9
Add missing pinctrl and defconfig options to enable PCIe and NVMe support on Radxa ROCK 3 Model A. Use of pcie20m1_pins and pcie30x2m1_pins ensure IO mux selection M1. The following pcie_reset_h and pcie3x2_reset_h ensure GPIO func is restored to the perstn pin, a workaround to avoid having to define a new rockchip,pins. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: veyron: Enable Winbond SPI flashAlper Nebi Yasak4-0/+4
Some veyron boards seem to have Winbond SPI flash chips instead of GigaDevice ones. At the very least, coreboot builds for veyron boards have them enabled [1]. Enable support for them here as well. [1] https://review.coreboot.org/c/coreboot/+/9719 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28arm: rockchip: Add Radxa ROCK 4SEChristopher Obbard1-0/+100
Add board-specific devicetree/config for the RK3399T-based Radxa ROCK 4SE board. This board offers similar peripherals in a similar form-factor to the existing ROCK Pi 4B but uses the cost-optimised RK3399T processor (which has different OPP table than the RK3399) and other minimal hardware changes. Kernel tag: next-20230719 Kernel commits: - 86a0e14a82ea ("arm64: dts: rockchip: Add Radxa ROCK 4SE") Signed-off-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28configs: evb-rk3229: Increase SPL_STACK_R_MALLOC_SIMPLE_LENAlex Bee1-1/+1
An OP-TEE FIT image will fail to extract in SPL because the malloc stack size is currently limited to 0x2000 for evb-rk3229 board. In SPL we do not have to care about size limitations, since we are no longer bound to SRAM limits after DRAM initialization has been done in TPL. Use the default value for CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN in order successfully unpack the FIT image. Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28configs: rockchip: rock5b-rk3588: Enable CONFIG_PCI_INIT_RChristopher Obbard1-0/+1
Enable CONFIG_PCI_INIT_R for rock5b pci enumeration during boot in order to autodetect the PCI ethernet NIC during the boot process. Signed-off-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: puma: pass platform parameter to TF-AQuentin Schulz1-1/+0
Puma supports upstream TF-A and is configured to output serial on UART0 instead of the default UART2. Since U-Boot is properly configured to output on UART0, let's pass the DT to TF-A so there is no need for a custom TF-A to make the latter output to UART0 too. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: rk3399: pass platform parameter to TF-A by default for new RK3399 ↵Quentin Schulz28-0/+28
boards Long are gone the times TF-A couldn't handle the FDT passed by U-Boot. Specifically, since commit e7b586987c0a ("rockchip: don't crash if we get an FDT we can't parse") in TF-A, failure to parse the FDT will use the fallback mechanism. This patch was merged in TF-A v2.4-rc0 from two years ago. New boards should likely have this option disabled or explicitly enable it in their respective defconfig. Because existing boards might depend on a TF-A version that predates v2.4, let's just enable this option in all RK3399 defconfigs. Maintainers of each board can decide for themselves if they would prefer to disable this option and allow U-Boot to pass the DT to TF-A. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28board: rockchip: Add Edgeble Neural Compute Module 6BJagan Teki1-0/+64
Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module based on Rockchip RK3588J from Edgeble AI. Add support for this SoM and IO board. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: rk3568: Add support for FriendlyARM NanoPi R5CTianling Shen1-0/+85
FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device. Specification: - Rockchip RK3568 - 1/4GB LPDDR4X RAM - 8/32GB eMMC - SD card slot - M.2 Connector - 2x USB 3.0 Port - 2x 2500 Base-T (PCIe, r8125) - HDMI 2.0 - MIPI DSI/CSI - USB Type C 5V The device tree is taken from kernel v6.4-rc1. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
2023-07-28rockchip: rk3568: Add support for FriendlyARM NanoPi R5STianling Shen1-0/+85
FriendlyARM NanoPi R5S is an open-sourced mini IoT gateway device. Board Specifications - Rockchip RK3568 - 2 or 4GB LPDDR4X - 8GB or 16GB eMMC, SD card slot - GbE LAN (Native) - 2x 2.5G LAN (PCIe) - M.2 Connector - HDMI 2.0, MIPI DSI/CSI - 2xUSB 3.0 Host - USB Type C PD, 5V/9V/12V - GPIO: 12-pin 0.5mm FPC connector The device tree is taken from kernel v6.4-rc1. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
2023-07-28rockchip: rk3328: Add support for Orange Pi R1 Plus LTSTianling Shen1-0/+114
The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with the on-board NIC chip changed from rtl8211e to yt8531c, and RAM type changed from DDR4 to LPDDR3. The device tree is taken from kernel v6.4-rc1. Signed-off-by: Tianling Shen <cnsztl@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: rk3328: Add support for Orange Pi R1 PlusTianling Shen1-0/+114
Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong. This device is similar to the NanoPi R2S, and has a 16MB SPI NOR (mx25l12805d). The reset button is changed to directly reset the power supply, another detail is that both network ports have independent MAC addresses. The device tree and description are taken from kernel v6.3-rc1. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
2023-07-28configs: Update anbernic-rgxx3_defconfig for panel detectionChris Morgan1-0/+15
Update the anbernic-rgxx3_defconfig file to support panel autodetection and automatically updating the compatible string in the devicetree. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28configs: rock5b-rk3588: enable USB 3.0 controller, command, gadgetEugen Hristev1-0/+14
Enable configuration for USB 3.0 controller, the commands required, and the gadget drivers. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 23:58:58 +0000