platform/kernel/u-boot - Domain: System / Kernel;

Age	Commit message (Expand)	Author	Files	Lines
2019-07-16	efi_loader: use predefined constants in crt0_*_efi.S	Heinrich Schuchardt	1	-6/+5
2019-06-05	riscv: Add Microchip MPFS Icicle board support	Padmarao Begari	1	-0/+4
2019-05-18	CONFIG_SPL_SYS_[DI]CACHE_OFF: add	Trevor Woerner	2	-4/+18
2019-05-18	CONFIG_SYS_[DI]CACHE_OFF: convert to Kconfig	Trevor Woerner	1	-0/+12
2019-05-09	RISCV: image: Add booti support	Atish Patra	2	-0/+56
2019-05-09	riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...	Rick Chen	2	-0/+4
2019-05-09	riscv: Introduce CONFIG_XIP to support booting from flash	Rick Chen	6	-0/+21
2019-04-12	dts: switch spi-flash to jedec, spi-nor compatible	Neil Armstrong	2	-2/+2
2019-04-08	riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failure	Rick Chen	1	-0/+2
2019-04-08	riscv: dts: ae350 support SMP	Rick Chen	2	-44/+118
2019-04-08	riscv: ax25: Andes specific cache shall only support in M-mode	Rick Chen	1	-0/+1
2019-04-08	riscv: ax25: Add platform-specific Kconfig options	Rick Chen	1	-0/+6
2019-04-08	riscv: Add a SYSCON driver for Andestech's PLMT	Rick Chen	5	-0/+67
2019-04-08	riscv: Add a SYSCON driver for Andestech's PLIC	Rick Chen	5	-2/+127
2019-04-08	riscv: hang if relocation of secondary harts fails	Lukas Auer	1	-1/+12
2019-04-08	riscv: do not rely on hart ID passed by previous boot stage	Lukas Auer	1	-0/+4
2019-04-08	riscv: boot images passed to bootm on all harts	Lukas Auer	1	-1/+12
2019-04-08	riscv: add support for multi-hart systems	Lukas Auer	5	-2/+147
2019-04-08	riscv: save hart ID in register tp instead of s0	Lukas Auer	1	-2/+2
2019-04-08	riscv: delay initialization of caches and debug UART	Lukas Auer	1	-8/+8
2019-04-08	riscv: implement IPI platform functions using SBI	Lukas Auer	3	-0/+31
2019-04-08	riscv: import the supervisor binary interface header file	Lukas Auer	1	-0/+94
2019-04-08	riscv: add infrastructure for calling functions on other harts	Lukas Auer	5	-0/+197
2019-02-27	riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrd	Anup Patel	1	-0/+1
2019-02-27	riscv: Add SiFive FU540 board support	Anup Patel	1	-0/+4
2019-02-27	riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems	Anup Patel	1	-0/+20
2019-02-27	riscv: Add place-holder asm/arch/clk.h for driver compilation	Anup Patel	1	-0/+14
2019-02-27	riscv: Add asm/dma-mapping.h for DMA mappings	Anup Patel	1	-0/+38
2019-02-27	riscv: Rename cpu/qemu to cpu/generic	Anup Patel	5	-2/+2
2019-01-15	riscv: qemu: define standalone load address	Lukas Auer	1	-1/+1
2019-01-15	riscv: remove RISC-V standalone linker script	Lukas Auer	1	-1/+0
2019-01-15	riscv: use invalidate/flush_*cache_range functions in cache.c	Lukas Auer	1	-2/+2
2019-01-15	riscv: move the AX25-specific implementation of flush_dcache_all	Lukas Auer	2	-6/+26
2019-01-15	riscv: clarify error message on undefined exceptions	Lukas Auer	1	-1/+2
2018-12-31	riscv: bootm: Support booting VxWorks	Bin Meng	1	-1/+7
2018-12-18	riscv: Remove ae350.dts	Bin Meng	1	-229/+0
2018-12-18	riscv: bootm: Change to use boot_hart from global data	Bin Meng	1	-1/+1
2018-12-18	riscv: Save boot hart id to the global data	Bin Meng	3	-0/+24
2018-12-18	riscv: Adjust the _exit_trap() position to come before handle_trap()	Bin Meng	1	-32/+30
2018-12-18	riscv: Return to previous privilege level after trap handling	Bin Meng	1	-8/+0
2018-12-18	riscv: Fix context restore before returning from trap handler	Bin Meng	1	-1/+1
2018-12-18	riscv: Move trap handler codes to mtrap.S	Bin Meng	3	-90/+112
2018-12-18	riscv: Do some basic architecture level cpu initialization	Bin Meng	1	-1/+26
2018-12-18	riscv: Add indirect stringification to csr_xxx ops	Bin Meng	1	-7/+9
2018-12-18	riscv: Update supports_extension() to use desc from cpu driver	Bin Meng	1	-0/+26
2018-12-18	riscv: Add exception codes for xcause register	Bin Meng	1	-0/+15
2018-12-18	riscv: Add CSR numbers	Bin Meng	1	-0/+221
2018-12-18	riscv: Remove non-DM version of print_cpuinfo()	Bin Meng	1	-37/+0
2018-12-18	riscv: Probe cpus during boot	Bin Meng	2	-0/+27
2018-12-18	riscv: Enlarge the default SYS_MALLOC_F_LEN	Bin Meng	1	-0/+3