platform/kernel/u-boot - Domain: System / Kernel;

Age	Commit message (Expand)	Author	Files	Lines
2023-12-27	andes: cpu: Enable cache and TLB ECC support	Leo Yu-Chi Liang	2	-1/+5
2023-12-27	andes: cpu: Enable memboost feature	Leo Yu-Chi Liang	2	-1/+14
2023-12-27	andes: ae350: Implement cache switch via Kconfig	Leo Yu-Chi Liang	1	-9/+16
2023-12-27	andes: csr.h: Clean up CSR definition	Leo Yu-Chi Liang	2	-12/+9
2023-12-27	riscv: Extend board compatible string with "qemu,mbv"	Michal Simek	1	-1/+1
2023-12-27	riscv: cache: support cache enable in SPL stage	Zong Li	1	-0/+21
2023-12-21	Merge patch series "Complete decoupling of bootm logic from commands"	Tom Rini	3	-10/+21
2023-12-21	bootm: Adjust arguments of boot_os_fn	Simon Glass	1	-5/+6
2023-12-21	riscv: Add a reset_cpu() function	Simon Glass	2	-5/+15
2023-12-21	global: Rework architecture global_data.h to include <linux/types.h>	Tom Rini	1	-0/+1
2023-12-18	Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv ...	Tom Rini	4	-0/+117
2023-12-18	Merge tag 'v2024.01-rc5' into next	Tom Rini	3	-28/+29
2023-12-18	riscv: Add support for AMD/Xilinx MicroBlaze V	Michal Simek	3	-0/+112
2023-12-18	riscv: dts: jh7110: Add a gpio-restart node	Jaehoon Chung	1	-0/+5
2023-12-06	riscv: binman: fix the load field format	Randolph	1	-10/+4
2023-12-06	riscv: andes: Fix enable register settings of PLICSW	Yu Chien Peter Lin	1	-18/+15
2023-12-05	riscv: dts: jh7110: Add watchdog device tree node	Chanho Park	1	-0/+10
2023-11-28	riscv: io.h: Fix signatures of reads/writes functions	Igor Prusov	1	-6/+12
2023-11-28	riscv: io.h: Add defines for reads/writes functions	Igor Prusov	1	-0/+8
2023-11-02	riscv: dts: jh7110: Add rng device tree node	Chanho Park	1	-0/+10
2023-11-02	riscv: import read/write_relaxed functions	Chanho Park	1	-0/+45
2023-11-02	riscv: allow resume after exception	Heinrich Schuchardt	1	-0/+13
2023-11-02	riscv: cpu: jh7110: Add gpio helper macros	Chanho Park	1	-0/+85
2023-11-02	riscv: Weakly define invalidate_icache_range()	Samuel Holland	1	-1/+1
2023-11-02	riscv: Align the trap handler to 64 bytes	Samuel Holland	1	-1/+1
2023-11-02	riscv: Sort target configs alphabetically	Samuel Holland	1	-9/+9
2023-10-30	Kconfig: Remove all default n/no options	Michal Simek	1	-1/+0
2023-10-24	riscv: Remove common.h usage	Tom Rini	31	-29/+8
2023-10-22	sunxi: dts: arm: add T113s/D1 DT files from Linux-v6.6-rc6	Andre Przywara	2	-0/+942
2023-10-19	riscv: Add Zbb support for building U-Boot	Yu Chien Peter Lin	7	-1/+392
2023-10-19	riscv: dts: binman: add condition for opensbi os boot	Randolph	1	-0/+24
2023-10-19	riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol	Randolph	1	-0/+8
2023-10-19	riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy	Randolph	1	-13/+11
2023-10-19	riscv: binman: Fix compilation error	Mayuresh Chitale	1	-4/+10
2023-10-19	riscv: remove dram_init_banksize()	Heinrich Schuchardt	1	-16/+0
2023-10-04	riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode	Yu Chien Peter Lin	1	-1/+2
2023-10-04	configs: andes: add vender prefix for target name	Randolph	2	-3/+3
2023-10-04	riscv: enable CONFIG_DEBUG_UART by default	Heinrich Schuchardt	1	-0/+1
2023-10-04	riscv: bootstage: correct bootstage_report guard	Chanho Park	1	-1/+1
2023-10-02	Merge branch 'next'	Tom Rini	6	-11/+22
2023-09-26	riscv: set fdtfile on VisionFive 2	Heinrich Schuchardt	1	-0/+1
2023-09-24	common: Drop linux/printk.h from common header	Simon Glass	1	-0/+1
2023-09-22	Record the position of the SMBIOS tables	Simon Glass	1	-0/+3
2023-09-20	riscv: dts: starfive: generate u-boot-spl.bin.normal.out	Heinrich Schuchardt	1	-0/+11
2023-09-20	riscv: set fdtfile on VisionFive 2	Heinrich Schuchardt	1	-0/+1
2023-09-06	riscv: Correct event usage for riscv_cpu_probe/setup	Tom Rini	1	-5/+1
2023-09-06	riscv: Rework riscv_cpu_probe for current event macros	Tom Rini	1	-2/+2
2023-09-05	risc-v: implement DBCN write byte	Heinrich Schuchardt	2	-0/+17
2023-09-05	riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT	Shengyu Qu	1	-0/+1
2023-09-05	riscv: jh7110: enable riscv,timer in the device tree	Torsten Duwe	1	-0/+9