summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2017-06-07configs: rk3328: add support for usb and config ehci and ohci driverMeng Dongyang2-0/+11
Add defconfig for usb and ehci and ohci controller, config maximal number of ports of the root hub for ohci driver. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: pinctrl: rk3328: do not set io routingKever Yang2-34/+43
In rk3328, some function pin may have more than one choice, and muxed with more than one IO, for example, the UART2 controller IO, TX and RX, have 3 choice(setting in com_iomux): - M0 which mux with GPIO1A0/GPIO1A1 - M1 which mux with GPIO2A0/GPIO2A1 - usb2phy which mux with USB2.0 DP/DM pin. We should not decide which group to use in pinctrl driver, for it may be different in different board, it should goes to board file, and the pinctrl file should setting correct iomux depends on the com_iomux value. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: pinctrl: move rk3328 grf reg definition in header fileKever Yang2-155/+164
Move GRF register bit definition into GRF header file, remove 'GRF_' prefix and add 'GPIOmXn_' as prefix for bit meaning. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: rk3036: clean mask definition for grf regKever Yang2-95/+82
U-Boot prefer to use MASKs with SHIFT embeded, clean the Macro definition in grf header file and pinctrl driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: clock: rk3036: some fix according TRMKever Yang2-12/+12
- hclk/pclk_div range　should use '<=' instead of '<' - use GPLL for pd_bus clock source - pd_bus HCLK/PCLK clock rate should not bigger than ACLK Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: rk3036: clean mask definition for cru regKever Yang2-80/+69
Embeded the shift in mask MACRO definition in cru header file and clock driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: rk3368: Add PX5 Evaluation boardAndy Yan10-0/+457
PX5 EVB is designed by Rockchip for automotive field with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS HDMI video input/output interface, audio codec ES8396, WIFI / BT (on RTL8723BS), Gsensor BMA250E and light&proximity sensor STK3410. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: rk3368: Add initial support for RK3368 based GeekBoxAndreas Färber10-0/+421
The GeekBox is a TV box from GeekBuying, based on an MXM3 module. The module can be used with base boards such as the GeekBox Landingship. This adds basic support to chain-load U-Boot from Rockchip's miniloader. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: rk3368: add Sheep boardAndy Yan10-0/+453
Sheep board is designed by Rockchip as a EVB for rk3368. Currently it is able to boot a linux kernel and system to console with the miniloader run as fist level loader. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2017-06-07rockchip: rk3368: Add sysreset driverAndy Yan2-0/+63
Add sysreset driver to reset rk3368 SOC. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: rk3368: Add core start-up code for RK3368Andreas Färber10-0/+1693
The RK3368 is an octa-core Cortex-A53 SoC from Rockchip. This adds basic support to chain-load U-Boot from Rockchip's miniloader. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: rk3368: Add pinctrl driverAndy Yan4-0/+600
Add driver to support iomux setup for the most commonly used peripherals on rk3368. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: rk3368: Add clock driverAndy Yan3-0/+416
Add driver to setup the various PLLs and peripheral clocks on the RK3368. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07regulator: pwm: Fix handling of missing init voltageMark Kettenis1-4/+4
Since priv->init_voltage is an unsigned integer it can never be negative. So the current code fails to detect a missing 'regulator-init-microvolt' property and instead misconfigures the PWM device. Fix this by making the relevant members of 'struct pwm_regulator_info' signed integers. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2017-06-07power: rk808: fix ldo register offsetHeiko Stübner1-2/+2
Till now get_ldo_reg did a return &rk808_ldo[num - 1]; to return the ldo register offset but didn't take into account that its calling functions already created the ldo as ldo = dev->driver_data - 1. This resulted in the setting for ldo8 writing to the register of ldo7 and so on. So fix this and get the correct ldo register data. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: board: puma_rk3399: build FIT image via u-boot.itbPhilipp Tomsich2-3/+3
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: defconfig: puma-rk3399: enable RK3399 efuse driverPhilipp Tomsich1-0/+2
With everything in place (i.e. the new efuse driver, the clk-support for the non-secure efuse block, and the board-specific functions to derive 'serial#' from the cpu-id within the efuses), enable this in the RK3399-Q7 defconfig. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: board: puma_rk3399: derive ethaddr from cpuidKlaus Goger1-2/+40
Generate a MAC address based on the cpuid available in the efuse block: Use the first 6 byte of the cpuid's SHA256 hash and set the locally administered bits. Also ensure that the multicast bit is cleared. The MAC address is only generated and set if there is no ethaddr present in the saved environment. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: board: puma_rk3399: add support for serial# and cpuid# via efusesPhilipp Tomsich2-0/+84
With our efuse driver for the RK3399 ready, we can add the board-specific code that consumes the cpuid from the efuse block and postprocesses it into the system serial (using the same CRC32 based derivation as in Linux). We expose the cpuid via two distinct environment variables: serial# - the serial number, as derived in Linux cpuid# - the raw 16 byte CPU id field from the fuse block Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: efuse: add (misc) driver for RK3399 non-secure efuse blockPhilipp Tomsich3-0/+175
This adds a simple driver for reading the efuse block of the RK3399. It should be easy enough to add drivers for other devices (e.g. the RK3328, RK3368, etc.) by passing the device details via driver_data. Unlike the kernel driver (using the nvmem subsystem), we don't expose the efuse as multiple named cells, but rather as a linear memory that can be read using misc_read(...). The primary use case (as of today) is the generation of a 'serial#' (and a 'cpuid#') environment variable for the RK3399-Q7 (Puma) system-on-module. Note that this adds a debug-only (i.e. only if DEBUG is defined) command 'rk3399_dump_efuses' that dumps the efuse block's content. N.B.: The name 'rk3399_dump_efuses' was intentionally chosen to include a SoC-name (together with a comment in the function) to remind whoever adds support for additional SoCs that this function currently makes assumptions regarding the size of the fuse-box based on the RK3399. The hope is that the function is adjusted to reflect any changes resulting from generalising the driver for multiple SoCs and is then renamed. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: rk8xx: allocate priv structure for driverKever Yang1-0/+1
The rk8xx_priv structure need to allocate for driver, or else it will cause data abort when CPU access it. This is a bug fix for below patch set: https://www.mail-archive.com/u-boot@lists.denx.de/msg247345.html Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip; rk3399: disable SRAM security regionKever Yang1-3/+5
Some host like SD and eMMC may use DMA to transter data to SRAM, set memory to non-secure to make sure the address can be accessed. The security of SRAM in OS suppose to initialized in ATF bl31, and the SPL is before the bl31. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07defconfig: firefly-rk3399: fix pinctrl config optionHeiko Stübner1-1/+1
The option is named PINCTRL_ROCKCHIP_RK3399 not ROCKCHIP_RK3399_PINCTRL. Set the correct option. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
2017-06-06Merge git://git.denx.de/u-boot-ubiTom Rini1-1/+1
2017-06-06fs: usbifs: Fix warning in ubifsSiva Durga Prasad Paladugu1-1/+1
This patch fixes the below warning by typecasting it properly fs/ubifs/ubifs.c: In function 'ubifs_load': fs/ubifs/ubifs.c:942:29: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] err = ubifs_read(filename, (void *)addr, 0, size, &actread); Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2017-06-05Merge git://git.denx.de/u-boot-usbTom Rini3-1/+171
2017-06-05Prepare v2017.07-rc1v2017.07-rc1Tom Rini1-2/+2
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-05armv7m: Fix larger buildsPhil Edworthy1-1/+3
The branch instruction only has an 11-bit relative target address, which is sometimes not enough. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
2017-06-05arm: Add Kconfig symbols used for Linux asm compatibilityPhil Edworthy2-2/+10
Rather than change asm files that come from Linux, add the symbols to Kconfig. Since one of the symbols is for thumb2 builds, make CPU_V7M always select them. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
2017-06-05arm64: hikey: Fix instructions in readmeMichal Simek1-4/+4
Fix inaccurate instructions in README. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-05drivers: ram: stm32: fix compilation issuePatrice Chotard1-1/+1
If CONFIG_CLK flag is not set, compilation raises the following error message: drivers/ram/stm32_sdram.c: In function 'stm32_fmc_probe': drivers/ram/stm32_sdram.c:154:2: error: 'ret' undeclared (first use in this function) ret = stm32_sdram_init(dev); Signed-off-by: Patrice Chotard <patrice.chotard@st.com> cc: Vikas Manocha <vikas.manocha@st.com>
2017-06-05arm64: Add NOLOAD attribute NOLOAD to .bss sectionsMichal Simek1-3/+3
Mark explicitly bss sections to not be loaded at run time. The similar patch was done in past by: "Fix linker scripts: add NOLOAD atribute to .bss/.sbss sections" (sha1: 64134f011254123618798ff77c42ba196b2ec485) The problem is related to latest toolchain added to Xilinx v2017.1 design tools where jtag loader is trying to access ununitialized memory. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-05ARMv8: Add support for poweroff via PSCIMichal Simek1-0/+17
Add support for calling poweroff in case of psci is wired. Based on the same solution as is used for reset. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Move all logic in to fwcall.c as other ARMs implement poweroff via PMIC] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-05cmd/ethsw: Disable implicit enum conversion warningTom Rini1-0/+2
With clang-3.8 we see warnings like: cmd/ethsw.c:304:6: warning: implicit conversion from enumeration type 'enum ethsw_keyword_opt_id' to different enumeration type 'enum ethsw_keyword_id' [-Wenum-conversion] ethsw_id_pvid_no, ^~~~~~~~~~~~~~~~ Because we have one enum for ethsw_keyword_id and a second enum for ethsw_keyword_opt_id. This ends up being safe as ethsw_keyword_opt_id explicitly starts after ethsw_keyword_id enum ends. Disable the warning here rather than collapse these into one enum and rely on comments to denote where optional keywords begin. Cc: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-05malloc: Turn on DEBUG when enabling unit testsPantelis Antoniou1-1/+1
Unit tests require mallinfo which in turn requires DEBUG on dlmalloc to be enabled. The dependancy on CONFIG_SANDBOX is wrong. Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-05arm: Always keep the dtb section on objcopyPantelis Antoniou1-2/+4
The dtb blob section must always be present in the resulting image. Either if OF_EMBEDED is used or if unit tests include dtb blobs. Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-05board: ti: am571-idx: Add vcores supportKeerthy1-0/+50
Update vcores for am571-idk board. Reported-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-06-05scripts/Makefile.lib: Only apply u-boot.dtsi files in the target directoryTom Rini1-7/+5
We only want to apply files such as 'omap5-u-boot.dtsi', which resides in arch/arm/dts/ to other files in arch/arm/dts/ and not say test/overlay/. Rework the make logic to check for -u-boot.dtsi files in the same directory as their target dts. Cc: Simon Glass <sjg@chromium.org> Reported-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-05ARM: ti: Update layout for MMC and eMMC (env and dfu)Jean-Jacques Hiblot4-10/+13
The problems with the current DFU layout are: MMC: The space allocated for u-boot is too small for the latest u-boot (>750KB). We need to increase it. eMMC uses a much bigger area (2MB). eMMC: region "u-boot.img.raw" overlaps the environment area and the region "spl-os-image.raw". both: region "spl-os-image.raw" is quite small and can't handle android kernels Fixing this requires growing some regions and moving others. Care has been taken to leave some room for further growth of "spl-os-args.raw". Also the "env" now appears in the dfu so that it's apparent that the region is not free space that can be used to grow "u-boot.img.raw". The MLO region is 0x100 sectors wide but the 0x100 are unused in case the MLO comes too overflow this areas. The total space allocated for those raw binaries is 16MB, of which 13+MB are reserved for the kernel image. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-06-05common/spl/Kconfig: Use 'if SPL' / 'if TPL' guardsTom Rini1-72/+24
Much of the entries here simply depend on SPL (or TPL). Instead of this redundancy use if SPL / if TPL to guard the rest of the choices and only show them when we have the relevant option enabled. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-05bootstage: Record time taken to set up the live device treeSimon Glass2-2/+10
This time is interesting as a comparision with the flat device tree time. Add it to the record. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05bootstage: Support SPLSimon Glass5-5/+57
At present bootstage only supports U-Boot proper. But SPL can also consume boot time so it is useful to have the record start there. Add bootstage support to SPL. Also support stashing the timing information when SPL finishes so that it can be picked up and reported by U-Boot proper. This provides a full boot time record, excluding only the time taken by the boot ROM. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05bootstage: Adjust to use const * where possibleSimon Glass2-8/+8
There are a few places that should use const *, such as bootstage_unstash(). Update these to make it clearer when parameters are changed. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05bootstage: Tidy up error return valuesSimon Glass2-12/+14
We should return a proper error number instead of just -1. This helps the caller to determine what when wrong. Update a few functions to fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05bootstage: Record the time taken to set up driver modelSimon Glass3-0/+6
Driver model is set up ones before relocation and once after. Record the time taken in each case. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05bootstage: Init as early as possibleSimon Glass2-3/+2
At present we don't allow use of bootstage before driver model is running. This means we cannot time the init of driver model itself. Now that bootstage requires its own board-specific timer, we can move its init to earlier in the sequence, both before and after relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05bootstage: Support relocating boostage dataSimon Glass4-0/+52
Some boards cannot access pre-relocation data after relocation. Reserve space for this and copy it during preparation for relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05bootstage: Use debug() for stashing messagesSimon Glass1-2/+2
We don't normally want to see these messages. Change them to debug-only. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05bootstage: Show records with a zero timeSimon Glass1-7/+4
We can now use the record count to determine whether a record is valid or not. Drop the test for a zero time. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05bootstage: Use rec_count as the array indexSimon Glass2-49/+96
At present bootstage has a large array with all possible bootstage IDs recorded. It adds times to the array element indexed by the ID. This is inefficient because many IDs are not used during boot. We can save space by only recording those IDs which actually have timestamps. Update the array to use a record count, which increments with each addition of a new timestamp. This takes longer to record a time, since it may involve an array search. Such a search may be particularly expensive before relocation when the CPU is running slowly or the cache is off. But at that stage there should be very few records. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 02:01:37 +0000