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2020-08-03liebherr: Drop duplicate dm.h inclusionSimon Glass1-1/+0
We only need to include this header once. Drop the duplicate. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03ti: am654: Drop duplicate dm.h inclusionSimon Glass1-1/+0
We only need to include this header once. Drop the duplicate. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03spi: Drop duplicate dm.h inclusionSimon Glass1-1/+0
We only need to include this header once. Drop the duplicate. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03mmc: Drop duplicate dm.h inclusionSimon Glass1-1/+0
We only need to include this header once. Drop the duplicate. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03power: Tidy up inclusion of regulator_common.hSimon Glass4-5/+7
This file should not include common.h and dm.h so remove them. Also move the inclusion of this file to after the normal includes. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-08-03efi: Tidy up header includesSimon Glass3-2/+3
Two files relies on efi_driver.h to include common.h and dm.h which is incorrect. The former should always be included in a non-host C file and the latter should be included if driver model is used. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03w1: Drop dm.h header fileSimon Glass3-1/+3
This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03thermal: Drop dm.h header fileSimon Glass2-1/+2
This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03sf: Drop dm.h header file from spi_flash.hSimon Glass5-1/+6
This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03net: Drop dm.h header file from phy.hSimon Glass6-3/+12
This header file should not be included in other header files. Remove it and use other headers and C inclusions instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03fs: fs-loader: Drop dm.h header fileSimon Glass2-1/+2
This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03dm: core: Drop header files from dm/test.hSimon Glass63-20/+82
These header file should not be included in other header files. Remove them and add to each individual file. Add test/test.h to test/ui.h since that is a reasonable place. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03dm: core: Drop dm.h header file from dm-demo.hSimon Glass2-2/+1
This header file should not be included in other header files. Remove it and add it to the cmd file instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03mtd: spi: Drop SPI_XFER_MMAP*Simon Glass1-2/+0
These two defines are no-longer supported. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03mtd: spi-mem: Drop dm.h header fileSimon Glass4-5/+10
This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03wdt: Drop dm.h header fileSimon Glass1-3/+1
This header file should not be included in other header files. Remove it and use a forward declaration instead. Also remove the other headers that are not needed, since the inline code was removed in a recent commit: b4d9452c4 ("watchdog: move initr_watchdog() to wdt-uclass.c") Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03mtd: spi-nor: Tidy up error handling / debug codeSimon Glass3-4/+4
The -ENODEV error value in spi_nor_read_id() is incorrect since there clearly is a device - it just cannot be supported. Use -ENOMEDIUM instead which has the virtue of being less common. Fix the return value in spi_nor_scan(). Also there are a few printf() statements which should be debug() since they bloat the code with unused strings at present. Fix those while here. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03spi: Allow separate control of SPI_FLASH_TINY for SPL/TPLSimon Glass2-1/+11
In some cases SPL needs to be able to erase but TPL just needs to read. Allow these to have separate settings for SPI_FLASH_TINY. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-04configs: reset: fu540: enable dm reset framework for SiFiveSagar Shrikant Kadam3-0/+12
Add necessary defconfig and Kconfig entries to enable SiFive SoC's reset driver so as to utilise U-Boot's reset framework. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2020-08-04sifive: reset: add DM based reset driver for SiFive SoC'sSagar Shrikant Kadam3-15/+189
PRCI module within SiFive SoC's has register with which we can reset the sub-systems within the SoC. The resets to DDR and ethernet sub systems within FU540-C000 SoC are active low, and are hold low by default on power-up. Currently these are directly asserted within prci driver via register read/write. With the DM based reset driver support here, we bind the reset driver with clock (prci) driver and assert the reset signals of both sub-system's appropriately. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2020-08-04fu540: dtsi: add reset producer and consumer entriesSagar Shrikant Kadam1-0/+12
The resets to DDR and ethernet sub-system are connected to PRCI device reset control register, these reset signals are active low and are held low at power-up. Add these reset producer and consumer details needed by the reset driver. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-08-04fu540: prci: use common reset indexes defined in binding headerSagar Shrikant Kadam1-10/+7
Indexes of reset signals available in PRCI driver are also defined in include/dt-bindings/reset/sifive-fu540-prci.h. So use those instead of defining new ones again within the fu540-prci driver. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-08-04dt-bindings: prci: add indexes for reset signals available in prciSagar Shrikant Kadam1-0/+19
Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC. The DDR and ethernet sub-system's have reset signals indicated by these reset indexes. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-08-03video: ipuv3: fix framebuffer base address init with multiple IPUsAnatolij Gustschin1-4/+9
Since commit 7812bbdc3732 ("video: Correctly handle multiple framebuffers") the vidconsole output is missing on the primary display on boards with two IPU units (all i.MX6Q/D based boards). The base address of the allocated framebuffer is not correctly programmed in the display controller. Fix it. Reported-by: Soeren Moch <smoch@web.de> Signed-off-by: Anatolij Gustschin <agust@denx.de> Tested-by: Soeren Moch <smoch@web.de>
2020-08-03board: tbs2910: Fix video output with existing environmentsSoeren Moch1-0/+1
Migration to DM_VIDEO changed the output device name (in stout, stderr) from 'vga' to 'vidconsole'. This also was adapted in the default environment. However, existing user defined environments still use 'vga'. Enable this workaround to map the 'vga' name to 'vidconsole'. So we get HDMI video output also with existing legacy environments. Signed-off-by: Soeren Moch <smoch@web.de>
2020-08-03mips: octeon: Update EBB7304 defconfigStefan Roese1-1/+11
This patch enables the following options for the Octeon EBB7304 EVB: - PCI & DM_PCI - DM_SPI_FLASH & SPI flash device support - SPI & Octeon SPI driver - GPIO cmd support - I2C cmd support Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03mips: octeon: Update Octeon KconfigStefan Roese1-2/+4
This patch selects DM_SPI & DM_I2C for MIPS Octeon. DM_GPIO, DM_SERIAL and DM_ETH are already selected. Additionally the selections are now alphabetically sorted. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03mips: octeon: mrvl, octeon-ebb7304.dts: Add SPI flash DT nodeStefan Roese1-0/+9
Add the SPI flash DT node for the EBB7304. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03mips: octeon: mrvl,cn73xx.dtsi: Add SPI DT nodeStefan Roese1-0/+10
Add the Octeon SPI DT node to the dtsi file. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03drivers: spi: Add SPI controller driver for OcteonSuneel Garapati3-0/+622
Adds support for SPI controllers found on Octeon II/III and Octeon TX TX2 SoC platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-08-03mips: octeon: dts: Add Octeon clock driver DT nodesStefan Roese2-1/+11
This patch adds the DT nodes for the Octeon clock support via the common clk_ API. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03clk: clk_octeon: Add simple MIPS Octeon clock driverStefan Roese4-0/+92
This patch adds a simple clock driver for the Marvell Octeon MIPS SoC family. Its for IO clock rate passing via DT in some of the Octeon driver, like I2C. So that we don't need to use the non-mainline API octeon_get_io_clock(). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Lukasz Majewski <lukma@denx.de>
2020-08-03mips: octeon: dts: Add I2C DT nodesStefan Roese2-0/+30
Add I2C DT nodes to the Octeon dts / dtsi files. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03mips: octeon: mrvl,cn73xx.dtsi: Add GPIO DT nodesStefan Roese1-0/+26
Add the Octeon GPIO DT node to the dtsi file. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03gpio: octeon_gpio: Add GPIO controller driver for OcteonSuneel Garapati3-0/+253
Add support for GPIO controllers found on Octeon II/III and Octeon TX TX2 SoC platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-08-03doc: qemu-mips build instructionsHeinrich Schuchardt1-4/+4
Correct the make commands for the defconfigs. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-03configs: pico-imx6: convert ethernet function to DM_ETHWig Cheng1-0/+3
Before enable _DM_ETH: Net: FEC [PRIME] After enable DM_ETH: Net: eth0: ethernet@2188000 Here is the test commands: => dhcp BOOTP broadcast 1 DHCP client bound to address 10.88.88.152 (146 ms) *** ERROR: `serverip' not set Cannot autoload with TFTPGET => ping 8.8.8.8 Using ethernet@2188000 device host 8.8.8.8 is alive Signed-off-by: Wig Cheng <wig.cheng@technexion.com>
2020-08-03imx8m: enlarge CONFIG_SYS_BOOTM_LENPeng Fan3-0/+6
Enlarge CONFIG_SYS_BOOTM_LEN when booting FIT image with AArch32 mode Linux kernel. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-08-03arm: imx6q: pcm058: Rework SPI NOR configurationNiel Fourie2-9/+14
Enable CONFIG_SPL_DM_SPI_FLASH to be able to boot from SPI NOR, modify the offset of U-boot proper in the SPI NOR, so the difference in offset matches between SPL and U-boot matches that of the SD Card, allowing u-boot-with-spl.imx to also be copied to SPI NOR at an offset of 0x400. Update the README to reflect this change. Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2020-08-03ARM: imx: hab: panic on authentication failureMarek Vasut1-4/+2
Instead of hang()ing the system and thus disallowing any automated recovery possibility from a HAB authentication failure, panic() . The panic() function can be configured to hang() the system after printing an error message, however the default is to reset the system instead. This allows redundant boot to work correctly. In case the primary or secondary image cannot be authenticated, the system reboots and bootrom can try to start the other one. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-08-03imx: Add MYiR Tech MYS-6ULX supportParthiban Nallathambi14-0/+840
MYS-6ULX is single board computer (SBC) comes with eMMC or NAND based on imx6ULL SoC from NXP and provision for expansion board. This commit adds support only for SBC with NAND. CPU: Freescale i.MX6ULL rev1.1 528 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 45C Reset cause: WDOG Model: MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND Board: MYiR MYS-6ULX 6ULL Single Board Computer DRAM: 256 MiB NAND: 256 MiB MMC: FSL_SDHC: 0 In: serial@2020000 Out: serial@2020000 Err: serial@2020000 Net: FEC0 Working: - Eth0 - MMC/SD - NAND - UART 1 - USB host Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
2020-08-03Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini9-11/+81
- ApolloLake: add u64 parameters support for FSP2 bindings - ApolloLake: add missing parameters to support full configuration of the latest FSP MR6 release - Append appropriate suffixes in various assembly codes
2020-08-03Merge tag 'efi-2020-10-rc2' of ↵Tom Rini17-194/+245
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-10-rc2 This series comprises error corrections for the UEFI subsystem: * make the memory size reserved for the U-Boot stack customizable and reduce it for the MAIX board * correct build dependencies for UEFI unit test * enable read-only UEFI variable are enabled with the TEE backend * add 10 ms wait to sysreset to fix a problem with unit testing
2020-08-03x86: call32: Append appropriate suffixesAndy Shevchenko1-3/+2
Assembler is not happy: arch/x86/cpu/call32.S: Assembler messages: arch/x86/cpu/call32.S:36: Warning: no instruction mnemonic suffix given and no register operands; using default for `retf' Fix this by adding appropriate suffixes to the assembler commands. Fixes: 6f92ed8f1abf ("x86: Add a way to call 32-bit code from 64-bit mode") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-03x86: sipi_vector: Append appropriate suffixesAndy Shevchenko1-3/+3
Assembler is not happy: arch/x86/cpu/sipi_vector.S: Assembler messages: arch/x86/cpu/sipi_vector.S:134: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp' arch/x86/cpu/sipi_vector.S:139: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts' arch/x86/cpu/sipi_vector.S:157: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp' Fix this by adding appropriate suffixes to the assembler commands. Fixes: 45b5a37836d5 ("x86: Add multi-processor init") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-03arch: x86: apl: Update FSP parametersBernhard Messerklinger5-2/+44
Add missing parameters to support full configuration of the latest FSP MR6 release. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-03x86: apl: fsp_bindings: Add support for u64 parametersBernhard Messerklinger2-0/+29
Add FSP_UINT64 read support as preparation for FSP-M and FSP-S parameter update. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-03x86: irq: Fix some typosWolfgang Wallner1-3/+3
Fix some typos in arch/x86/include/asm/irq.h. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-02sh: r2dplus: Enable additional PCI ethernet devicesMarek Vasut1-0/+4
Enable these extra PCI ethernet devices, so they can be tested in CI. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-08-02sh: r2dplus: Enable DM_SERIAL and DM_CLKMarek Vasut2-2/+4
Switch r2dplus to DM and DT probing for serial and clock. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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