diff options
Diffstat (limited to 'arch')
219 files changed, 4695 insertions, 2315 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index c4dc47dccb..1ffd77c0f4 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -146,7 +146,6 @@ config SANDBOX select DM_SPI select DM_SPI_FLASH select GZIP_COMPRESSED - select HAVE_BLOCK_DEVICE select LZO select OF_BOARD_SETUP select PCI_ENDPOINT @@ -167,7 +166,6 @@ config SANDBOX imply CMD_IO imply CMD_IOTRACE imply CMD_LZMADEC - imply CMD_SATA imply CMD_SF imply CMD_SF_TEST imply CRC32_VERIFY diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c index 628addd87e..07b2c1540d 100644 --- a/arch/arc/lib/bootm.c +++ b/arch/arc/lib/bootm.c @@ -22,10 +22,10 @@ static int cleanup_before_linux(void) return 0; } -__weak int board_prep_linux(bootm_headers_t *images) { return 0; } +__weak int board_prep_linux(struct bootm_headers *images) { return 0; } /* Subcommand: PREP */ -static int boot_prep_linux(bootm_headers_t *images) +static int boot_prep_linux(struct bootm_headers *images) { int ret; @@ -49,7 +49,7 @@ __weak void board_jump_and_run(ulong entry, int zero, int arch, uint params) } /* Subcommand: GO */ -static void boot_jump_linux(bootm_headers_t *images, int flag) +static void boot_jump_linux(struct bootm_headers *images, int flag) { ulong kernel_entry; unsigned int r0, r2; @@ -79,7 +79,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) board_jump_and_run(kernel_entry, r0, 0, r2); } -int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) +int do_bootm_linux(int flag, int argc, char *argv[], struct bootm_headers *images) { /* No need for those on ARC */ if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE)) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 82cd456f51..2e83394052 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -488,6 +488,15 @@ config TPL_SYS_THUMB_BUILD density. For ARM architectures that support Thumb2 this flag will result in Thumb2 code generated by GCC. +config SYS_L2_PL310 + bool "ARM PL310 L2 cache controller" + help + Enable support for ARM PL310 L2 cache controller in U-Boot + +config SPL_SYS_L2_PL310 + bool "ARM PL310 L2 cache controller in SPL" + help + Enable support for ARM PL310 L2 cache controller in SPL config SYS_L2CACHE_OFF bool "L2cache off" @@ -618,6 +627,7 @@ config ARCH_KIRKWOOD select BOARD_EARLY_INIT_F select CPU_ARM926EJS select GPIO_EXTRA_HEADER + select TIMER config ARCH_MVEBU bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)" @@ -629,6 +639,8 @@ config ARCH_MVEBU select GPIO_EXTRA_HEADER select SPL_DM_SPI if SPL select SPL_DM_SPI_FLASH if SPL + select SPL_TIMER if SPL + select TIMER select OF_CONTROL select OF_SEPARATE select SPI @@ -639,6 +651,7 @@ config ARCH_ORION5X select CPU_ARM926EJS select GPIO_EXTRA_HEADER select SPL_SEPARATE_BSS if SPL + select TIMER config TARGET_STV0991 bool "Support stv0991" @@ -989,6 +1002,7 @@ config ARCH_MX6 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE + select SYS_L2_PL310 if !SYS_L2CACHE_OFF imply MXC_GPIO imply SYS_THUMB_BUILD imply SPL_SEPARATE_BSS @@ -1016,7 +1030,6 @@ config ARCH_NPCM config ARCH_APPLE bool "Apple SoCs" select ARM64 - select BLK select CLK select CMD_USB select DM @@ -1238,6 +1251,18 @@ config ARCH_VERSAL imply BOARD_LATE_INIT imply ENV_VARS_UBOOT_RUNTIME_CONFIG +config ARCH_VERSAL_NET + bool "Support Xilinx Keystone Platform" + select ARM64 + select CLK + select DM + select DM_ETH if NET + select DM_MMC if MMC + select DM_SERIAL + select OF_CONTROL + imply BOARD_LATE_INIT + imply ENV_VARS_UBOOT_RUNTIME_CONFIG + config ARCH_VF610 bool "Freescale Vybrid" select CPU_V7A @@ -1249,6 +1274,7 @@ config ARCH_VF610 config ARCH_ZYNQ bool "Xilinx Zynq based platform" + select ARM_TWD_TIMER select CLK select CLK_ZYNQ select CPU_V7A @@ -1268,7 +1294,9 @@ config ARCH_ZYNQ select SPL_DM_SPI_FLASH if SPL select SPL_OF_CONTROL if SPL select SPL_SEPARATE_BSS if SPL + select SPL_TIMER if SPL select SUPPORT_SPL + select TIMER imply ARCH_EARLY_INIT_R imply BOARD_LATE_INIT imply CMD_CLK @@ -2284,6 +2312,8 @@ source "arch/arm/mach-zynqmp/Kconfig" source "arch/arm/mach-versal/Kconfig" +source "arch/arm/mach-versal-net/Kconfig" + source "arch/arm/mach-zynqmp-r5/Kconfig" source "arch/arm/cpu/armv7/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 1f4a1d5788..ac602aed9c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -88,6 +88,7 @@ machine-$(CONFIG_ARCH_OCTEONTX) += octeontx machine-$(CONFIG_ARCH_OCTEONTX2) += octeontx2 machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_VERSAL) += versal +machine-$(CONFIG_ARCH_VERSAL_NET) += versal-net machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5 diff --git a/arch/arm/config.mk b/arch/arm/config.mk index b3548ce243..2065438d05 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -15,11 +15,11 @@ CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \ -fstack-protector-strong CFLAGS_EFI := -fpic -fshort-wchar -ifneq ($(CONFIG_LTO)$(CONFIG_USE_PRIVATE_LIBGCC),yy) +ifneq ($(LTO_ENABLE)$(CONFIG_USE_PRIVATE_LIBGCC),yy) LDFLAGS_FINAL += --gc-sections endif -ifndef CONFIG_LTO +ifneq ($(LTO_ENABLE),y) PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 965895bc2a..71e9bd4da3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -233,8 +233,11 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra210-p3450-0000.dtb ifdef CONFIG_ARMADA_32BIT +ifdef CONFIG_ARMADA_375 +dtb-$(CONFIG_ARCH_MVEBU) += \ + armada-375-db.dtb +else dtb-$(CONFIG_ARCH_MVEBU) += \ - armada-375-db.dtb \ armada-385-atl-x530.dtb \ armada-385-atl-x530DP.dtb \ armada-385-db-88f6820-amc.dtb \ @@ -254,6 +257,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-xp-maxbcm.dtb \ armada-xp-synology-ds414.dtb \ armada-xp-theadorable.dtb +endif else dtb-$(CONFIG_ARCH_MVEBU) += \ armada-3720-db.dtb \ @@ -379,6 +383,9 @@ dtb-$(CONFIG_ARCH_VERSAL) += \ versal-mini-emmc0.dtb \ versal-mini-emmc1.dtb \ xilinx-versal-virt.dtb +dtb-$(CONFIG_ARCH_VERSAL_NET) += \ + versal-net-mini.dtb \ + xilinx-versal-net-virt.dtb dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \ zynqmp-r5.dtb dtb-$(CONFIG_AM33XX) += \ @@ -388,8 +395,6 @@ dtb-$(CONFIG_AM33XX) += \ am335x-boneblack-wireless.dtb \ am335x-boneblue.dtb \ am335x-brppt1-mmc.dtb \ - am335x-brppt1-nand.dtb \ - am335x-brppt1-spi.dtb \ am335x-brxre1.dtb \ am335x-brsmarc1.dtb \ am335x-draco.dtb \ @@ -1233,6 +1238,15 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-bananapi-bpi-r64.dtb \ mt7623n-bananapi-bpi-r2.dtb \ mt7629-rfb.dtb \ + mt7981-rfb.dtb \ + mt7981-emmc-rfb.dtb \ + mt7981-sd-rfb.dtb \ + mt7986a-rfb.dtb \ + mt7986b-rfb.dtb \ + mt7986a-sd-rfb.dtb \ + mt7986b-sd-rfb.dtb \ + mt7986a-emmc-rfb.dtb \ + mt7986b-emmc-rfb.dtb \ mt8183-pumpkin.dtb \ mt8512-bm1-emmc.dtb \ mt8516-pumpkin.dtb \ diff --git a/arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi b/arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi new file mode 100644 index 0000000000..a3d5650e48 --- /dev/null +++ b/arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 B&R Industrial Automation GmbH - + * https://www.br-automation.com/ + */ + +/ { + ocp { + u-boot,dm-pre-reloc; + }; +}; + +&l4_wkup { + u-boot,dm-pre-reloc; + segment@200000 { + u-boot,dm-pre-reloc; + target-module@0 + { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + }; + target-module@7000 { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + }; + target-module@9000 { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + }; + }; +}; + +&wkup_cm { + u-boot,dm-pre-reloc; +}; + +&l4_wkup_clkctrl { + u-boot,dm-pre-reloc; +}; + +&l4_per { + u-boot,dm-pre-reloc; + segment@0 { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + target-module@4c000 { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + }; + }; + + segment@100000 { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + target-module@ac000 { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + }; + target-module@ae000 { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + }; + }; +}; + +&prcm { + u-boot,dm-pre-reloc; +}; + +&gpio0_target { + u-boot,dm-pre-reloc; +}; + +&prcm_clocks { + compatible = "simple-bus"; +}; + +&scm_clocks { + compatible = "simple-bus"; +}; + +&i2c0 { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&mmc1 { + u-boot,dm-pre-reloc; +}; + +&mmc2 { + u-boot,dm-pre-reloc; +}; + +&gpio0 { + u-boot,dm-pre-reloc; +}; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&gpio2 { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/am335x-brppt1-mmc.dts b/arch/arm/dts/am335x-brppt1-mmc.dts index bd2f6c2e3e..4db279b65e 100644 --- a/arch/arm/dts/am335x-brppt1-mmc.dts +++ b/arch/arm/dts/am335x-brppt1-mmc.dts @@ -12,25 +12,10 @@ model = "BRPPT1 (MMC) Panel"; compatible = "ti,am33xx"; - fset: factory-settings { - bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890"; - version = <0x0100>; - order-no = "6PPT30 (MMC)"; - hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890"; - serial-no = "0"; - device-id = <0x0>; - parent-id = <0x0>; - hw-variant = <0x1>; - }; aliases { - ds1bkl0 = &pwmbacklight; - ds1bkl1 = &tps_bl; - ds1timing = &timing0; - ds1ctrl = &lcdc; gpmc = &gpmc; mmc = &mmc2; - fset = &fset; }; chosen { @@ -43,110 +28,21 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - panel { - status = "disabled"; - - compatible = "ti,tilcdc,panel"; - enable-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - - backlight = <&pwmbacklight>; - bkl-pwm = <&pwmbacklight>; - bkl-tps = <&tps_bl>; - - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - display-timings { - native-mode = <&timing0>; - timing0: lcd { - clock-frequency = <32000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <2>; - hback-porch = <192>; - hsync-len = <1>; - vfront-porch = <20>; - vback-porch = <2>; - vsync-len = <1>; - hsync-active = <1>; - vsync-active = <1>; - pupdelay = <10>; - pondelay = <10>; - }; - }; - }; - vmmcsd_fixed: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - - pwm0: omap-pwm@timer5 { - compatible = "ti,omap-dmtimer-pwm"; - ti,timers = <&timer5>; - #pwm-cells = <3>; - }; - - pwm1: omap-pwm@timer6 { - compatible = "ti,omap-dmtimer-pwm"; - ti,timers = <&timer6>; - #pwm-cells = <3>; - }; - - beeper: pwm-beep { - compatible = "pwm-beeper"; - pwms = <&pwm0 0 0 0>; - }; - - pwmbacklight: pwm-bkl { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000 0>; - - default-brightness-level = <255>; - brightness-levels = <0 16 32 64 128 170 202 234 255>; - - power-supply = <&vmmcsd_fixed>; - enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; }; &uart0 { /* console uart */ - u-boot,dm-spl; - status = "okay"; -}; - -&uart1 { status = "okay"; }; &i2c0 { - u-boot,dm-spl; status = "okay"; clock-frequency = <400000>; - - tps: tps@24 { /* PMIC controller */ - u-boot,dm-spl; - reg = <0x24>; - compatible = "ti,tps65217"; - - tps_bl: backlight { - compatible = "ti,tps65217-bl"; - isel = <1>; /* 1 - ISET1, 2 ISET2 */ - fdim = <1000>; /* TPS65217_BL_FDIM_1kHZ */ - default-brightness = <50>; - }; - }; }; &i2c2 { @@ -158,10 +54,6 @@ status = "okay"; }; -&cppi41dma { - status = "okay"; -}; - &usb { status = "okay"; }; @@ -217,7 +109,6 @@ }; &mmc1 { - u-boot,dm-spl; vmmc-supply = <&vmmcsd_fixed>; bus-width = <0x4>; ti,non-removable; @@ -227,7 +118,6 @@ }; &mmc2 { - u-boot,dm-spl; vmmc-supply = <&vmmcsd_fixed>; bus-width = <0x8>; ti,non-removable; @@ -236,77 +126,20 @@ status = "okay"; }; -&l4_per { - - segment@300000 { - - target-module@e000 { - u-boot,dm-pre-reloc; - - lcdc: lcdc@0 { - u-boot,dm-pre-reloc; - status = "disabled"; - }; - }; - }; -}; - -&elm { - status = "okay"; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - &gpio0 { - u-boot,dm-spl; ti,no-reset-on-init; }; &gpio1 { - u-boot,dm-spl; ti,no-reset-on-init; }; &gpio2 { - u-boot,dm-spl; ti,no-reset-on-init; }; &gpio3 { - u-boot,dm-spl; - ti,no-reset-on-init; -}; - -&wdt2 { ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,zx-cutoff-ratio = <40>; - ti,min_deviation = <60>; - ti,max_deviation = <600>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - - bnr-buttons { - Home-Button {}; - }; - }; - - adc { - ti,adc-channels = <5 6 7>; - }; }; &timer6 { /* used for cpsw end device */ @@ -320,37 +153,3 @@ ti,no-reset-on-init; ti,no-idle-on-init; }; - -&wdt2 { - status = "okay"; - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&epwmss0 { - status = "okay"; -}; - -&tscadc { - status = "okay"; -}; - -&dcan0 { - status = "okay"; -}; - -&dcan1 { - status = "okay"; -}; - -&sham { - status = "disabled"; -}; - -&aes { - status = "disabled"; -}; - -&rng { - status = "disabled"; -}; diff --git a/arch/arm/dts/am335x-brppt1-nand.dts b/arch/arm/dts/am335x-brppt1-nand.dts deleted file mode 100644 index 67c609739f..0000000000 --- a/arch/arm/dts/am335x-brppt1-nand.dts +++ /dev/null @@ -1,374 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 B&R Industrial Automation GmbH - * http://www.br-automation.com - * - */ -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - model = "BRPPT1 (NAND) Panel"; - compatible = "ti,am33xx"; - - fset: factory-settings { - bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890"; - version = <0x0100>; - order-no = "6PPT30 (NAND)"; - hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890"; - serial-no = "0"; - device-id = <0x0>; - parent-id = <0x0>; - hw-variant = <0x1>; - }; - - aliases { - ds1bkl0 = &pwmbacklight; - ds1bkl1 = &tps_bl; - ds1timing = &timing0; - ds1ctrl = &lcdc; - gpmc = &gpmc; - mmc = &mmc2; - fset = &fset; - }; - - chosen { - bootargs = "console=ttyO0,115200 earlyprintk"; - stdout-path = &uart0; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - panel { - status = "disabled"; - - compatible = "ti,tilcdc,panel"; - enable-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - - backlight = <&pwmbacklight>; - bkl-pwm = <&pwmbacklight>; - bkl-tps = <&tps_bl>; - - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - display-timings { - native-mode = <&timing0>; - timing0: lcd { - clock-frequency = <32000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <2>; - hback-porch = <192>; - hsync-len = <1>; - vfront-porch = <20>; - vback-porch = <2>; - vsync-len = <1>; - hsync-active = <1>; - vsync-active = <1>; - pupdelay = <10>; - pondelay = <10>; - }; - }; - }; - - vmmcsd_fixed: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - pwm0: omap-pwm@timer5 { - compatible = "ti,omap-dmtimer-pwm"; - ti,timers = <&timer5>; - #pwm-cells = <3>; - }; - - pwm1: omap-pwm@timer6 { - compatible = "ti,omap-dmtimer-pwm"; - ti,timers = <&timer6>; - #pwm-cells = <3>; - }; - - beeper: pwm-beep { - compatible = "pwm-beeper"; - pwms = <&pwm0 0 0 0>; - }; - - pwmbacklight: pwm-bkl { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000 0>; - - default-brightness-level = <255>; - brightness-levels = <0 16 32 64 128 170 202 234 255>; - - power-supply = <&vmmcsd_fixed>; - enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart0 { /* console uart */ - u-boot,dm-spl; - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - u-boot,dm-spl; - status = "okay"; - clock-frequency = <400000>; - - tps: tps@24 { /* PMIC controller */ - u-boot,dm-spl; - reg = <0x24>; - compatible = "ti,tps65217"; - - tps_bl: backlight { - compatible = "ti,tps65217-bl"; - isel = <1>; /* 1 - ISET1, 2 ISET2 */ - fdim = <1000>; /* TPS65217_BL_FDIM_1kHZ */ - default-brightness = <50>; - }; - }; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <100000>; -}; - -&edma { - status = "okay"; -}; - -&cppi41dma { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&davinci_mdio { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <1>; - }; - - phy1: ethernet-phy@1 { - reg = <2>; - }; -}; - -&mac { - dual_emac; - status = "okay"; -}; - -&cpsw_emac0 { - phy-handle = <&phy0>; - dual_emac_res_vlan = <1>; - phy-mode = "mii"; -}; - -&cpsw_emac1 { - phy-handle = <&phy1>; - dual_emac_res_vlan = <2>; - phy-mode = "mii"; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <0x4>; - ti,non-removable; - ti,needs-special-hs-handling; - ti,vcc-aux-disable-is-sleep; - status = "disabled"; -}; - -&l4_per { - - segment@300000 { - - target-module@e000 { - u-boot,dm-pre-reloc; - - lcdc: lcdc@0 { - u-boot,dm-pre-reloc; - status = "disabled"; - }; - }; - }; -}; - -&elm { - status = "okay"; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0 { - u-boot,dm-spl; - ti,no-reset-on-init; -}; - -&gpio1 { - u-boot,dm-spl; - ti,no-reset-on-init; -}; - -&gpio2 { - u-boot,dm-spl; - ti,no-reset-on-init; -}; - -&gpio3 { - u-boot,dm-spl; - ti,no-reset-on-init; -}; - -&wdt2 { - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,zx-cutoff-ratio = <40>; - ti,min_deviation = <60>; - ti,max_deviation = <600>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - - bnr-buttons { - Home-Button {}; - }; - }; - - adc { - ti,adc-channels = <5 6 7>; - }; -}; - -&gpmc { - u-boot,dm-spl; - status = "okay"; - pinctrl-names = "default"; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - rb-gpios = <&gpmc 1 GPIO_ACTIVE_HIGH>; /* gpmc_wait1 */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,wait-pin = <1>; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.MLO"; - reg = <0x00000000 0x000020000>; - }; - partition@1 { - label = "NAND.cfgscr"; - reg = <0x00020000 0x00020000>; - }; - partition@2 { - label = "NAND.dtb"; - reg = <0x00040000 0x00020000>; - }; - partition@3 { - label = "NAND.u-boot-env"; - reg = <0x00060000 0x00020000>; - }; - partition@4 { - label = "NAND.u-boot"; - reg = <0x00080000 0x00080000>; - }; - partition@5 { - label = "NAND.kernel"; - reg = <0x00100000 0x00400000>; - }; - partition@6 { - label = "NAND.rootfs"; - reg = <0x00500000 0x08000000>; - }; - partition@7 { - label = "NAND.user"; - reg = <0x08500000 0x17b00000>; - }; - }; -}; diff --git a/arch/arm/dts/am335x-brppt1-spi.dts b/arch/arm/dts/am335x-brppt1-spi.dts deleted file mode 100644 index ce3dce204d..0000000000 --- a/arch/arm/dts/am335x-brppt1-spi.dts +++ /dev/null @@ -1,377 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 B&R Industrial Automation GmbH - * http://www.br-automation.com - * - */ -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - model = "BRPPT1 (MMC) Panel"; - compatible = "ti,am33xx"; - - fset: factory-settings { - bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890"; - version = <0x0100>; - order-no = "6PPT30 (SPI)"; - hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890"; - serial-no = "0"; - device-id = <0x0>; - parent-id = <0x0>; - hw-variant = <0x1>; - }; - - aliases { - ds1bkl0 = &pwmbacklight; - ds1bkl1 = &tps_bl; - ds1timing = &timing0; - ds1ctrl = &lcdc; - gpmc = &gpmc; - mmc = &mmc2; - spi0 = &spi0; - fset = &fset; - }; - - chosen { - bootargs = "console=ttyO0,115200 earlyprintk"; - stdout-path = &uart0; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - panel { - status = "disabled"; - - compatible = "ti,tilcdc,panel"; - enable-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - - backlight = <&pwmbacklight>; - bkl-pwm = <&pwmbacklight>; - bkl-tps = <&tps_bl>; - - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - display-timings { - native-mode = <&timing0>; - timing0: lcd { - clock-frequency = <32000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <2>; - hback-porch = <192>; - hsync-len = <1>; - vfront-porch = <20>; - vback-porch = <2>; - vsync-len = <1>; - hsync-active = <1>; - vsync-active = <1>; - pupdelay = <10>; - pondelay = <10>; - }; - }; - }; - - vmmcsd_fixed: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - pwm0: omap-pwm@timer5 { - compatible = "ti,omap-dmtimer-pwm"; - ti,timers = <&timer5>; - #pwm-cells = <3>; - }; - - pwm1: omap-pwm@timer6 { - compatible = "ti,omap-dmtimer-pwm"; - ti,timers = <&timer6>; - #pwm-cells = <3>; - }; - - beeper: pwm-beep { - compatible = "pwm-beeper"; - pwms = <&pwm0 0 0 0>; - }; - - pwmbacklight: pwm-bkl { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000 0>; - - default-brightness-level = <255>; - brightness-levels = <0 16 32 64 128 170 202 234 255>; - - power-supply = <&vmmcsd_fixed>; - enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart0 { /* console uart */ - u-boot,dm-spl; - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - u-boot,dm-spl; - status = "okay"; - clock-frequency = <400000>; - - tps: tps@24 { /* PMIC controller */ - u-boot,dm-spl; - reg = <0x24>; - compatible = "ti,tps65217"; - - tps_bl: backlight { - compatible = "ti,tps65217-bl"; - isel = <1>; /* 1 - ISET1, 2 ISET2 */ - fdim = <1000>; /* TPS65217_BL_FDIM_1kHZ */ - default-brightness = <50>; - }; - }; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <100000>; -}; - -&spi0 { - u-boot,dm-spl; - status = "okay"; - - cs-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>, - <&gpio0 6 GPIO_ACTIVE_HIGH>, - <0>, - <0>; - - spi-max-frequency = <24000000>; - - spi_flash: spiflash@0 { - u-boot,dm-spl; - u-boot,dm-pre-reloc; - compatible = "spidev", "jedec,spi-nor"; - spi-max-frequency = <24000000>; - reg = <0>; - }; -}; - -&edma { - status = "okay"; -}; - -&cppi41dma { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&davinci_mdio { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <1>; - }; - - phy1: ethernet-phy@1 { - reg = <2>; - }; -}; - -&mac { - status = "okay"; -}; - -&cpsw_emac0 { - phy-handle = <&phy0>; - dual_emac_res_vlan = <1>; - phy-mode = "mii"; -}; - -&cpsw_emac1 { - phy-handle = <&phy1>; - dual_emac_res_vlan = <2>; - phy-mode = "mii"; -}; - -&mmc1 { - u-boot,dm-spl; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <0x4>; - ti,non-removable; - ti,needs-special-hs-handling; - ti,vcc-aux-disable-is-sleep; - status = "okay"; -}; - -&mmc2 { - u-boot,dm-spl; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <0x8>; - ti,non-removable; - ti,needs-special-hs-handling; - ti,vcc-aux-disable-is-sleep; - status = "okay"; -}; - -&l4_per { - - segment@300000 { - - target-module@e000 { - u-boot,dm-pre-reloc; - - lcdc: lcdc@0 { - u-boot,dm-pre-reloc; - status = "disabled"; - }; - }; - }; -}; - -&elm { - status = "okay"; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0 { - u-boot,dm-spl; - ti,no-reset-on-init; -}; - -&gpio1 { - u-boot,dm-spl; - ti,no-reset-on-init; -}; - -&gpio2 { - u-boot,dm-spl; - ti,no-reset-on-init; -}; - -&gpio3 { - u-boot,dm-spl; - ti,no-reset-on-init; -}; - -&wdt2 { - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,zx-cutoff-ratio = <40>; - ti,min_deviation = <60>; - ti,max_deviation = <600>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - - bnr-buttons { - Home-Button {}; - }; - }; - - adc { - ti,adc-channels = <5 6 7>; - }; -}; - -&timer6 { /* used for cpsw end device */ - status = "okay"; - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&timer7 { /* used for cpsw end device */ - status = "okay"; - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&wdt2 { - status = "okay"; - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&epwmss0 { - status = "okay"; -}; - -&tscadc { - status = "okay"; -}; - -&dcan0 { - status = "okay"; -}; - -&dcan1 { - status = "okay"; -}; - -&sham { - status = "disabled"; -}; - -&aes { - status = "disabled"; -}; - -&rng { - status = "disabled"; -}; diff --git a/arch/arm/dts/armada-375.dtsi b/arch/arm/dts/armada-375.dtsi index 20a8c352b2..a044b3fc99 100644 --- a/arch/arm/dts/armada-375.dtsi +++ b/arch/arm/dts/armada-375.dtsi @@ -187,7 +187,7 @@ reg = <0xc000 0x58>; }; - timer@c600 { + timer0: timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; @@ -416,7 +416,7 @@ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; }; - timer@20300 { + timer1: timer@20300 { compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; reg = <0x20300 0x30>, <0x21040 0x30>; interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts index ba73386d4f..7d833640b6 100644 --- a/arch/arm/dts/armada-xp-theadorable.dts +++ b/arch/arm/dts/armada-xp-theadorable.dts @@ -107,20 +107,6 @@ status = "okay"; }; - mdio { - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "sgmii"; - }; - usb@50000 { status = "okay"; }; @@ -166,6 +152,18 @@ clock-frequency = <100000>; }; +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + phy = <&phy0>; + phy-mode = "sgmii"; +}; + &spi0 { status = "okay"; @@ -198,7 +196,6 @@ }; }; - &pciec { status = "okay"; diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts index cc577761fa..1fbacf985f 100644 --- a/arch/arm/dts/ast2500-evb.dts +++ b/arch/arm/dts/ast2500-evb.dts @@ -78,6 +78,39 @@ pinctrl-0 = <&pinctrl_sd2_default>; }; +&fmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fwspics1_default>; + + flash@0 { + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; + + flash@1 { + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1cs1_default>; + + flash@0 { + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + &i2c3 { status = "okay"; diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi index cea08e6f08..320d2e5340 100644 --- a/arch/arm/dts/ast2500.dtsi +++ b/arch/arm/dts/ast2500.dtsi @@ -57,23 +57,26 @@ ranges; fmc: flash-controller@1e620000 { - reg = < 0x1e620000 0xc4 - 0x20000000 0x10000000 >; + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-fmc"; + clocks = <&scu ASPEED_CLK_AHB>; + num-cs = <3>; status = "disabled"; - interrupts = <19>; + flash@0 { reg = < 0 >; compatible = "jedec,spi-nor"; status = "disabled"; }; + flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; status = "disabled"; }; + flash@2 { reg = < 2 >; compatible = "jedec,spi-nor"; @@ -82,17 +85,20 @@ }; spi1: flash-controller@1e630000 { - reg = < 0x1e630000 0xc4 - 0x30000000 0x08000000 >; + reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-spi"; + clocks = <&scu ASPEED_CLK_AHB>; + num-cs = <2>; status = "disabled"; + flash@0 { reg = < 0 >; compatible = "jedec,spi-nor"; status = "disabled"; }; + flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; @@ -101,17 +107,20 @@ }; spi2: flash-controller@1e631000 { - reg = < 0x1e631000 0xc4 - 0x38000000 0x08000000 >; + reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-spi"; + clocks = <&scu ASPEED_CLK_AHB>; + num-cs = <2>; status = "disabled"; + flash@0 { reg = < 0 >; compatible = "jedec,spi-nor"; status = "disabled"; }; + flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts index a9bba96816..a097f320e4 100644 --- a/arch/arm/dts/ast2600-evb.dts +++ b/arch/arm/dts/ast2600-evb.dts @@ -72,12 +72,10 @@ &fmc { status = "okay"; - pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fmcquad_default>; flash@0 { - compatible = "spi-flash", "sst,w25q256"; status = "okay"; spi-max-frequency = <50000000>; spi-tx-bus-width = <4>; @@ -85,7 +83,6 @@ }; flash@1 { - compatible = "spi-flash", "sst,w25q256"; status = "okay"; spi-max-frequency = <50000000>; spi-tx-bus-width = <4>; @@ -93,7 +90,6 @@ }; flash@2 { - compatible = "spi-flash", "sst,w25q256"; status = "okay"; spi-max-frequency = <50000000>; spi-tx-bus-width = <4>; @@ -103,14 +99,12 @@ &spi1 { status = "okay"; - pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default &pinctrl_spi1cs1_default &pinctrl_spi1wp_default &pinctrl_spi1wp_default &pinctrl_spi1quad_default>; flash@0 { - compatible = "spi-flash", "sst,w25q256"; status = "okay"; spi-max-frequency = <50000000>; spi-tx-bus-width = <4>; @@ -120,13 +114,11 @@ &spi2 { status = "okay"; - pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default &pinctrl_spi2cs2_default &pinctrl_spi2quad_default>; flash@0 { - compatible = "spi-flash", "sst,w25q256"; status = "okay"; spi-max-frequency = <50000000>; spi-tx-bus-width = <4>; diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index ac8cd4d67d..8d91eedc17 100644 --- a/arch/arm/dts/ast2600.dtsi +++ b/arch/arm/dts/ast2600.dtsi @@ -129,74 +129,78 @@ }; fmc: flash-controller@1e620000 { - reg = < 0x1e620000 0xc4 - 0x20000000 0x10000000 >; + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2600-fmc"; status = "disabled"; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_AHB>; num-cs = <3>; + flash@0 { - reg = < 0 >; + reg = <0>; compatible = "jedec,spi-nor"; status = "disabled"; }; + flash@1 { - reg = < 1 >; + reg = <1>; compatible = "jedec,spi-nor"; status = "disabled"; }; + flash@2 { - reg = < 2 >; + reg = <2>; compatible = "jedec,spi-nor"; status = "disabled"; }; }; spi1: flash-controller@1e630000 { - reg = < 0x1e630000 0xc4 - 0x30000000 0x08000000 >; + reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2600-spi"; clocks = <&scu ASPEED_CLK_AHB>; num-cs = <2>; status = "disabled"; + flash@0 { - reg = < 0 >; + reg = <0>; compatible = "jedec,spi-nor"; status = "disabled"; }; + flash@1 { - reg = < 1 >; + reg = <1>; compatible = "jedec,spi-nor"; status = "disabled"; }; }; spi2: flash-controller@1e631000 { - reg = < 0x1e631000 0xc4 - 0x50000000 0x08000000 >; + reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2600-spi"; clocks = <&scu ASPEED_CLK_AHB>; num-cs = <3>; status = "disabled"; + flash@0 { - reg = < 0 >; + reg = <0>; compatible = "jedec,spi-nor"; status = "disabled"; }; + flash@1 { - reg = < 1 >; + reg = <1>; compatible = "jedec,spi-nor"; status = "disabled"; }; + flash@2 { - reg = < 2 >; + reg = <2>; compatible = "jedec,spi-nor"; status = "disabled"; }; diff --git a/arch/arm/dts/at91-sam9x60_curiosity.dts b/arch/arm/dts/at91-sam9x60_curiosity.dts index 2e7ccb0ffb..7c5b6ae2b8 100644 --- a/arch/arm/dts/at91-sam9x60_curiosity.dts +++ b/arch/arm/dts/at91-sam9x60_curiosity.dts @@ -44,6 +44,11 @@ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; }; + + pinctrl_onewire_tm_default: onewire_tm_default { + atmel,pins = + <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; + }; }; }; }; @@ -66,6 +71,18 @@ memory { reg = <0x20000000 0x8000000>; }; + + onewire_tm: onewire { + gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_onewire_tm_default>; + status = "okay"; + + w1_eeprom: w1_eeprom@0 { + compatible = "maxim,ds24b33"; + status = "okay"; + }; + }; }; &macb0 { diff --git a/arch/arm/dts/at91-sama5d27_giantboard.dts b/arch/arm/dts/at91-sama5d27_giantboard.dts index e81ca60ca0..2625f81c8b 100644 --- a/arch/arm/dts/at91-sama5d27_giantboard.dts +++ b/arch/arm/dts/at91-sama5d27_giantboard.dts @@ -30,7 +30,7 @@ sdmmc1: sdio-host@b0000000 { bus-width = <4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc1_default>; status = "okay"; u-boot,dm-pre-reloc; }; @@ -73,10 +73,9 @@ u-boot,dm-pre-reloc; }; - pioA: gpio@fc038000 { - pinctrl { - - pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default { + pioA: pinctrl@fc038000 { + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_data { pinmux = <PIN_PA28__SDMMC1_CMD>, <PIN_PA18__SDMMC1_DAT0>, <PIN_PA19__SDMMC1_DAT1>, @@ -86,41 +85,41 @@ u-boot,dm-pre-reloc; }; - pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { + ck_cd { pinmux = <PIN_PA22__SDMMC1_CK>, <PIN_PA30__SDMMC1_CD>; bias-disable; u-boot,dm-pre-reloc; }; + }; - pinctrl_uart1_default: uart1_default { - pinmux = <PIN_PD2__URXD1>, - <PIN_PD3__UTXD1>; - bias-disable; - u-boot,dm-pre-reloc; - }; + pinctrl_uart1_default: uart1_default { + pinmux = <PIN_PD2__URXD1>, + <PIN_PD3__UTXD1>; + bias-disable; + u-boot,dm-pre-reloc; + }; - pinctrl_i2c0_default: i2c0_default { - pinmux = <PIN_PD21__TWD0>, - <PIN_PD22__TWCK0>; - bias-disable; - }; + pinctrl_i2c0_default: i2c0_default { + pinmux = <PIN_PD21__TWD0>, + <PIN_PD22__TWCK0>; + bias-disable; + }; - pinctrl_i2c1_default: i2c1_default { - pinmux = <PIN_PD4__TWD1>, - <PIN_PD5__TWCK1>; - bias-disable; - }; + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PD4__TWD1>, + <PIN_PD5__TWCK1>; + bias-disable; + }; - pinctrl_usb_default: usb_default { - pinmux = <PIN_PB10__GPIO>; - bias-disable; - }; + pinctrl_usb_default: usb_default { + pinmux = <PIN_PB10__GPIO>; + bias-disable; + }; - pinctrl_usba_vbus: usba_vbus { - pinmux = <PIN_PA31__GPIO>; - bias-disable; - }; + pinctrl_usba_vbus: usba_vbus { + pinmux = <PIN_PA31__GPIO>; + bias-disable; }; }; }; diff --git a/arch/arm/dts/at91-sama5d27_som1_ek.dts b/arch/arm/dts/at91-sama5d27_som1_ek.dts index efd1a5d197..70d15c8a62 100644 --- a/arch/arm/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/dts/at91-sama5d27_som1_ek.dts @@ -83,7 +83,7 @@ sdmmc0: sdio-host@a0000000 { bus-width = <8>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc0_default>; status = "okay"; u-boot,dm-pre-reloc; }; @@ -91,7 +91,7 @@ sdmmc1: sdio-host@b0000000 { bus-width = <4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc1_default>; status = "okay"; /* conflict with qspi0 */ u-boot,dm-pre-reloc; }; @@ -129,7 +129,7 @@ u-boot,dm-pre-reloc; }; - pioA: gpio@fc038000 { + pioA: pinctrl@fc038000 { pinctrl { pinctrl_lcd_base: pinctrl_lcd_base { pinmux = <PIN_PC5__LCDVSYNC>, @@ -166,43 +166,47 @@ bias-disable; }; - pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default { - pinmux = <PIN_PA1__SDMMC0_CMD>, - <PIN_PA2__SDMMC0_DAT0>, - <PIN_PA3__SDMMC0_DAT1>, - <PIN_PA4__SDMMC0_DAT2>, - <PIN_PA5__SDMMC0_DAT3>, - <PIN_PA6__SDMMC0_DAT4>, - <PIN_PA7__SDMMC0_DAT5>, - <PIN_PA8__SDMMC0_DAT6>, - <PIN_PA9__SDMMC0_DAT7>; - bias-pull-up; - u-boot,dm-pre-reloc; - }; - - pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { - pinmux = <PIN_PA0__SDMMC0_CK>, - <PIN_PA10__SDMMC0_RSTN>, - <PIN_PA13__SDMMC0_CD>; - bias-disable; - u-boot,dm-pre-reloc; + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_dat { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_DAT0>, + <PIN_PA3__SDMMC0_DAT1>, + <PIN_PA4__SDMMC0_DAT2>, + <PIN_PA5__SDMMC0_DAT3>, + <PIN_PA6__SDMMC0_DAT4>, + <PIN_PA7__SDMMC0_DAT5>, + <PIN_PA8__SDMMC0_DAT6>, + <PIN_PA9__SDMMC0_DAT7>; + bias-pull-up; + u-boot,dm-pre-reloc; + }; + + ck_cd { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA10__SDMMC0_RSTN>, + <PIN_PA13__SDMMC0_CD>; + bias-disable; + u-boot,dm-pre-reloc; + }; }; - pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default { - pinmux = <PIN_PA28__SDMMC1_CMD>, - <PIN_PA18__SDMMC1_DAT0>, - <PIN_PA19__SDMMC1_DAT1>, - <PIN_PA20__SDMMC1_DAT2>, - <PIN_PA21__SDMMC1_DAT3>; - bias-pull-up; - u-boot,dm-pre-reloc; - }; - - pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { - pinmux = <PIN_PA22__SDMMC1_CK>, - <PIN_PA30__SDMMC1_CD>; - bias-disable; - u-boot,dm-pre-reloc; + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_dat { + pinmux = <PIN_PA28__SDMMC1_CMD>, + <PIN_PA18__SDMMC1_DAT0>, + <PIN_PA19__SDMMC1_DAT1>, + <PIN_PA20__SDMMC1_DAT2>, + <PIN_PA21__SDMMC1_DAT3>; + bias-pull-up; + u-boot,dm-pre-reloc; + }; + + ck_cd { + pinmux = <PIN_PA22__SDMMC1_CK>, + <PIN_PA30__SDMMC1_CD>; + bias-disable; + u-boot,dm-pre-reloc; + }; }; pinctrl_uart1_default: uart1_default { diff --git a/arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi b/arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi index 8c84dd08fd..41cf9061a1 100644 --- a/arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi +++ b/arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi @@ -37,11 +37,7 @@ u-boot,dm-pre-reloc; }; -&pinctrl_sdmmc0_cmd_dat_default { - u-boot,dm-pre-reloc; -}; - -&pinctrl_sdmmc0_ck_cd_default { +&pinctrl_sdmmc0_default { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts index f3f6942143..eec183d5de 100644 --- a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts +++ b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts @@ -34,7 +34,7 @@ sdmmc0: sdio-host@a0000000 { bus-width = <4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc0_default>; status = "okay"; }; @@ -78,44 +78,44 @@ status = "okay"; }; - pioA: gpio@fc038000 { - pinctrl { - pinctrl_lcd_base: pinctrl_lcd_base { - pinmux = <PIN_PC30__LCDVSYNC>, - <PIN_PC31__LCDHSYNC>, - <PIN_PD1__LCDDEN>, - <PIN_PD0__LCDPCK>; - bias-disable; - }; + pioA: pinctrl@fc038000 { + pinctrl_lcd_base: pinctrl_lcd_base { + pinmux = <PIN_PC30__LCDVSYNC>, + <PIN_PC31__LCDHSYNC>, + <PIN_PD1__LCDDEN>, + <PIN_PD0__LCDPCK>; + bias-disable; + }; - pinctrl_lcd_pwm: pinctrl_lcd_pwm { - pinmux = <PIN_PC28__LCDPWM>; - bias-disable; - }; + pinctrl_lcd_pwm: pinctrl_lcd_pwm { + pinmux = <PIN_PC28__LCDPWM>; + bias-disable; + }; - pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 { - pinmux = <PIN_PC10__LCDDAT2>, - <PIN_PC11__LCDDAT3>, - <PIN_PC12__LCDDAT4>, - <PIN_PC13__LCDDAT5>, - <PIN_PC14__LCDDAT6>, - <PIN_PC15__LCDDAT7>, - <PIN_PC16__LCDDAT10>, - <PIN_PC17__LCDDAT11>, - <PIN_PC18__LCDDAT12>, - <PIN_PC19__LCDDAT13>, - <PIN_PC20__LCDDAT14>, - <PIN_PC21__LCDDAT15>, - <PIN_PC22__LCDDAT18>, - <PIN_PC23__LCDDAT19>, - <PIN_PC24__LCDDAT20>, - <PIN_PC25__LCDDAT21>, - <PIN_PC26__LCDDAT22>, - <PIN_PC27__LCDDAT23>; - bias-disable; - }; + pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 { + pinmux = <PIN_PC10__LCDDAT2>, + <PIN_PC11__LCDDAT3>, + <PIN_PC12__LCDDAT4>, + <PIN_PC13__LCDDAT5>, + <PIN_PC14__LCDDAT6>, + <PIN_PC15__LCDDAT7>, + <PIN_PC16__LCDDAT10>, + <PIN_PC17__LCDDAT11>, + <PIN_PC18__LCDDAT12>, + <PIN_PC19__LCDDAT13>, + <PIN_PC20__LCDDAT14>, + <PIN_PC21__LCDDAT15>, + <PIN_PC22__LCDDAT18>, + <PIN_PC23__LCDDAT19>, + <PIN_PC24__LCDDAT20>, + <PIN_PC25__LCDDAT21>, + <PIN_PC26__LCDDAT22>, + <PIN_PC27__LCDDAT23>; + bias-disable; + }; - pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default { + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_data { pinmux = <PIN_PA1__SDMMC0_CMD>, <PIN_PA2__SDMMC0_DAT0>, <PIN_PA3__SDMMC0_DAT1>, @@ -124,24 +124,24 @@ bias-disable; }; - pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { + ck_cd_vddsel { pinmux = <PIN_PA0__SDMMC0_CK>, <PIN_PA11__SDMMC0_VDDSEL>, <PIN_PA12__SDMMC0_WP>, <PIN_PA13__SDMMC0_CD>; bias-disable; }; + }; - pinctrl_uart0_default: uart0_default { - pinmux = <PIN_PB26__URXD0>, - <PIN_PB27__UTXD0>; - bias-disable; - }; + pinctrl_uart0_default: uart0_default { + pinmux = <PIN_PB26__URXD0>, + <PIN_PB27__UTXD0>; + bias-disable; + }; - pinctrl_onewire_tm_default: onewire_tm_default { - pinmux = <PIN_PC9__GPIO>; - bias-pull-up; - }; + pinctrl_onewire_tm_default: onewire_tm_default { + pinmux = <PIN_PC9__GPIO>; + bias-pull-up; }; }; }; diff --git a/arch/arm/dts/at91-sama5d2_icp.dts b/arch/arm/dts/at91-sama5d2_icp.dts index 0b0db1b2be..2dffae9c5c 100644 --- a/arch/arm/dts/at91-sama5d2_icp.dts +++ b/arch/arm/dts/at91-sama5d2_icp.dts @@ -86,75 +86,73 @@ }; }; - pioA: gpio@fc038000 { + pioA: pinctrl@fc038000 { status = "okay"; - pinctrl { - pinctrl_i2c1_default: i2c1_default { - pinmux = <PIN_PD19__TWD1>, - <PIN_PD20__TWCK1>; - bias-disable; - }; - - pinctrl_macb0_rmii: macb0_rmii { - pinmux = <PIN_PD1__GRXCK>, - <PIN_PD2__GTXER>, - <PIN_PD5__GRX2>, - <PIN_PD6__GRX3>, - <PIN_PD7__GTX2>, - <PIN_PD8__GTX3>, - <PIN_PD9__GTXCK>, - <PIN_PD10__GTXEN>, - <PIN_PD11__GRXDV>, - <PIN_PD12__GRXER>, - <PIN_PD13__GRX0>, - <PIN_PD14__GRX1>, - <PIN_PD15__GTX0>, - <PIN_PD16__GTX1>, - <PIN_PD17__GMDC>, - <PIN_PD18__GMDIO>; - bias-disable; - }; - - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = <PIN_PD3__GPIO>; - bias-disable; - }; - - pinctrl_macb0_rst: macb0_sw_rst { - pinmux = <PIN_PD4__GPIO>; - bias-pull-up; - }; - - pinctrl_mikrobus1_uart: mikrobus1_uart { - pinmux = <PIN_PB26__URXD0>, - <PIN_PB27__UTXD0>; - bias-disable; - }; - - pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default { - pinmux = <PIN_PA6__QSPI1_SCK>, - <PIN_PA11__QSPI1_CS>; - bias-disable; - }; - - pinctrl_qspi1_dat_default: qspi1_dat_default { - pinmux = <PIN_PA7__QSPI1_IO0>, - <PIN_PA8__QSPI1_IO1>, - <PIN_PA9__QSPI1_IO2>, - <PIN_PA10__QSPI1_IO3>; - bias-pull-up; - }; - - pinctrl_sdmmc0_default: sdmmc0_default { - pinmux = <PIN_PA1__SDMMC0_CMD>, - <PIN_PA2__SDMMC0_DAT0>, - <PIN_PA3__SDMMC0_DAT1>, - <PIN_PA4__SDMMC0_DAT2>, - <PIN_PA5__SDMMC0_DAT3>, - <PIN_PA0__SDMMC0_CK>, - <PIN_PA13__SDMMC0_CD>; - bias-disable; - }; + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PD19__TWD1>, + <PIN_PD20__TWCK1>; + bias-disable; + }; + + pinctrl_macb0_rmii: macb0_rmii { + pinmux = <PIN_PD1__GRXCK>, + <PIN_PD2__GTXER>, + <PIN_PD5__GRX2>, + <PIN_PD6__GRX3>, + <PIN_PD7__GTX2>, + <PIN_PD8__GTX3>, + <PIN_PD9__GTXCK>, + <PIN_PD10__GTXEN>, + <PIN_PD11__GRXDV>, + <PIN_PD12__GRXER>, + <PIN_PD13__GRX0>, + <PIN_PD14__GRX1>, + <PIN_PD15__GTX0>, + <PIN_PD16__GTX1>, + <PIN_PD17__GMDC>, + <PIN_PD18__GMDIO>; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PD3__GPIO>; + bias-disable; + }; + + pinctrl_macb0_rst: macb0_sw_rst { + pinmux = <PIN_PD4__GPIO>; + bias-pull-up; + }; + + pinctrl_mikrobus1_uart: mikrobus1_uart { + pinmux = <PIN_PB26__URXD0>, + <PIN_PB27__UTXD0>; + bias-disable; + }; + + pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default { + pinmux = <PIN_PA6__QSPI1_SCK>, + <PIN_PA11__QSPI1_CS>; + bias-disable; + }; + + pinctrl_qspi1_dat_default: qspi1_dat_default { + pinmux = <PIN_PA7__QSPI1_IO0>, + <PIN_PA8__QSPI1_IO1>, + <PIN_PA9__QSPI1_IO2>, + <PIN_PA10__QSPI1_IO3>; + bias-pull-up; + }; + + pinctrl_sdmmc0_default: sdmmc0_default { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_DAT0>, + <PIN_PA3__SDMMC0_DAT1>, + <PIN_PA4__SDMMC0_DAT2>, + <PIN_PA5__SDMMC0_DAT3>, + <PIN_PA0__SDMMC0_CK>, + <PIN_PA13__SDMMC0_CD>; + bias-disable; }; }; }; diff --git a/arch/arm/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/dts/at91-sama5d2_ptc_ek.dts index f45fb1ef26..36d52c2c5e 100644 --- a/arch/arm/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/dts/at91-sama5d2_ptc_ek.dts @@ -94,7 +94,7 @@ sdmmc0: sdio-host@a0000000 { bus-width = <8>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc0_default>; status = "okay"; u-boot,dm-pre-reloc; }; @@ -102,7 +102,7 @@ sdmmc1: sdio-host@b0000000 { bus-width = <4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc1_default>; status = "disabled"; /* conflicts with nand and qspi0*/ u-boot,dm-pre-reloc; }; @@ -137,34 +137,34 @@ }; }; - pioA: gpio@fc038000 { - pinctrl { - pinctrl_i2c1_default: i2c1_default { - pinmux = <PIN_PC6__TWD1>, - <PIN_PC7__TWCK1>; - bias-disable; - }; + pioA: pinctrl@fc038000 { + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PC6__TWD1>, + <PIN_PC7__TWCK1>; + bias-disable; + }; - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = <PIN_PB24__GPIO>; - bias-disable; - }; + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PB24__GPIO>; + bias-disable; + }; - pinctrl_macb0_rmii: macb0_rmii { - pinmux = <PIN_PB14__GTXCK>, - <PIN_PB15__GTXEN>, - <PIN_PB16__GRXDV>, - <PIN_PB17__GRXER>, - <PIN_PB18__GRX0>, - <PIN_PB19__GRX1>, - <PIN_PB20__GTX0>, - <PIN_PB21__GTX1>, - <PIN_PB22__GMDC>, - <PIN_PB23__GMDIO>; - bias-disable; - }; + pinctrl_macb0_rmii: macb0_rmii { + pinmux = <PIN_PB14__GTXCK>, + <PIN_PB15__GTXEN>, + <PIN_PB16__GRXDV>, + <PIN_PB17__GRXER>, + <PIN_PB18__GRX0>, + <PIN_PB19__GRX1>, + <PIN_PB20__GTX0>, + <PIN_PB21__GTX1>, + <PIN_PB22__GMDC>, + <PIN_PB23__GMDIO>; + bias-disable; + }; - pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default { + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_dat { pinmux = <PIN_PA1__SDMMC0_CMD>, <PIN_PA2__SDMMC0_DAT0>, <PIN_PA3__SDMMC0_DAT1>, @@ -178,7 +178,7 @@ u-boot,dm-pre-reloc; }; - pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { + ck_cd { pinmux = <PIN_PA0__SDMMC0_CK>, <PIN_PA10__SDMMC0_RSTN>, <PIN_PA11__SDMMC0_VDDSEL>, @@ -186,8 +186,10 @@ bias-disable; u-boot,dm-pre-reloc; }; + }; - pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default { + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_dat { pinmux = <PIN_PA28__SDMMC1_CMD>, <PIN_PA18__SDMMC1_DAT0>, <PIN_PA19__SDMMC1_DAT1>, @@ -197,34 +199,34 @@ u-boot,dm-pre-reloc; }; - pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { + ck_cd { pinmux = <PIN_PA22__SDMMC1_CK>, <PIN_PA30__SDMMC1_CD>; bias-disable; u-boot,dm-pre-reloc; }; + }; - pinctrl_uart0_default: uart0_default { - pinmux = <PIN_PB26__URXD0>, - <PIN_PB27__UTXD0>; - bias-disable; - u-boot,dm-pre-reloc; - }; + pinctrl_uart0_default: uart0_default { + pinmux = <PIN_PB26__URXD0>, + <PIN_PB27__UTXD0>; + bias-disable; + u-boot,dm-pre-reloc; + }; - pinctrl_usb_default: usb_default { - pinmux = <PIN_PB12__GPIO>; - bias-disable; - }; + pinctrl_usb_default: usb_default { + pinmux = <PIN_PB12__GPIO>; + bias-disable; + }; - pinctrl_usba_vbus: usba_vbus { - pinmux = <PIN_PB11__GPIO>; - bias-disable; - }; + pinctrl_usba_vbus: usba_vbus { + pinmux = <PIN_PB11__GPIO>; + bias-disable; + }; - pinctrl_onewire_tm_default: onewire_tm_default { - pinmux = <PIN_PB31__GPIO>; - bias-pull-up; - }; + pinctrl_onewire_tm_default: onewire_tm_default { + pinmux = <PIN_PB31__GPIO>; + bias-pull-up; }; }; }; diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts b/arch/arm/dts/at91-sama5d2_xplained.dts index 34b64a22af..78a3a851bb 100644 --- a/arch/arm/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/dts/at91-sama5d2_xplained.dts @@ -44,7 +44,7 @@ sdmmc0: sdio-host@a0000000 { bus-width = <8>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc0_default>; status = "okay"; u-boot,dm-pre-reloc; }; @@ -52,7 +52,7 @@ sdmmc1: sdio-host@b0000000 { bus-width = <4>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; + pinctrl-0 = <&pinctrl_sdmmc1_default>; status = "okay"; /* conflict with qspi0 */ u-boot,dm-pre-reloc; }; @@ -143,85 +143,85 @@ }; }; - pioA: gpio@fc038000 { - pinctrl { - pinctrl_i2c1_default: i2c1_default { - pinmux = <PIN_PD4__TWD1>, - <PIN_PD5__TWCK1>; - bias-disable; - }; + pioA: pinctrl@fc038000 { + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PD4__TWD1>, + <PIN_PD5__TWCK1>; + bias-disable; + }; - pinctrl_lcd_base: pinctrl_lcd_base { - pinmux = <PIN_PC30__LCDVSYNC>, - <PIN_PC31__LCDHSYNC>, - <PIN_PD1__LCDDEN>, - <PIN_PD0__LCDPCK>; - bias-disable; - }; + pinctrl_lcd_base: pinctrl_lcd_base { + pinmux = <PIN_PC30__LCDVSYNC>, + <PIN_PC31__LCDHSYNC>, + <PIN_PD1__LCDDEN>, + <PIN_PD0__LCDPCK>; + bias-disable; + }; - pinctrl_lcd_pwm: pinctrl_lcd_pwm { - pinmux = <PIN_PC28__LCDPWM>; - bias-disable; - }; + pinctrl_lcd_pwm: pinctrl_lcd_pwm { + pinmux = <PIN_PC28__LCDPWM>; + bias-disable; + }; - pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 { - pinmux = <PIN_PC10__LCDDAT2>, - <PIN_PC11__LCDDAT3>, - <PIN_PC12__LCDDAT4>, - <PIN_PC13__LCDDAT5>, - <PIN_PC14__LCDDAT6>, - <PIN_PC15__LCDDAT7>, - <PIN_PC16__LCDDAT10>, - <PIN_PC17__LCDDAT11>, - <PIN_PC18__LCDDAT12>, - <PIN_PC19__LCDDAT13>, - <PIN_PC20__LCDDAT14>, - <PIN_PC21__LCDDAT15>, - <PIN_PC22__LCDDAT18>, - <PIN_PC23__LCDDAT19>, - <PIN_PC24__LCDDAT20>, - <PIN_PC25__LCDDAT21>, - <PIN_PC26__LCDDAT22>, - <PIN_PC27__LCDDAT23>; - bias-disable; - }; + pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 { + pinmux = <PIN_PC10__LCDDAT2>, + <PIN_PC11__LCDDAT3>, + <PIN_PC12__LCDDAT4>, + <PIN_PC13__LCDDAT5>, + <PIN_PC14__LCDDAT6>, + <PIN_PC15__LCDDAT7>, + <PIN_PC16__LCDDAT10>, + <PIN_PC17__LCDDAT11>, + <PIN_PC18__LCDDAT12>, + <PIN_PC19__LCDDAT13>, + <PIN_PC20__LCDDAT14>, + <PIN_PC21__LCDDAT15>, + <PIN_PC22__LCDDAT18>, + <PIN_PC23__LCDDAT19>, + <PIN_PC24__LCDDAT20>, + <PIN_PC25__LCDDAT21>, + <PIN_PC26__LCDDAT22>, + <PIN_PC27__LCDDAT23>; + bias-disable; + }; - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = <PIN_PC9__GPIO>; - bias-disable; - }; + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PC9__GPIO>; + bias-disable; + }; - pinctrl_macb0_rmii: macb0_rmii { - pinmux = <PIN_PB14__GTXCK>, - <PIN_PB15__GTXEN>, - <PIN_PB16__GRXDV>, - <PIN_PB17__GRXER>, - <PIN_PB18__GRX0>, - <PIN_PB19__GRX1>, - <PIN_PB20__GTX0>, - <PIN_PB21__GTX1>, - <PIN_PB22__GMDC>, - <PIN_PB23__GMDIO>; - bias-disable; - }; + pinctrl_macb0_rmii: macb0_rmii { + pinmux = <PIN_PB14__GTXCK>, + <PIN_PB15__GTXEN>, + <PIN_PB16__GRXDV>, + <PIN_PB17__GRXER>, + <PIN_PB18__GRX0>, + <PIN_PB19__GRX1>, + <PIN_PB20__GTX0>, + <PIN_PB21__GTX1>, + <PIN_PB22__GMDC>, + <PIN_PB23__GMDIO>; + bias-disable; + }; - pinctrl_qspi0_sck_cs_default: qspi0_sck_cs_default { - pinmux = <PIN_PA22__QSPI0_SCK>, - <PIN_PA23__QSPI0_CS>; - bias-disable; - u-boot,dm-pre-reloc; - }; + pinctrl_qspi0_sck_cs_default: qspi0_sck_cs_default { + pinmux = <PIN_PA22__QSPI0_SCK>, + <PIN_PA23__QSPI0_CS>; + bias-disable; + u-boot,dm-pre-reloc; + }; - pinctrl_qspi0_dat_default: qspi0_dat_default { - pinmux = <PIN_PA24__QSPI0_IO0>, - <PIN_PA25__QSPI0_IO1>, - <PIN_PA26__QSPI0_IO2>, - <PIN_PA27__QSPI0_IO3>; - bias-pull-up; - u-boot,dm-pre-reloc; - }; + pinctrl_qspi0_dat_default: qspi0_dat_default { + pinmux = <PIN_PA24__QSPI0_IO0>, + <PIN_PA25__QSPI0_IO1>, + <PIN_PA26__QSPI0_IO2>, + <PIN_PA27__QSPI0_IO3>; + bias-pull-up; + u-boot,dm-pre-reloc; + }; - pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default { + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_dat { pinmux = <PIN_PA1__SDMMC0_CMD>, <PIN_PA2__SDMMC0_DAT0>, <PIN_PA3__SDMMC0_DAT1>, @@ -235,7 +235,7 @@ u-boot,dm-pre-reloc; }; - pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { + ck_cd_default { pinmux = <PIN_PA0__SDMMC0_CK>, <PIN_PA10__SDMMC0_RSTN>, <PIN_PA11__SDMMC0_VDDSEL>, @@ -243,8 +243,10 @@ bias-disable; u-boot,dm-pre-reloc; }; + }; - pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default { + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_dat { pinmux = <PIN_PA28__SDMMC1_CMD>, <PIN_PA18__SDMMC1_DAT0>, <PIN_PA19__SDMMC1_DAT1>, @@ -254,42 +256,42 @@ u-boot,dm-pre-reloc; }; - pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { + ck_cd { pinmux = <PIN_PA22__SDMMC1_CK>, <PIN_PA30__SDMMC1_CD>; bias-disable; u-boot,dm-pre-reloc; }; + }; - pinctrl_spi0_default: spi0_default { - pinmux = <PIN_PA14__SPI0_SPCK>, - <PIN_PA15__SPI0_MOSI>, - <PIN_PA16__SPI0_MISO>; - bias-disable; - u-boot,dm-pre-reloc; - }; + pinctrl_spi0_default: spi0_default { + pinmux = <PIN_PA14__SPI0_SPCK>, + <PIN_PA15__SPI0_MOSI>, + <PIN_PA16__SPI0_MISO>; + bias-disable; + u-boot,dm-pre-reloc; + }; - pinctrl_uart1_default: uart1_default { - pinmux = <PIN_PD2__URXD1>, - <PIN_PD3__UTXD1>; - bias-disable; - u-boot,dm-pre-reloc; - }; + pinctrl_uart1_default: uart1_default { + pinmux = <PIN_PD2__URXD1>, + <PIN_PD3__UTXD1>; + bias-disable; + u-boot,dm-pre-reloc; + }; - pinctrl_usb_default: usb_default { - pinmux = <PIN_PB10__GPIO>; - bias-disable; - }; + pinctrl_usb_default: usb_default { + pinmux = <PIN_PB10__GPIO>; + bias-disable; + }; - pinctrl_usba_vbus: usba_vbus { - pinmux = <PIN_PA31__GPIO>; - bias-disable; - }; + pinctrl_usba_vbus: usba_vbus { + pinmux = <PIN_PA31__GPIO>; + bias-disable; + }; - pinctrl_onewire_tm_default: onewire_tm_default { - pinmux = <PIN_PB0__GPIO>; - bias-pull-up; - }; + pinctrl_onewire_tm_default: onewire_tm_default { + pinmux = <PIN_PB0__GPIO>; + bias-pull-up; }; }; }; diff --git a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi index 601386788f..d294ddb54a 100644 --- a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi +++ b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi @@ -28,7 +28,7 @@ u-boot,dm-pre-reloc; }; -&pinctrl { +&pioA { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/at91-sama7g5ek.dts b/arch/arm/dts/at91-sama7g5ek.dts index eaba0de3f7..aed84f15a1 100644 --- a/arch/arm/dts/at91-sama7g5ek.dts +++ b/arch/arm/dts/at91-sama7g5ek.dts @@ -690,46 +690,67 @@ }; pinctrl_sdmmc0_default: sdmmc0_default { - pinmux = <PIN_PA1__SDMMC0_CMD>, - <PIN_PA3__SDMMC0_DAT0>, - <PIN_PA4__SDMMC0_DAT1>, - <PIN_PA5__SDMMC0_DAT2>, - <PIN_PA6__SDMMC0_DAT3>, - <PIN_PA7__SDMMC0_DAT4>, - <PIN_PA8__SDMMC0_DAT5>, - <PIN_PA9__SDMMC0_DAT6>, - <PIN_PA10__SDMMC0_DAT7>, - <PIN_PA0__SDMMC0_CK>, - <PIN_PA2__SDMMC0_RSTN>, - <PIN_PA14__SDMMC0_CD>, - <PIN_PA11__SDMMC0_DS>; + cmd_data { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA3__SDMMC0_DAT0>, + <PIN_PA4__SDMMC0_DAT1>, + <PIN_PA5__SDMMC0_DAT2>, + <PIN_PA6__SDMMC0_DAT3>, + <PIN_PA7__SDMMC0_DAT4>, + <PIN_PA8__SDMMC0_DAT5>, + <PIN_PA9__SDMMC0_DAT6>, + <PIN_PA10__SDMMC0_DAT7>; slew-rate = <0>; bias-pull-up; + }; + + ck_cd_rstn_vddsel { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA2__SDMMC0_RSTN>, + <PIN_PA14__SDMMC0_CD>, + <PIN_PA11__SDMMC0_DS>; + slew-rate = <0>; + bias-pull-up; + }; }; pinctrl_sdmmc1_default: sdmmc1_default { - pinmux = <PIN_PB29__SDMMC1_CMD>, - <PIN_PB31__SDMMC1_DAT0>, - <PIN_PC0__SDMMC1_DAT1>, - <PIN_PC1__SDMMC1_DAT2>, - <PIN_PC2__SDMMC1_DAT3>, - <PIN_PB30__SDMMC1_CK>, - <PIN_PB28__SDMMC1_RSTN>, - <PIN_PC5__SDMMC1_1V8SEL>, - <PIN_PC4__SDMMC1_CD>; - slew-rate = <0>; - bias-pull-up; + cmd_data { + pinmux = <PIN_PB29__SDMMC1_CMD>, + <PIN_PB31__SDMMC1_DAT0>, + <PIN_PC0__SDMMC1_DAT1>, + <PIN_PC1__SDMMC1_DAT2>, + <PIN_PC2__SDMMC1_DAT3>; + slew-rate = <0>; + bias-pull-up; + }; + + ck_cd_rstn_vddsel { + pinmux = <PIN_PB30__SDMMC1_CK>, + <PIN_PB28__SDMMC1_RSTN>, + <PIN_PC5__SDMMC1_1V8SEL>, + <PIN_PC4__SDMMC1_CD>; + slew-rate = <0>; + bias-pull-up; + }; }; pinctrl_sdmmc2_default: sdmmc2_default { - pinmux = <PIN_PD3__SDMMC2_CMD>, - <PIN_PD5__SDMMC2_DAT0>, - <PIN_PD6__SDMMC2_DAT1>, - <PIN_PD7__SDMMC2_DAT2>, - <PIN_PD8__SDMMC2_DAT3>, - <PIN_PD4__SDMMC2_CK>; - slew-rate = <0>; - bias-pull-up; + cmd_data { + pinmux = <PIN_PD3__SDMMC2_CMD>, + <PIN_PD5__SDMMC2_DAT0>, + <PIN_PD6__SDMMC2_DAT1>, + <PIN_PD7__SDMMC2_DAT2>, + <PIN_PD8__SDMMC2_DAT3>; + slew-rate = <0>; + bias-pull-up; + }; + + ck { + pinmux = <PIN_PD4__SDMMC2_CK>; + slew-rate = <0>; + bias-pull-up; + }; }; pinctrl_spdifrx_default: spdifrx_default { diff --git a/arch/arm/dts/dragonboard410c-uboot.dtsi b/arch/arm/dts/dragonboard410c-uboot.dtsi index 9c1be2566f..e4fecaa19e 100644 --- a/arch/arm/dts/dragonboard410c-uboot.dtsi +++ b/arch/arm/dts/dragonboard410c-uboot.dtsi @@ -14,7 +14,7 @@ soc { u-boot,dm-pre-reloc; - qcom,tlmm@1000000 { + pinctrl@1000000 { u-boot,dm-pre-reloc; uart { diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts index 50523712cb..59cf45eb17 100644 --- a/arch/arm/dts/dragonboard410c.dts +++ b/arch/arm/dts/dragonboard410c.dts @@ -60,9 +60,13 @@ reg = <0x60000 0x8000>; }; - pinctrl: qcom,tlmm@1000000 { - compatible = "qcom,tlmm-apq8016"; + soc_gpios: pinctrl@1000000 { + compatible = "qcom,msm8916-pinctrl"; reg = <0x1000000 0x400000>; + gpio-controller; + gpio-count = <122>; + gpio-bank-name="soc"; + #gpio-cells = <2>; blsp1_uart: uart { function = "blsp1_uart"; @@ -86,15 +90,6 @@ pinctrl-0 = <&blsp1_uart>; }; - soc_gpios: pinctrl@1000000 { - compatible = "qcom,apq8016-pinctrl"; - reg = <0x1000000 0x300000>; - gpio-controller; - gpio-count = <122>; - gpio-bank-name="soc"; - #gpio-cells = <2>; - }; - ehci@78d9000 { compatible = "qcom,ehci-host"; reg = <0x78d9000 0x400>; diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi b/arch/arm/dts/dragonboard820c-uboot.dtsi index 8610d7ec37..2270ac73bf 100644 --- a/arch/arm/dts/dragonboard820c-uboot.dtsi +++ b/arch/arm/dts/dragonboard820c-uboot.dtsi @@ -13,7 +13,7 @@ soc { u-boot,dm-pre-reloc; - qcom,tlmm@1010000 { + pinctrl@1010000 { u-boot,dm-pre-reloc; uart { diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts index b72a2471cf..aaca681d2e 100644 --- a/arch/arm/dts/dragonboard820c.dts +++ b/arch/arm/dts/dragonboard820c.dts @@ -64,8 +64,8 @@ reg = <0x300000 0x90000>; }; - pinctrl: qcom,tlmm@1010000 { - compatible = "qcom,tlmm-apq8096"; + pinctrl: pinctrl@1010000 { + compatible = "qcom,msm8996-pinctrl"; reg = <0x1010000 0x400000>; blsp8_uart: uart { diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts index 30a9137407..b44f19f05a 100644 --- a/arch/arm/dts/mt7622-rfb.dts +++ b/arch/arm/dts/mt7622-rfb.dts @@ -159,6 +159,14 @@ }; }; + + i2c1_pins_default: i2c1-default { + mux { + function = "i2c"; + groups = "i2c1_0"; + }; + }; + }; &snfi { @@ -242,3 +250,13 @@ &u3phy { status = "okay"; }; + +&soft_i2c { + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_default>; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index 0127474c95..2d89fa08b4 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -175,6 +175,7 @@ status = "disabled"; assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; + mediatek,force-highspeed; }; mmc0: mmc@11230000 { @@ -423,4 +424,28 @@ status = "disabled"; }; + soft_i2c: soft_i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + gpios = <&gpio 56 GPIO_ACTIVE_HIGH>, /* SDA */ + <&gpio 55 GPIO_ACTIVE_HIGH>; /* CLK */ + i2c-gpio,delay-us = <5>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt7622-i2c"; + reg = <0x11008000 0x90>, + <0x11000180 0x80>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C1_PD>, + <&pericfg CLK_PERI_AP_DMA_PD>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; diff --git a/arch/arm/dts/mt7981-emmc-rfb.dts b/arch/arm/dts/mt7981-emmc-rfb.dts new file mode 100644 index 0000000000..2b7eae99ce --- /dev/null +++ b/arch/arm/dts/mt7981-emmc-rfb.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7981.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "mt7981-rfb"; + compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&pinctrl { + spic_pins: spi1-pins-func-1 { + mux { + function = "spi"; + groups = "spi1_1"; + }; + }; + + uart1_pins: spi1-pins-func-3 { + mux { + function = "uart"; + groups = "uart1_2"; + }; + }; + + /* pin15 as pwm0 */ + one_pwm_pins: one-pwm-pins { + mux { + function = "pwm"; + groups = "pwm0_1"; + }; + }; + + /* pin15 as pwm0 and pin14 as pwm1 */ + two_pwm_pins: two-pwm-pins { + mux { + function = "pwm"; + groups = "pwm0_1", "pwm1_0"; + }; + }; + + /* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */ + three_pwm_pins: three-pwm-pins { + mux { + function = "pwm"; + groups = "pwm0_1", "pwm1_0", "pwm2"; + }; + }; + + mmc0_pins_default: mmc0default { + mux { + function = "flash"; + groups = "emmc_45"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI0_HOLD", "SPI0_WP", + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + conf-rst { + pins = "PWM0"; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&two_pwm_pins>; + status = "okay"; +}; + +&watchdog { + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + bus-width = <8>; + max-frequency = <52000000>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7981-rfb.dts b/arch/arm/dts/mt7981-rfb.dts new file mode 100644 index 0000000000..5559ace953 --- /dev/null +++ b/arch/arm/dts/mt7981-rfb.dts @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7981.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "mt7981-rfb"; + compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&pinctrl { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_11>; + }; + }; + + spi2_flash_pins: spi2-spi2-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_00>; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_00>; + }; + }; + + spic_pins: spi1-pins-func-1 { + mux { + function = "spi"; + groups = "spi1_1"; + }; + }; + + uart1_pins: spi1-pins-func-3 { + mux { + function = "uart"; + groups = "uart1_2"; + }; + }; + + /* pin15 as pwm0 */ + one_pwm_pins: one-pwm-pins { + mux { + function = "pwm"; + groups = "pwm0_1"; + }; + }; + + /* pin15 as pwm0 and pin14 as pwm1 */ + two_pwm_pins: two-pwm-pins { + mux { + function = "pwm"; + groups = "pwm0_1", "pwm1_0"; + }; + }; + + /* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */ + three_pwm_pins: three-pwm-pins { + mux { + function = "pwm"; + groups = "pwm0_1", "pwm1_0", "pwm2"; + }; + }; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + }; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&two_pwm_pins>; + status = "okay"; +}; + +&watchdog { + status = "disabled"; +}; diff --git a/arch/arm/dts/mt7981-sd-rfb.dts b/arch/arm/dts/mt7981-sd-rfb.dts new file mode 100644 index 0000000000..34ac227ecf --- /dev/null +++ b/arch/arm/dts/mt7981-sd-rfb.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7981.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "mt7981-rfb"; + compatible = "mediatek,mt7981", "mediatek,mt7981-sd-rfb"; + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&pinctrl { + spic_pins: spi1-pins-func-1 { + mux { + function = "spi"; + groups = "spi1_1"; + }; + }; + + uart1_pins: spi1-pins-func-3 { + mux { + function = "uart"; + groups = "uart1_2"; + }; + }; + + /* pin15 as pwm0 */ + one_pwm_pins: one-pwm-pins { + mux { + function = "pwm"; + groups = "pwm0_1"; + }; + }; + + /* pin15 as pwm0 and pin14 as pwm1 */ + two_pwm_pins: two-pwm-pins { + mux { + function = "pwm"; + groups = "pwm0_1", "pwm1_0"; + }; + }; + + /* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */ + three_pwm_pins: three-pwm-pins { + mux { + function = "pwm"; + groups = "pwm0_1", "pwm1_0", "pwm2"; + }; + }; + + mmc0_pins_default: mmc0default { + mux { + function = "flash"; + groups = "emmc_45"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI0_HOLD", "SPI0_WP", + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + conf-rst { + pins = "PWM0"; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&two_pwm_pins>; + status = "okay"; +}; + +&watchdog { + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + r_smpl = <0>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi new file mode 100644 index 0000000000..3089371805 --- /dev/null +++ b/arch/arm/dts/mt7981.dtsi @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/mt7981-clk.h> +#include <dt-bindings/reset/mt7629-reset.h> +#include <dt-bindings/pinctrl/mt65xx.h> + +/ { + compatible = "mediatek,mt7981"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + mediatek,hwver = <&hwver>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + mediatek,hwver = <&hwver>; + }; + }; + + gpt_clk: gpt_dummy20m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + u-boot,dm-pre-reloc; + }; + + hwver: hwver { + compatible = "mediatek,hwver", "syscon"; + reg = <0x8000000 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + clock-frequency = <13000000>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + arm,cpu-registers-not-fw-configured; + }; + + timer0: timer@10008000 { + compatible = "mediatek,mt7986-timer"; + reg = <0x10008000 0x1000>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gpt_clk>; + clock-names = "gpt-clk"; + u-boot,dm-pre-reloc; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7986-wdt"; + reg = <0x1001c000 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + status = "disabled"; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0x0c000000 0x40000>, /* GICD */ + <0x0c080000 0x200000>; /* GICR */ + + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + fixed_plls: apmixedsys@1001e000 { + compatible = "mediatek,mt7981-fixed-plls"; + reg = <0x1001e000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + topckgen: topckgen@1001b000 { + compatible = "mediatek,mt7981-topckgen"; + reg = <0x1001b000 0x1000>; + clock-parent = <&fixed_plls>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + infracfg_ao: infracfg_ao@10001000 { + compatible = "mediatek,mt7981-infracfg_ao"; + reg = <0x10001000 0x80>; + clock-parent = <&infracfg>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt7981-infracfg"; + reg = <0x10001000 0x30>; + clock-parent = <&topckgen>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + pinctrl: pinctrl@11d00000 { + compatible = "mediatek,mt7981-pinctrl"; + reg = <0x11d00000 0x1000>, + <0x11c00000 0x1000>, + <0x11c10000 0x1000>, + <0x11d20000 0x1000>, + <0x11e00000 0x1000>, + <0x11e20000 0x1000>, + <0x11f00000 0x1000>, + <0x11f10000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base", + "iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base", + "iocfg_tm_base", "iocfg_tl_base", "eint"; + gpio: gpio-controller { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + pwm: pwm@10048000 { + compatible = "mediatek,mt7981-pwm"; + reg = <0x10048000 0x1000>; + #clock-cells = <1>; + #pwm-cells = <2>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CK_INFRA_PWM>, + <&infracfg_ao CK_INFRA_PWM_BSEL>, + <&infracfg_ao CK_INFRA_PWM1_CK>, + <&infracfg_ao CK_INFRA_PWM2_CK>, + /* FIXME */ + <&infracfg_ao CK_INFRA_PWM2_CK>; + assigned-clocks = <&topckgen CK_TOP_PWM_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + status = "disabled"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,hsuart"; + reg = <0x11002000 0x400>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg_ao CK_INFRA_UART0_CK>; + assigned-clocks = <&topckgen CK_TOP_UART_SEL>, + <&infracfg_ao CK_INFRA_UART0_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, + <&infracfg CK_INFRA_UART>; + mediatek,force-highspeed; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + uart1: serial@11003000 { + compatible = "mediatek,hsuart"; + reg = <0x11003000 0x400>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg_ao CK_INFRA_UART1_CK>; + assigned-clocks = <&topckgen CK_TOP_UART_SEL>, + <&infracfg_ao CK_INFRA_UART1_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, + <&infracfg CK_INFRA_UART>; + mediatek,force-highspeed; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,hsuart"; + reg = <0x11004000 0x400>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg_ao CK_INFRA_UART2_CK>; + assigned-clocks = <&topckgen CK_TOP_UART_SEL>, + <&infracfg_ao CK_INFRA_UART2_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, + <&infracfg CK_INFRA_UART>; + mediatek,force-highspeed; + status = "disabled"; + }; + + snand: snand@11005000 { + compatible = "mediatek,mt7986-snand"; + reg = <0x11005000 0x1000>, + <0x11006000 0x1000>; + reg-names = "nfi", "ecc"; + clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>, + <&infracfg_ao CK_INFRA_NFI1_CK>, + <&infracfg_ao CK_INFRA_NFI_HCK_CK>; + clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; + assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, + <&topckgen CK_TOP_NFI1X_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, + <&topckgen CK_TOP_CB_M_D8>; + status = "disabled"; + }; + + ethsys: syscon@15000000 { + compatible = "mediatek,mt7981-ethsys", "syscon"; + reg = <0x15000000 0x1000>; + clock-parent = <&topckgen>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7981-eth", "syscon"; + reg = <0x15100000 0x20000>; + resets = <ðsys ETHSYS_FE_RST>; + reset-names = "fe"; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7986-sgmiisys", "syscon"; + reg = <0x10060000 0x1000>; + pn_swap; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7986-sgmiisys", "syscon"; + reg = <0x10070000 0x1000>; + #clock-cells = <1>; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,ipm-spi"; + reg = <0x1100a000 0x100>; + clocks = <&infracfg_ao CK_INFRA_SPI0_CK>, + <&topckgen CK_TOP_SPI_SEL>; + assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, + <&infracfg CK_INFRA_SPI0_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, + <&topckgen CK_INFRA_ISPI0>; + clock-names = "sel-clk", "spi-clk"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + spi1: spi@1100b000 { + compatible = "mediatek,ipm-spi"; + reg = <0x1100b000 0x100>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + spi2: spi@11009000 { + compatible = "mediatek,ipm-spi"; + reg = <0x11009000 0x100>; + clocks = <&infracfg_ao CK_INFRA_SPI0_CK>, + <&topckgen CK_TOP_SPI_SEL>; + assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, + <&infracfg CK_INFRA_SPI0_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, + <&topckgen CK_INFRA_ISPI0>; + clock-names = "sel-clk", "spi-clk"; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt7981-mmc"; + reg = <0x11230000 0x1000>, + <0x11C20000 0x1000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CK_TOP_EMMC_400M>, + <&topckgen CK_TOP_EMMC_208M>, + <&infracfg_ao CK_INFRA_MSDC_CK>; + assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>, + <&topckgen CK_TOP_EMMC_208M_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>, + <&topckgen CK_TOP_CB_M_D2>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + +}; diff --git a/arch/arm/dts/mt7986-u-boot.dtsi b/arch/arm/dts/mt7986-u-boot.dtsi new file mode 100644 index 0000000000..95671f8afa --- /dev/null +++ b/arch/arm/dts/mt7986-u-boot.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +&topckgen { + u-boot,dm-pre-reloc; +}; + +&pericfg { + u-boot,dm-pre-reloc; +}; + +&apmixedsys { + u-boot,dm-pre-reloc; +}; + +&timer0 { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&snand { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi new file mode 100644 index 0000000000..794ab1f4bd --- /dev/null +++ b/arch/arm/dts/mt7986.dtsi @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/clock/mt7986-clk.h> +#include <dt-bindings/reset/mt7629-reset.h> +#include <dt-bindings/pinctrl/mt65xx.h> + +/ { + compatible = "mediatek,mt7986"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + config { + u-boot,mmc-env-partition = "u-boot-env"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + mediatek,hwver = <&hwver>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + mediatek,hwver = <&hwver>; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + mediatek,hwver = <&hwver>; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + mediatek,hwver = <&hwver>; + }; + }; + + dummy_clk: dummy12m { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + #clock-cells = <0>; + /* must need this line, or uart uanable to get dummy_clk */ + u-boot,dm-pre-reloc; + }; + + hwver: hwver { + compatible = "mediatek,hwver", "syscon"; + reg = <0x8000000 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + clock-frequency = <13000000>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + arm,cpu-registers-not-fw-configured; + }; + + timer0: timer@10008000 { + compatible = "mediatek,mt7986-timer"; + reg = <0x10008000 0x1000>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CK_INFRA_CK_F26M>; + clock-names = "gpt-clk"; + u-boot,dm-pre-reloc; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7986-wdt"; + reg = <0x1001c000 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + status = "disabled"; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0x0c000000 0x40000>, /* GICD */ + <0x0c080000 0x200000>; /* GICR */ + + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + fixed_plls: apmixedsys@1001E000 { + compatible = "mediatek,mt7986-fixed-plls"; + reg = <0x1001E000 0x1000>; + #clock-cells = <1>; + }; + + topckgen: topckgen@1001B000 { + compatible = "mediatek,mt7986-topckgen"; + reg = <0x1001B000 0x1000>; + clock-parent = <&fixed_plls>; + #clock-cells = <1>; + }; + + infracfg_ao: infracfg_ao@10001000 { + compatible = "mediatek,mt7986-infracfg_ao"; + reg = <0x10001000 0x68>; + clock-parent = <&infracfg>; + #clock-cells = <1>; + }; + + infracfg: infracfg@10001040 { + compatible = "mediatek,mt7986-infracfg"; + reg = <0x10001000 0x1000>; + clock-parent = <&topckgen>; + #clock-cells = <1>; + }; + + pinctrl: pinctrl@1001f000 { + compatible = "mediatek,mt7986-pinctrl"; + reg = <0x1001f000 0x1000>, + <0x11c30000 0x1000>, + <0x11c40000 0x1000>, + <0x11e20000 0x1000>, + <0x11e30000 0x1000>, + <0x11f00000 0x1000>, + <0x11f10000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base", + "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base", + "iocfg_tl_base", "eint"; + gpio: gpio-controller { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + pwm: pwm@10048000 { + compatible = "mediatek,mt7986-pwm"; + reg = <0x10048000 0x1000>; + #clock-cells = <1>; + #pwm-cells = <2>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CK_INFRA_PWM>, + <&infracfg_ao CK_INFRA_PWM_BSEL>, + <&infracfg_ao CK_INFRA_PWM1_CK>, + <&infracfg_ao CK_INFRA_PWM2_CK>; + assigned-clocks = <&topckgen CK_TOP_PWM_SEL>, + <&infracfg CK_INFRA_PWM_BSEL>, + <&infracfg CK_INFRA_PWM1_SEL>, + <&infracfg CK_INFRA_PWM2_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>, + <&infracfg CK_INFRA_PWM>, + <&infracfg CK_INFRA_PWM>, + <&infracfg CK_INFRA_PWM>; + clock-names = "top", "main", "pwm1", "pwm2"; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + uart0: serial@11002000 { + compatible = "mediatek,hsuart"; + reg = <0x11002000 0x400>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg_ao CK_INFRA_UART0_CK>; + assigned-clocks = <&topckgen CK_TOP_UART_SEL>, + <&infracfg_ao CK_INFRA_UART0_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, + <&infracfg CK_INFRA_UART>; + mediatek,force-highspeed; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + uart1: serial@11003000 { + compatible = "mediatek,hsuart"; + reg = <0x11003000 0x400>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg_ao CK_INFRA_UART1_CK>; + assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>; + assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; + mediatek,force-highspeed; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,hsuart"; + reg = <0x11004000 0x400>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg_ao CK_INFRA_UART2_CK>; + assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>; + assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; + mediatek,force-highspeed; + status = "disabled"; + }; + + snand: snand@11005000 { + compatible = "mediatek,mt7986-snand"; + reg = <0x11005000 0x1000>, + <0x11006000 0x1000>; + reg-names = "nfi", "ecc"; + clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>, + <&infracfg_ao CK_INFRA_NFI1_CK>, + <&infracfg_ao CK_INFRA_NFI_HCK_CK>; + clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; + assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, + <&topckgen CK_TOP_NFI1X_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, + <&topckgen CK_TOP_CB_M_D8>; + status = "disabled"; + }; + + ethsys: syscon@15000000 { + compatible = "mediatek,mt7986-ethsys", "syscon"; + reg = <0x15000000 0x1000>; + clock-parent = <&topckgen>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7986-eth", "syscon"; + reg = <0x15100000 0x20000>; + resets = <ðsys ETHSYS_FE_RST>; + reset-names = "fe"; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7986-sgmiisys", "syscon"; + reg = <0x10060000 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7986-sgmiisys", "syscon"; + reg = <0x10070000 0x1000>; + #clock-cells = <1>; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,ipm-spi"; + reg = <0x1100a000 0x100>; + clocks = <&infracfg_ao CK_INFRA_SPI0_CK>, + <&topckgen CK_TOP_SPI_SEL>; + assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, + <&infracfg CK_INFRA_SPI0_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, + <&topckgen CK_INFRA_ISPI0>; + clock-names = "sel-clk", "spi-clk"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + spi1: spi@1100b000 { + compatible = "mediatek,ipm-spi"; + reg = <0x1100b000 0x100>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt7986-mmc"; + reg = <0x11230000 0x1000>, + <0x11C20000 0x1000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CK_TOP_EMMC_416M>, + <&topckgen CK_TOP_EMMC_250M>, + <&infracfg_ao CK_INFRA_MSDC_CK>; + assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>, + <&topckgen CK_TOP_EMMC_250M_SEL>; + assigned-clock-parents = <&topckgen CK_TOP_CB_M_416M>, + <&topckgen CK_TOP_NET1_D5_D2>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + xhci: xhci@11200000 { + compatible = "mediatek,mt7986-xhci", + "mediatek,mtk-xhci"; + reg = <0x11200000 0x2e00>, + <0x11203e00 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>, + <&u2port1 PHY_TYPE_USB2>; + clocks = <&dummy_clk>, + <&dummy_clk>, + <&dummy_clk>, + <&dummy_clk>, + <&dummy_clk>; + clock-names = "sys_ck", + "xhci_ck", + "ref_ck", + "mcu_ck", + "dma_ck"; + tpl-support; + status = "okay"; + }; + + usbtphy: usb-phy@11e10000 { + compatible = "mediatek,mt7986", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + u2port0: usb-phy@11e10000 { + reg = <0x11e10000 0x700>; + clocks = <&dummy_clk>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@11e10700 { + reg = <0x11e10700 0x900>; + clocks = <&dummy_clk>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u2port1: usb-phy@11e11000 { + reg = <0x11e11000 0x700>; + clocks = <&dummy_clk>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/dts/mt7986a-emmc-rfb.dts b/arch/arm/dts/mt7986a-emmc-rfb.dts new file mode 100644 index 0000000000..315bdd0b14 --- /dev/null +++ b/arch/arm/dts/mt7986a-emmc-rfb.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7986a-rfb.dts" + +/ { + compatible = "mediatek,mt7986", "mediatek,mt7986-rfb", + "mediatek,mt7986-emmc-rfb"; + bl2_verify { + bl2_compatible = "emmc"; + }; +}; diff --git a/arch/arm/dts/mt7986a-rfb.dts b/arch/arm/dts/mt7986a-rfb.dts new file mode 100644 index 0000000000..80def57e1a --- /dev/null +++ b/arch/arm/dts/mt7986a-rfb.dts @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7986.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "mt7986-rfb"; + compatible = "mediatek,mt7986", "mediatek,mt7986-rfb"; + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&pinctrl { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_11>; + }; + }; + + snfi_pins: snfi-pins-func-1 { + mux { + function = "flash"; + groups = "snfi"; + }; + + clk { + pins = "SPI0_CLK"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_00>; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_00>; + }; + + conf-pd { + pins = "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_00>; + }; + }; + + spic_pins: spi1-pins-func-1 { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + + uart1_pins: spi1-pins-func-3 { + mux { + function = "uart"; + groups = "uart1_2"; + }; + }; + + pwm_pins: pwm0-pins-func-1 { + mux { + function = "pwm"; + groups = "pwm0"; + }; + }; + + mmc0_pins_default: mmc0default { + mux { + function = "flash"; + groups = "emmc_51"; + }; + + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + conf-clk { + pins = "EMMC_CK"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + conf-dsl { + pins = "EMMC_DSL"; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; +}; + +&snand { + pinctrl-names = "default"; + pinctrl-0 = <&snfi_pins>; + status = "okay"; + quad-spi; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + }; + + spi_nand@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <52000000>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&watchdog { + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + bus-width = <8>; + max-frequency = <52000000>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7986a-sd-rfb.dts b/arch/arm/dts/mt7986a-sd-rfb.dts new file mode 100644 index 0000000000..5807c5d5cc --- /dev/null +++ b/arch/arm/dts/mt7986a-sd-rfb.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7986.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "mt7986-rfb"; + compatible = "mediatek,mt7986", "mediatek,mt7986-rfb", + "mediatek,mt7986-sd-rfb"; + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&pinctrl { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_11>; + }; + }; + + spic_pins: spi1-pins-func-1 { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + + uart1_pins: spi1-pins-func-3 { + mux { + function = "uart"; + groups = "uart1_2"; + }; + }; + + pwm_pins: pwm0-pins-func-1 { + mux { + function = "pwm"; + groups = "pwm0"; + }; + }; + + mmc0_pins_default: mmc0default { + mux { + function = "flash"; + groups = "emmc_51"; + }; + + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + conf-clk { + pins = "EMMC_CK"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + conf-dsl { + pins = "EMMC_DSL"; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + }; + + spi_nand@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <52000000>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&watchdog { + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + r_smpl = <1>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7986b-emmc-rfb.dts b/arch/arm/dts/mt7986b-emmc-rfb.dts new file mode 100644 index 0000000000..315bdd0b14 --- /dev/null +++ b/arch/arm/dts/mt7986b-emmc-rfb.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7986a-rfb.dts" + +/ { + compatible = "mediatek,mt7986", "mediatek,mt7986-rfb", + "mediatek,mt7986-emmc-rfb"; + bl2_verify { + bl2_compatible = "emmc"; + }; +}; diff --git a/arch/arm/dts/mt7986b-rfb.dts b/arch/arm/dts/mt7986b-rfb.dts new file mode 100644 index 0000000000..0c4e3e878f --- /dev/null +++ b/arch/arm/dts/mt7986b-rfb.dts @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7986.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "mt7986-rfb"; + compatible = "mediatek,mt7986", "mediatek,mt7986-rfb"; + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&pinctrl { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_11>; + }; + }; + + snfi_pins: snfi-pins-func-1 { + mux { + function = "flash"; + groups = "snfi"; + }; + + clk { + pins = "SPI0_CLK"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_00>; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_00>; + }; + + conf-pd { + pins = "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_00>; + }; + }; + + spic_pins: spi1-pins-func-1 { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + + uart1_pins: spi1-pins-func-3 { + mux { + function = "uart"; + groups = "uart1_2"; + }; + }; + + pwm_pins: pwm0-pins-func-1 { + mux { + function = "pwm"; + groups = "pwm0"; + }; + }; + + mmc0_pins_default: mmc0default { + mux { + function = "flash"; + groups = "emmc_45"; + input-schmitt-enable; + }; + + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI0_HOLD", "SPI0_WP", + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + conf-rst { + pins = "PWM1"; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; +}; + +&snand { + pinctrl-names = "default"; + pinctrl-0 = <&snfi_pins>; + status = "okay"; + quad-spi; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + }; + + spi_nand@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <52000000>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&watchdog { + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + bus-width = <8>; + max-frequency = <52000000>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7986b-sd-rfb.dts b/arch/arm/dts/mt7986b-sd-rfb.dts new file mode 100644 index 0000000000..48f9320e7a --- /dev/null +++ b/arch/arm/dts/mt7986b-sd-rfb.dts @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7986.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "mt7986-rfb"; + compatible = "mediatek,mt7986", "mediatek,mt7986-rfb", + "mediatek,mt7986-sd-rfb"; + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&pinctrl { + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_11>; + }; + }; + + spic_pins: spi1-pins-func-1 { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + + uart1_pins: spi1-pins-func-3 { + mux { + function = "uart"; + groups = "uart1_2"; + }; + }; + + pwm_pins: pwm0-pins-func-1 { + mux { + function = "pwm"; + groups = "pwm0"; + }; + }; + + mmc0_pins_default: mmc0default { + mux { + function = "flash"; + groups = "emmc_45"; + input-schmitt-enable; + }; + + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI0_HOLD", "SPI0_WP", + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + conf-rst { + pins = "PWM1"; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + }; + + spi_nand@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <52000000>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&watchdog { + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + r_smpl = <1>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/dts/mvebu-u-boot.dtsi b/arch/arm/dts/mvebu-u-boot.dtsi index 5538f95148..db4bf39920 100644 --- a/arch/arm/dts/mvebu-u-boot.dtsi +++ b/arch/arm/dts/mvebu-u-boot.dtsi @@ -15,6 +15,17 @@ u-boot,dm-pre-reloc; }; +#ifdef CONFIG_ARMADA_375 +/* Armada 375 has multiple timers, use timer1 here */ +&timer1 { + u-boot,dm-pre-reloc; +}; +#else +&timer { + u-boot,dm-pre-reloc; +}; +#endif + #ifdef CONFIG_SPL_SPI &spi0 { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi index 7a52ea2c4e..181732d262 100644 --- a/arch/arm/dts/qcom-ipq4019.dtsi +++ b/arch/arm/dts/qcom-ipq4019.dtsi @@ -75,9 +75,13 @@ u-boot,dm-pre-reloc; }; - pinctrl: qcom,tlmm@1000000 { - compatible = "qcom,tlmm-ipq4019"; + soc_gpios: pinctrl@1000000 { + compatible = "qcom,ipq4019-pinctrl"; reg = <0x1000000 0x300000>; + gpio-controller; + gpio-count = <100>; + gpio-bank-name="soc"; + #gpio-cells = <2>; u-boot,dm-pre-reloc; }; @@ -90,16 +94,6 @@ u-boot,dm-pre-reloc; }; - soc_gpios: pinctrl@1000000 { - compatible = "qcom,ipq4019-pinctrl"; - reg = <0x1000000 0x300000>; - gpio-controller; - gpio-count = <100>; - gpio-bank-name="soc"; - #gpio-cells = <2>; - u-boot,dm-pre-reloc; - }; - blsp1_spi1: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x78b5000 0x600>; diff --git a/arch/arm/dts/qcs404-evb-uboot.dtsi b/arch/arm/dts/qcs404-evb-uboot.dtsi index c18080a483..c73d71e8c7 100644 --- a/arch/arm/dts/qcs404-evb-uboot.dtsi +++ b/arch/arm/dts/qcs404-evb-uboot.dtsi @@ -22,3 +22,9 @@ }; }; }; + +&pms405_gpios { + usb_vbus_boost_pin { + gpios = <&pms405_gpios 2 0>; + }; +}; diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts index 4f0ae20bdb..0639af8fe3 100644 --- a/arch/arm/dts/qcs404-evb.dts +++ b/arch/arm/dts/qcs404-evb.dts @@ -38,7 +38,7 @@ compatible = "simple-bus"; pinctrl_north@1300000 { - compatible = "qcom,tlmm-qcs404"; + compatible = "qcom,qcs404-pinctrl"; reg = <0x1300000 0x200000>; blsp1_uart2: uart { @@ -52,6 +52,13 @@ reg = <0x1800000 0x80000>; #address-cells = <0x1>; #size-cells = <0x0>; + #clock-cells = <1>; + }; + + reset: gcc-reset@1800000 { + compatible = "qcom,gcc-reset-qcs404"; + reg = <0x1800000 0x80000>; + #reset-cells = <1>; }; debug_uart: serial@78b1000 { @@ -75,6 +82,117 @@ mmc-ddr-1_8v; mmc-hs400-1_8v; }; + + usb3_phy: phy@78000 { + compatible = "qcom,usb-ss-28nm-phy"; + #phy-cells = <0>; + reg = <0x78000 0x400>; + clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ahb", "pipe"; + resets = <&reset GCC_USB3_PHY_BCR>, + <&reset GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + }; + + usb2_phy_prim: phy@7a000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + #phy-cells = <0>; + reg = <0x7a000 0x200>; + clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ahb", "sleep"; + resets = <&reset GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&reset GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + }; + + usb2_phy_sec: phy@7c000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + #phy-cells = <0>; + reg = <0x7c000 0x200>; + clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ahb", "sleep"; + resets = <&reset GCC_QUSB2_PHY_BCR>, + <&reset GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", "por"; + }; + + usb3: usb@7678800 { + compatible = "qcom,dwc3"; + reg = <0x7678800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + + dwc3@7580000 { + compatible = "snps,dwc3"; + reg = <0x7580000 0xcd00>; + phys = <&usb2_phy_prim>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + }; + }; + + usb2: usb@79b8800 { + compatible = "qcom,dwc3"; + reg = <0x79b8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, + <&gcc GCC_PCNOC_USB2_CLK>, + <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + + dwc3@78c0000 { + compatible = "snps,dwc3"; + reg = <0x78c0000 0xcc00>; + phys = <&usb2_phy_sec>; + phy-names = "usb2-phy"; + dr_mode = "peripheral"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed = "high-speed"; + }; + }; + + spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x200f000 0x1000 + 0x2400000 0x400000 + 0x2c00000 0x400000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + pms405_0: pms405@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 0x1>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + pms405_gpios: pms405_gpios@c000 { + compatible = "qcom,pms405-gpio"; + reg = <0xc000 0x400>; + gpio-controller; + gpio-count = <12>; + #gpio-cells = <2>; + gpio-bank-name="pmic"; + }; + }; + }; }; }; diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index d92bdd5588..790b746ed1 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -799,18 +799,13 @@ status = "disabled"; }; - pioA: gpio@fc038000 { - compatible = "atmel,sama5d2-gpio"; + pioA: pinctrl@fc038000 { + compatible = "atmel,sama5d2-pinctrl"; reg = <0xfc038000 0x600>; clocks = <&pioA_clk>; gpio-controller; #gpio-cells = <2>; u-boot,dm-pre-reloc; - - pinctrl { - compatible = "atmel,sama5d2-pinctrl"; - u-boot,dm-pre-reloc; - }; }; }; }; diff --git a/arch/arm/dts/sama5d27_som1.dtsi b/arch/arm/dts/sama5d27_som1.dtsi index db4fefadcd..f920077449 100644 --- a/arch/arm/dts/sama5d27_som1.dtsi +++ b/arch/arm/dts/sama5d27_som1.dtsi @@ -103,54 +103,52 @@ status = "okay"; }; - pioA: gpio@fc038000 { - pinctrl { - pinctrl_i2c0_default: i2c0_default { - pinmux = <PIN_PD21__TWD0>, - <PIN_PD22__TWCK0>; - bias-disable; - }; - - pinctrl_i2c1_default: i2c1_default { - pinmux = <PIN_PD4__TWD1>, - <PIN_PD5__TWCK1>; - bias-disable; - }; - - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = <PIN_PD31__GPIO>; - bias-disable; - }; - - pinctrl_macb0_rmii: macb0_rmii { - pinmux = <PIN_PD9__GTXCK>, - <PIN_PD10__GTXEN>, - <PIN_PD11__GRXDV>, - <PIN_PD12__GRXER>, - <PIN_PD13__GRX0>, - <PIN_PD14__GRX1>, - <PIN_PD15__GTX0>, - <PIN_PD16__GTX1>, - <PIN_PD17__GMDC>, - <PIN_PD18__GMDIO>; - bias-disable; - }; - - pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default { - pinmux = <PIN_PB5__QSPI1_SCK>, - <PIN_PB6__QSPI1_CS>; - bias-disable; - u-boot,dm-pre-reloc; - }; - - pinctrl_qspi1_dat_default: qspi1_dat_default { - pinmux = <PIN_PB7__QSPI1_IO0>, - <PIN_PB8__QSPI1_IO1>, - <PIN_PB9__QSPI1_IO2>, - <PIN_PB10__QSPI1_IO3>; - bias-pull-up; - u-boot,dm-pre-reloc; - }; + pioA: pinctrl@fc038000 { + pinctrl_i2c0_default: i2c0_default { + pinmux = <PIN_PD21__TWD0>, + <PIN_PD22__TWCK0>; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PD4__TWD1>, + <PIN_PD5__TWCK1>; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PD31__GPIO>; + bias-disable; + }; + + pinctrl_macb0_rmii: macb0_rmii { + pinmux = <PIN_PD9__GTXCK>, + <PIN_PD10__GTXEN>, + <PIN_PD11__GRXDV>, + <PIN_PD12__GRXER>, + <PIN_PD13__GRX0>, + <PIN_PD14__GRX1>, + <PIN_PD15__GTX0>, + <PIN_PD16__GTX1>, + <PIN_PD17__GMDC>, + <PIN_PD18__GMDIO>; + bias-disable; + }; + + pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default { + pinmux = <PIN_PB5__QSPI1_SCK>, + <PIN_PB6__QSPI1_CS>; + bias-disable; + u-boot,dm-pre-reloc; + }; + + pinctrl_qspi1_dat_default: qspi1_dat_default { + pinmux = <PIN_PB7__QSPI1_IO0>, + <PIN_PB8__QSPI1_IO1>, + <PIN_PB9__QSPI1_IO2>, + <PIN_PB10__QSPI1_IO3>; + bias-pull-up; + u-boot,dm-pre-reloc; }; }; }; diff --git a/arch/arm/dts/sama5d27_wlsom1.dtsi b/arch/arm/dts/sama5d27_wlsom1.dtsi index 889a0034d1..1c23b8c737 100644 --- a/arch/arm/dts/sama5d27_wlsom1.dtsi +++ b/arch/arm/dts/sama5d27_wlsom1.dtsi @@ -41,36 +41,34 @@ }; }; - pioA: gpio@fc038000 { - pinctrl { - pinctrl_macb0_phy_irq: macb0_phy_irq { - pinmux = <PIN_PB24__GPIO>; - bias-disable; - }; + pioA: pinctrl@fc038000 { + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PB24__GPIO>; + bias-disable; + }; - pinctrl_macb0_rmii: macb0_rmii { - pinmux = <PIN_PB14__GTXCK>, - <PIN_PB15__GTXEN>, - <PIN_PB16__GRXDV>, - <PIN_PB17__GRXER>, - <PIN_PB18__GRX0>, - <PIN_PB19__GRX1>, - <PIN_PB20__GTX0>, - <PIN_PB21__GTX1>, - <PIN_PB22__GMDC>, - <PIN_PB23__GMDIO>; - bias-disable; - }; + pinctrl_macb0_rmii: macb0_rmii { + pinmux = <PIN_PB14__GTXCK>, + <PIN_PB15__GTXEN>, + <PIN_PB16__GRXDV>, + <PIN_PB17__GRXER>, + <PIN_PB18__GRX0>, + <PIN_PB19__GRX1>, + <PIN_PB20__GTX0>, + <PIN_PB21__GTX1>, + <PIN_PB22__GMDC>, + <PIN_PB23__GMDIO>; + bias-disable; + }; - pinctrl_qspi1_default: qspi1_default { - pinmux = <PIN_PB5__QSPI1_SCK>, - <PIN_PB6__QSPI1_CS>, - <PIN_PB7__QSPI1_IO0>, - <PIN_PB8__QSPI1_IO1>, - <PIN_PB9__QSPI1_IO2>, - <PIN_PB10__QSPI1_IO3>; - bias-pull-up; - }; + pinctrl_qspi1_default: qspi1_default { + pinmux = <PIN_PB5__QSPI1_SCK>, + <PIN_PB6__QSPI1_CS>, + <PIN_PB7__QSPI1_IO0>, + <PIN_PB8__QSPI1_IO1>, + <PIN_PB9__QSPI1_IO2>, + <PIN_PB10__QSPI1_IO3>; + bias-pull-up; }; }; }; diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi index 97400dc18e..d38090d7dd 100644 --- a/arch/arm/dts/sama7g5.dtsi +++ b/arch/arm/dts/sama7g5.dtsi @@ -187,8 +187,8 @@ reg = <0xe0008000 0x20>; }; - pinctrl: pinctrl@e0014000 { - compatible = "microchip,sama7g5-gpio"; + pioA: pinctrl@e0014000 { + compatible = "microchip,sama7g5-pinctrl"; reg = <0xe0014000 0x800>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, @@ -196,14 +196,10 @@ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; - - pioA: pinctrl_default { - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - compatible = "microchip,sama7g5-pinctrl"; - }; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; }; pmc: pmc@e0018000 { diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi index df5b6dfcfc..607af277f8 100644 --- a/arch/arm/dts/sdm845.dtsi +++ b/arch/arm/dts/sdm845.dtsi @@ -37,7 +37,7 @@ }; tlmm_north: pinctrl_north@3900000 { - compatible = "qcom,tlmm-sdm845"; + compatible = "qcom,sdm845-pinctrl"; reg = <0x3900000 0x400000>; gpio-count = <150>; gpio-controller; diff --git a/arch/arm/dts/stm32429i-eval-u-boot.dtsi b/arch/arm/dts/stm32429i-eval-u-boot.dtsi index fcab9ae977..030da47b7a 100644 --- a/arch/arm/dts/stm32429i-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32429i-eval-u-boot.dtsi @@ -218,6 +218,6 @@ }; }; -&timer5 { +&timers5 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32746g-eval.dts b/arch/arm/dts/stm32746g-eval.dts index 9940cf1873..0e6445a539 100644 --- a/arch/arm/dts/stm32746g-eval.dts +++ b/arch/arm/dts/stm32746g-eval.dts @@ -45,12 +45,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "Wake up"; linux,code = <KEY_WAKEUP>; gpios = <&gpioc 13 0>; @@ -160,6 +158,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32f4-pinctrl.dtsi b/arch/arm/dts/stm32f4-pinctrl.dtsi index adf502694b..46815c965d 100644 --- a/arch/arm/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/dts/stm32f4-pinctrl.dtsi @@ -9,7 +9,7 @@ / { soc { - pinctrl: pin-controller { + pinctrl: pinctrl@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/dts/stm32f429-disco-u-boot.dtsi b/arch/arm/dts/stm32f429-disco-u-boot.dtsi index c993f86be8..45f899662d 100644 --- a/arch/arm/dts/stm32f429-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f429-disco-u-boot.dtsi @@ -27,10 +27,6 @@ soc { u-boot,dm-pre-reloc; - pin-controller { - u-boot,dm-pre-reloc; - }; - fmc: fmc@A0000000 { compatible = "st,stm32-fmc"; reg = <0xa0000000 0x1000>; @@ -123,6 +119,8 @@ }; &pinctrl { + u-boot,dm-pre-reloc; + usart1_pins_a: usart1-0 { u-boot,dm-pre-reloc; pins1 { @@ -193,6 +191,6 @@ u-boot,dm-pre-reloc; }; -&timer5 { +&timers5 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32f429-disco.dts b/arch/arm/dts/stm32f429-disco.dts index 42477c8d3f..30daabd10a 100644 --- a/arch/arm/dts/stm32f429-disco.dts +++ b/arch/arm/dts/stm32f429-disco.dts @@ -39,12 +39,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "User"; linux,code = <KEY_HOME>; gpios = <&gpioa 0 0>; @@ -152,7 +150,7 @@ display: display@1{ /* Connect panel-ilitek-9341 to ltdc */ - compatible = "st,sf-tc240t-9370-t"; + compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341"; reg = <1>; spi-3wire; spi-max-frequency = <10000000>; @@ -165,6 +163,18 @@ }; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32f429-pinctrl.dtsi b/arch/arm/dts/stm32f429-pinctrl.dtsi index 575c7eecab..5be171eea5 100644 --- a/arch/arm/dts/stm32f429-pinctrl.dtsi +++ b/arch/arm/dts/stm32f429-pinctrl.dtsi @@ -6,54 +6,50 @@ #include "stm32f4-pinctrl.dtsi" -/ { - soc { - pinctrl: pin-controller { - compatible = "st,stm32f429-pinctrl"; - - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 16>; - }; - - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 0 160 8>; - }; - }; +&pinctrl { + compatible = "st,stm32f429-pinctrl"; + + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 0 160 8>; }; }; diff --git a/arch/arm/dts/stm32f429.dtsi b/arch/arm/dts/stm32f429.dtsi index a81e916064..e5b13aca40 100644 --- a/arch/arm/dts/stm32f429.dtsi +++ b/arch/arm/dts/stm32f429.dtsi @@ -52,14 +52,6 @@ }; }; - timer2: timer@40000000 { - compatible = "st,stm32-timer"; - reg = <0x40000000 0x400>; - interrupts = <28>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; - status = "disabled"; - }; - timers2: timers@40000000 { #address-cells = <1>; #size-cells = <0>; @@ -82,14 +74,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -112,14 +96,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -142,13 +118,6 @@ }; }; - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; - }; - timers5: timers@40000c00 { #address-cells = <1>; #size-cells = <0>; @@ -171,14 +140,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -195,14 +156,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; @@ -242,8 +195,6 @@ }; timers13: timers@40001c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40001C00 0x400>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; @@ -258,8 +209,6 @@ }; timers14: timers@40002000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40002000 0x400>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; @@ -525,7 +474,7 @@ }; }; - sdio: sdio@40012c00 { + sdio: mmc@40012c00 { compatible = "arm,pl180", "arm,primecell"; arm,primecell-periphid = <0x00880180>; reg = <0x40012c00 0x400>; @@ -592,8 +541,6 @@ }; timers10: timers@40014400 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014400 0x400>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; @@ -608,8 +555,6 @@ }; timers11: timers@40014800 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014800 0x400>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; @@ -668,7 +613,7 @@ status = "disabled"; }; - rcc: rcc@40023810 { + rcc: rcc@40023800 { #reset-cells = <1>; #clock-cells = <2>; compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; @@ -726,6 +671,16 @@ status = "disabled"; }; + dma2d: dma2d@4002b000 { + compatible = "st,stm32-dma2d"; + reg = <0x4002b000 0xc00>; + interrupts = <90>; + resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>; + clock-names = "dma2d"; + status = "disabled"; + }; + usbotg_hs: usb@40040000 { compatible = "snps,dwc2"; reg = <0x40040000 0x40000>; diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi index cd173623ef..ee0c82b53e 100644 --- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi @@ -28,9 +28,6 @@ soc { u-boot,dm-pre-reloc; - pin-controller { - u-boot,dm-pre-reloc; - }; fmc: fmc@A0000000 { compatible = "st,stm32-fmc"; @@ -138,6 +135,8 @@ }; &pinctrl { + u-boot,dm-pre-reloc; + fmc_pins_d32: fmc_d32@0 { u-boot,dm-pre-reloc; pins @@ -256,6 +255,6 @@ u-boot,dm-pre-reloc; }; -&timer5 { +&timers5 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32f469-disco.dts b/arch/arm/dts/stm32f469-disco.dts index 23d87ee27a..6e0ffc1903 100644 --- a/arch/arm/dts/stm32f469-disco.dts +++ b/arch/arm/dts/stm32f469-disco.dts @@ -19,7 +19,7 @@ stdout-path = "serial0:115200n8"; }; - memory@00000000 { + memory@0 { device_type = "memory"; reg = <0x00000000 0x1000000>; }; @@ -63,12 +63,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "User"; linux,code = <KEY_WAKEUP>; gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; @@ -93,6 +91,10 @@ clock-frequency = <8000000>; }; +&dma2d { + status = "okay"; +}; + &dsi { #address-cells = <1>; #size-cells = <0>; @@ -185,6 +187,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart3 { pinctrl-0 = <&usart3_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32f469-pinctrl.dtsi b/arch/arm/dts/stm32f469-pinctrl.dtsi index 1e2bb0191e..0610407c7b 100644 --- a/arch/arm/dts/stm32f469-pinctrl.dtsi +++ b/arch/arm/dts/stm32f469-pinctrl.dtsi @@ -5,55 +5,51 @@ #include "stm32f4-pinctrl.dtsi" -/ { - soc { - pinctrl: pin-controller { - compatible = "st,stm32f469-pinctrl"; - - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 6>, - <&pinctrl 12 156 4>; - }; - - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 3 163 5>; - }; - }; +&pinctrl { + compatible = "st,stm32f469-pinctrl"; + + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 6>, + <&pinctrl 12 156 4>; + }; + + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 3 163 5>; }; }; diff --git a/arch/arm/dts/stm32f7-pinctrl.dtsi b/arch/arm/dts/stm32f7-pinctrl.dtsi index fe4cfda72a..8f37aefa73 100644 --- a/arch/arm/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/dts/stm32f7-pinctrl.dtsi @@ -9,7 +9,7 @@ / { soc { - pinctrl: pin-controller { + pinctrl: pinctrl@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index c1b2ac25c3..0ba8031c33 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -119,7 +119,7 @@ u-boot,dm-pre-reloc; }; -&timer5 { +&timers5 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index 9430dc08ec..1ed58f2361 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -73,6 +73,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_b>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 78facde2b5..c97b3d0d07 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -39,14 +39,6 @@ }; soc { - timer2: timer@40000000 { - compatible = "st,stm32-timer"; - reg = <0x40000000 0x400>; - interrupts = <28>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; - status = "disabled"; - }; - timers2: timers@40000000 { #address-cells = <1>; #size-cells = <0>; @@ -69,14 +61,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -99,14 +83,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -129,13 +105,6 @@ }; }; - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; - }; - timers5: timers@40000c00 { #address-cells = <1>; #size-cells = <0>; @@ -158,14 +127,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -182,14 +143,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; @@ -229,8 +182,6 @@ }; timers13: timers@40001c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40001C00 0x400>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; @@ -245,8 +196,6 @@ }; timers14: timers@40002000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40002000 0x400>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; @@ -313,7 +262,6 @@ clocks = <&rcc 1 CLK_I2C1>; #address-cells = <1>; #size-cells = <0>; - i2c-analog-filter; status = "disabled"; }; @@ -326,20 +274,18 @@ clocks = <&rcc 1 CLK_I2C2>; #address-cells = <1>; #size-cells = <0>; - i2c-analog-filter; status = "disabled"; }; - i2c3: i2c@40005C00 { + i2c3: i2c@40005c00 { compatible = "st,stm32f7-i2c"; - reg = <0x40005C00 0x400>; + reg = <0x40005c00 0x400>; interrupts = <72>, <73>; resets = <&rcc STM32F7_APB1_RESET(I2C3)>; clocks = <&rcc 1 CLK_I2C3>; #address-cells = <1>; #size-cells = <0>; - i2c-analog-filter; status = "disabled"; }; @@ -352,7 +298,6 @@ clocks = <&rcc 1 CLK_I2C4>; #address-cells = <1>; #size-cells = <0>; - i2c-analog-filter; status = "disabled"; }; @@ -441,7 +386,7 @@ status = "disabled"; }; - sdio2: sdio2@40011c00 { + sdio2: mmc@40011c00 { compatible = "arm,pl180", "arm,primecell"; arm,primecell-periphid = <0x00880180>; reg = <0x40011c00 0x400>; @@ -452,7 +397,7 @@ status = "disabled"; }; - sdio1: sdio1@40012c00 { + sdio1: mmc@40012c00 { compatible = "arm,pl180", "arm,primecell"; arm,primecell-periphid = <0x00880180>; reg = <0x40012c00 0x400>; @@ -499,8 +444,6 @@ }; timers10: timers@40014400 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014400 0x400>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; @@ -515,8 +458,6 @@ }; timers11: timers@40014800 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014800 0x400>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts index 03cfbd7cc2..6f93fc7bcf 100644 --- a/arch/arm/dts/stm32f769-disco.dts +++ b/arch/arm/dts/stm32f769-disco.dts @@ -39,12 +39,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "User"; linux,code = <KEY_HOME>; gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; @@ -103,6 +101,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index dbfebf07f2..ceb629c4fa 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -124,7 +124,6 @@ <32>; resets = <&rcc STM32H7_APB1L_RESET(I2C1)>; clocks = <&rcc I2C1_CK>; - i2c-analog-filter; status = "disabled"; }; @@ -137,7 +136,6 @@ <34>; resets = <&rcc STM32H7_APB1L_RESET(I2C2)>; clocks = <&rcc I2C2_CK>; - i2c-analog-filter; status = "disabled"; }; @@ -150,7 +148,6 @@ <73>; resets = <&rcc STM32H7_APB1L_RESET(I2C3)>; clocks = <&rcc I2C3_CK>; - i2c-analog-filter; status = "disabled"; }; @@ -337,12 +334,12 @@ dma-requests = <32>; }; - sdmmc1: sdmmc@52007000 { + sdmmc1: mmc@52007000 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x10153180>; reg = <0x52007000 0x1000>; interrupts = <49>; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; @@ -351,18 +348,19 @@ max-frequency = <120000000>; }; - sdmmc2: sdmmc@48022400 { + sdmmc2: mmc@48022400 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x10153180>; reg = <0x48022400 0x400>; interrupts = <124>; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC2_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; + status = "disabled"; }; exti: interrupt-controller@58000000 { @@ -398,7 +396,6 @@ <96>; resets = <&rcc STM32H7_APB4_RESET(I2C4)>; clocks = <&rcc I2C4_CK>; - i2c-analog-filter; status = "disabled"; }; @@ -452,8 +449,6 @@ }; lptimer4: timer@58002c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58002c00 0x400>; clocks = <&rcc LPTIM4_CK>; @@ -468,8 +463,6 @@ }; lptimer5: timer@58003000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58003000 0x400>; clocks = <&rcc LPTIM5_CK>; @@ -554,7 +547,7 @@ status = "disabled"; }; - pinctrl: pin-controller@58020000 { + pinctrl: pinctrl@58020000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32h743-pinctrl"; diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts index 3a01ebd563..b31188f8b9 100644 --- a/arch/arm/dts/stm32h743i-disco.dts +++ b/arch/arm/dts/stm32h743i-disco.dts @@ -41,10 +41,10 @@ &mac { status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; mdio0 { #address-cells = <1>; diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts index 38cc7faf68..5c5d8059bd 100644 --- a/arch/arm/dts/stm32h743i-eval.dts +++ b/arch/arm/dts/stm32h743i-eval.dts @@ -115,10 +115,10 @@ &mac { status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; mdio0 { #address-cells = <1>; diff --git a/arch/arm/dts/stm32h750i-art-pi.dts b/arch/arm/dts/stm32h750i-art-pi.dts index 2a4d1cb496..c7c7132f22 100644 --- a/arch/arm/dts/stm32h750i-art-pi.dts +++ b/arch/arm/dts/stm32h750i-art-pi.dts @@ -87,10 +87,10 @@ &mac { status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; mdio0 { #address-cells = <1>; diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi index 01552adb7c..47a43649bb 100644 --- a/arch/arm/dts/stm32mp13-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi @@ -17,6 +17,12 @@ pinctrl0 = &pinctrl; }; + firmware { + optee { + u-boot,dm-pre-reloc; + }; + }; + /* need PSCI for sysreset during board_f */ psci { u-boot,dm-pre-proper; @@ -82,10 +88,6 @@ u-boot,dm-pre-reloc; }; -&optee { - u-boot,dm-pre-reloc; -}; - &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index 84e16bb2f2..a1c6d0d00b 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -27,21 +27,8 @@ interrupt-parent = <&intc>; }; - scmi_sram: sram@2ffff000 { - compatible = "mmio-sram"; - reg = <0x2ffff000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2ffff000 0x1000>; - - scmi_shm: scmi_shm@0 { - compatible = "arm,scmi-shmem"; - reg = <0 0x80>; - }; - }; - firmware { - optee: optee { + optee { method = "smc"; compatible = "linaro,optee-tz"; }; @@ -151,6 +138,19 @@ interrupt-parent = <&intc>; ranges; + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm: scmi-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + }; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index f436ffab99..e6b8ffd332 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -31,8 +31,8 @@ #size-cells = <1>; ranges; - optee@de000000 { - reg = <0xde000000 0x2000000>; + optee@dd000000 { + reg = <0xdd000000 0x3000000>; no-map; }; }; diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi index 0aac9131a6..d02f79dac6 100644 --- a/arch/arm/dts/stm32mp15-ddr.dtsi +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -4,7 +4,22 @@ */ #include <linux/stringify.h> +#ifdef CONFIG_SPL &ddr { + clocks = <&rcc AXIDCG>, + <&rcc DDRC1>, + <&rcc DDRC2>, + <&rcc DDRPHYC>, + <&rcc DDRCAPB>, + <&rcc DDRPHYCAPB>; + + clock-names = "axidcg", + "ddrc1", + "ddrc2", + "ddrphyc", + "ddrcapb", + "ddrphycapb"; + config-DDR_MEM_COMPATIBLE { u-boot,dm-pre-reloc; @@ -119,6 +134,7 @@ status = "okay"; }; }; +#endif #undef DDR_MEM_COMPATIBLE #undef DDR_MEM_NAME diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index d3ed10335d..2cc9341d43 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -151,6 +151,43 @@ }; }; + dcmi_pins_c: dcmi-2 { + pins { + pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ + <STM32_PINMUX('E', 0, AF13)>,/* DCMI_D2 */ + <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ + <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ + <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ + <STM32_PINMUX('I', 6, AF13)>,/* DCMI_D6 */ + <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ + <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ + <STM32_PINMUX('H', 7, AF13)>;/* DCMI_D9 */ + bias-pull-up; + }; + }; + + dcmi_sleep_pins_c: dcmi-sleep-2 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ + <STM32_PINMUX('E', 0, ANALOG)>,/* DCMI_D2 */ + <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ + <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ + <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ + <STM32_PINMUX('I', 6, ANALOG)>,/* DCMI_D6 */ + <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ + <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ + <STM32_PINMUX('H', 7, ANALOG)>;/* DCMI_D9 */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ @@ -923,6 +960,21 @@ }; }; + mco1_pins_a: mco1-0 { + pins { + pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + mco1_sleep_pins_a: mco1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */ + }; + }; + mco2_pins_a: mco2-0 { pins { pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */ @@ -1814,30 +1866,30 @@ spi2_pins_a: spi2-0 { pins1 { - pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */ - <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */ + pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */ + <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { - pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */ + pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ bias-disable; }; }; spi2_pins_b: spi2-1 { pins1 { - pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI1_SCK */ - <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */ + pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */ + <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { - pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */ + pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ bias-disable; }; }; diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index d9d04743ac..d5c87d29d8 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -53,20 +53,6 @@ reg = <0x5a003000 0x550 0x5a004000 0x234>; - clocks = <&rcc AXIDCG>, - <&rcc DDRC1>, - <&rcc DDRC2>, - <&rcc DDRPHYC>, - <&rcc DDRCAPB>, - <&rcc DDRPHYCAPB>; - - clock-names = "axidcg", - "ddrc1", - "ddrc2", - "ddrphyc", - "ddrcapb", - "ddrphycapb"; - status = "okay"; }; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 767a06ef68..f0fb022fc6 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -1143,10 +1143,9 @@ reg = <0x4c001000 0x400>; st,proc-id = <0>; interrupts-extended = - <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <&exti 61 1>; - interrupt-names = "rx", "tx", "wakeup"; + <&exti 61 1>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; clocks = <&rcc IPCC>; wakeup-source; status = "disabled"; diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi index 2db045e7ce..1209dfe009 100644 --- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi @@ -5,7 +5,6 @@ #include <dt-bindings/clock/stm32mp1-clksrc.h> #include "stm32mp15-scmi-u-boot.dtsi" -#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" / { aliases { diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi index 54662f7e29..c265745ff1 100644 --- a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi @@ -5,7 +5,6 @@ #include <dt-bindings/clock/stm32mp1-clksrc.h> #include "stm32mp15-scmi-u-boot.dtsi" -#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" / { aliases { diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 3d36cac9ed..5a045d7156 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -685,6 +685,14 @@ &usbh_ehci { phys = <&usbphyc_port0>; status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&v3v3>; + }; }; &usbotg_hs { diff --git a/arch/arm/dts/total_compute.dts b/arch/arm/dts/total_compute.dts index 4399269a44..96edacda0b 100644 --- a/arch/arm/dts/total_compute.dts +++ b/arch/arm/dts/total_compute.dts @@ -45,4 +45,8 @@ clock-frequency = <24000000>; clock-output-names = "bp:clock24mhz"; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; }; diff --git a/arch/arm/dts/versal-net-mini.dts b/arch/arm/dts/versal-net-mini.dts new file mode 100644 index 0000000000..8c29a6ed6b --- /dev/null +++ b/arch/arm/dts/versal-net-mini.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal NET + * + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "xlnx,versal-net-mini"; + model = "Xilinx Versal NET MINI"; + #address-cells = <2>; + #size-cells = <2>; + + memory: memory@0 { + reg = <0 0xBBF00000 0 0x100000>, <0 0 0 0x80000000>; + device_type = "memory"; + }; + + aliases { + /* serial0 = &serial0; */ + serial0 = &dcc; + }; + + chosen { + stdout-path = "serial0:115200"; + }; + + clk1: clk1 { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + amba: axi { + compatible = "simple-bus"; + u-boot,dm-pre-reloc; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + serial0: serial@f1920000 { + u-boot,dm-pre-reloc; + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0xf1920000 0 0x1000>; + reg-io-width = <4>; + clock-names = "uartclk", "apb_pclk"; + clocks = <&clk1>, <&clk1>; + clock = <1000000>; + current-speed = <115200>; + skip-init; + }; + }; +}; diff --git a/arch/arm/dts/xilinx-versal-net-virt.dts b/arch/arm/dts/xilinx-versal-net-virt.dts new file mode 100644 index 0000000000..c99257cb08 --- /dev/null +++ b/arch/arm/dts/xilinx-versal-net-virt.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Empty device tree for versal-net-virt board + * + * Copyright (C) 2022, Advanced Micro Devices, Inc. + */ + +/dts-v1/; + +/ { +}; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 37155df0fd..edc147d63f 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -192,6 +192,17 @@ reg = <0xf8006000 0x1000>; }; + ocm: sram@fffc0000 { + compatible = "mmio-sram"; + reg = <0xfffc0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffc0000 0x10000>; + ocm-sram@0 { + reg = <0x0 0x10000>; + }; + }; + uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; @@ -235,19 +246,19 @@ }; qspi: spi@e000d000 { - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; - status = "disabled"; + reg = <0xe000d000 0x1000>; interrupt-parent = <&intc>; interrupts = <0 19 4>; - reg = <0xe000d000 0x1000>; + clocks = <&clkc 10>, <&clkc 43>; + clock-names = "ref_clk", "pclk"; + status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; gem0: ethernet@e000b000 { - compatible = "cdns,zynq-gem", "cdns,gem"; + compatible = "xlnx,zynq-gem", "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; @@ -258,7 +269,7 @@ }; gem1: ethernet@e000c000 { - compatible = "cdns,zynq-gem", "cdns,gem"; + compatible = "xlnx,zynq-gem", "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; @@ -378,9 +389,9 @@ devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; + reg = <0xf8007000 0x100>; interrupt-parent = <&intc>; interrupts = <0 8 4>; - reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; @@ -416,6 +427,7 @@ }; scutimer: timer@f8f00600 { + u-boot,dm-pre-reloc; interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index f2e05a55b9..1bd4f8c9f6 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -64,19 +64,6 @@ }; }; -&amba { - ocm: sram@fffc0000 { - compatible = "mmio-sram"; - reg = <0xfffc0000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xfffc0000 0x10000>; - ocm-sram@0 { - reg = <0x0 0x10000>; - }; - }; -}; - &can0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 7b09d75151..b99eb07b00 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -260,11 +260,19 @@ assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; +&dwc3_0 { + clocks = <&zynqmp_clk USB3_DUAL_REF>; +}; + &usb1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; +&dwc3_1 { + clocks = <&zynqmp_clk USB3_DUAL_REF>; +}; + &watchdog0 { clocks = <&zynqmp_clk WDT>; }; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 37c56181c9..3fa18f560c 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -155,8 +155,12 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; - phy0: ethernet-phy@0 { /* u131 M88E1512 */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { /* u131 M88E1512 */ + reg = <0>; + }; }; }; @@ -203,6 +207,18 @@ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; + + tca6416_u233: gpio@20 { /* u233 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ + "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULLSPD", /* 4 - 7 */ + "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 10 - 13 */ + "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ + }; + i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index ac349a9dcc..bae24aabdb 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -214,13 +214,17 @@ }; partition@2240000 { label = "SHA256"; - reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ + reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ read-only; lock; }; - partition@2250000 { + partition@2280000 { + label = "Secure OS Storage"; + reg = <0x2280000 0x20000>; /* 128KB */ + }; + partition@22A0000 { label = "User"; - reg = <0x2250000 0x1db0000>; /* 29.5 MB */ + reg = <0x22A0000 0x1db0000>; /* 29.5 MB */ }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index a4e92c8bb1..9d8e551ed2 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -200,13 +200,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@21 { - reg = <21>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@21 { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <21>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 1418cffb20..b9d82afc51 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -109,12 +109,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 7fd19ca3a8..6f24e335a1 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -114,12 +114,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index e412992ff1..2e95f22c3f 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -172,12 +172,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index c5cdd58af6..7e7e1577eb 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -169,12 +169,19 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index caae16965d..35a30971cb 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -176,15 +176,21 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; + }; }; }; - &gpio { status = "okay"; gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index fbc6e752da..f4184f79a5 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -529,7 +529,7 @@ }; gem0: ethernet@ff0b0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; + compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; @@ -543,7 +543,7 @@ }; gem1: ethernet@ff0c0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; + compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; @@ -557,7 +557,7 @@ }; gem2: ethernet@ff0d0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; + compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; @@ -571,7 +571,7 @@ }; gem3: ethernet@ff0e0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; + compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; @@ -869,6 +869,7 @@ iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; + clock-names = "ref"; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; @@ -900,6 +901,7 @@ iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; + clock-names = "ref"; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h index 3451e74a3d..57db839e8d 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -10,9 +10,9 @@ #include <asm/arch-stm32/stm32f.h> static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { - [0 ... 3] = 32 * 1024, - [4] = 128 * 1024, - [5 ... 7] = 256 * 1024 + [0 ... 3] = 32 * 1024, + [4] = 128 * 1024, + [5 ... CONFIG_SYS_MAX_FLASH_SECT - 1] = 256 * 1024 }; #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index b146918586..8d42ef4823 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -58,16 +58,22 @@ #endif /* - * We only support cores that support at least Thumb-1 and thus we use - * 'bx lr' + * Use 'bx lr' everywhere except ARMv4 (without 'T') where only 'mov pc, lr' + * works */ .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo .macro ret\c, reg + + /* ARMv4- don't know bx lr but the assembler fails to see that */ +#ifdef __ARM_ARCH_4__ + mov\c pc, \reg +#else .ifeqs "\reg", "lr" bx\c \reg .else mov\c pc, \reg .endif +#endif .endm .endr diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 6ee2a76761..cd6112dfcd 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -101,7 +101,7 @@ struct arch_global_data { #include <asm-generic/global_data.h> -#if defined(__clang__) || defined(CONFIG_LTO) +#if defined(__clang__) || defined(LTO_ENABLE) #define DECLARE_GLOBAL_DATA_PTR #define gd get_gd() diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index c603fe61bc..62cf80f373 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -33,10 +33,12 @@ obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o -obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o else obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o -obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o +ifdef CONFIG_SPL_FRAMEWORK +obj-$(CONFIG_CMD_BOOTI) += image.o +obj-$(CONFIG_CMD_BOOTZ) += zimage.o +endif obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o endif ifdef CONFIG_ARM64 @@ -46,6 +48,7 @@ else obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o endif +obj-$(CONFIG_$(SPL_TPL_)SYS_L2_PL310) += cache-pl310.o obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o ifneq ($(filter y,$(CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR) $(CONFIG_SAVE_PREV_BL_FDT_ADDR)),) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 9f086f3b90..e414ef8267 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -192,10 +192,10 @@ static void do_nonsec_virt_switch(void) } #endif -__weak void board_prep_linux(bootm_headers_t *images) { } +__weak void board_prep_linux(struct bootm_headers *images) { } /* Subcommand: PREP */ -static void boot_prep_linux(bootm_headers_t *images) +static void boot_prep_linux(struct bootm_headers *images) { char *commandline = env_get("bootargs"); @@ -288,7 +288,7 @@ static void switch_to_el1(void) #endif /* Subcommand: GO */ -static void boot_jump_linux(bootm_headers_t *images, int flag) +static void boot_jump_linux(struct bootm_headers *images, int flag) { #ifdef CONFIG_ARM64 void (*kernel_entry)(void *fdt_addr, void *res0, void *res1, @@ -379,7 +379,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) * they are called if subcommand is equal 0. */ int do_bootm_linux(int flag, int argc, char *const argv[], - bootm_headers_t *images) + struct bootm_headers *images) { /* No need for those on ARM */ if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE) @@ -401,7 +401,7 @@ int do_bootm_linux(int flag, int argc, char *const argv[], } #if defined(CONFIG_BOOTM_VXWORKS) -void boot_prep_vxworks(bootm_headers_t *images) +void boot_prep_vxworks(struct bootm_headers *images) { #if defined(CONFIG_OF_LIBFDT) int off; @@ -416,7 +416,8 @@ void boot_prep_vxworks(bootm_headers_t *images) #endif cleanup_before_linux(); } -void boot_jump_vxworks(bootm_headers_t *images) + +void boot_jump_vxworks(struct bootm_headers *images) { #if defined(CONFIG_ARM64) && defined(CONFIG_ARMV8_PSCI) armv8_setup_psci(); diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S index 700eee5fbb..7ff4446dd6 100644 --- a/arch/arm/lib/lib1funcs.S +++ b/arch/arm/lib/lib1funcs.S @@ -377,7 +377,7 @@ ENTRY(__gnu_thumb1_case_sqi) lsls r1, r1, #1 add lr, lr, r1 pop {r1} - bx lr + ret lr ENDPROC(__gnu_thumb1_case_sqi) .popsection @@ -391,7 +391,7 @@ ENTRY(__gnu_thumb1_case_uqi) lsls r1, r1, #1 add lr, lr, r1 pop {r1} - bx lr + ret lr ENDPROC(__gnu_thumb1_case_uqi) .popsection @@ -406,7 +406,7 @@ ENTRY(__gnu_thumb1_case_shi) lsls r1, r1, #1 add lr, lr, r1 pop {r0, r1} - bx lr + ret lr ENDPROC(__gnu_thumb1_case_shi) .popsection @@ -421,7 +421,7 @@ ENTRY(__gnu_thumb1_case_uhi) lsls r1, r1, #1 add lr, lr, r1 pop {r0, r1} - bx lr + ret lr ENDPROC(__gnu_thumb1_case_uhi) .popsection #endif diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S index eee7a219ce..a1c996f94e 100644 --- a/arch/arm/lib/memcpy.S +++ b/arch/arm/lib/memcpy.S @@ -59,7 +59,7 @@ #endif ENTRY(memcpy) cmp r0, r1 - bxeq lr + reteq lr enter r4, lr @@ -148,7 +148,7 @@ ENTRY(memcpy) str1b r0, ip, cs, abort=21f exit r4, lr - bx lr + ret lr 9: rsb ip, ip, #4 cmp ip, #2 @@ -258,7 +258,7 @@ ENTRY(memcpy) .macro copy_abort_end ldmfd sp!, {r4, lr} - bx lr + ret lr .endm ENDPROC(memcpy) diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index 5102bfabde..dd6f2e3bd5 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -61,7 +61,7 @@ ENTRY(relocate_vectors) stmia r1!, {r2-r8,r10} #endif #endif - bx lr + ret lr ENDPROC(relocate_vectors) @@ -127,13 +127,7 @@ relocate_done: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ #endif - /* ARMv4- don't know bx lr but the assembler fails to see that */ - -#ifdef __ARM_ARCH_4__ - mov pc, lr -#else - bx lr -#endif + ret lr ENDPROC(relocate_code) diff --git a/arch/arm/lib/setjmp.S b/arch/arm/lib/setjmp.S index 176a1d5315..2f041aeef0 100644 --- a/arch/arm/lib/setjmp.S +++ b/arch/arm/lib/setjmp.S @@ -17,7 +17,7 @@ ENTRY(setjmp) mov ip, sp stm a1, {v1-v8, ip, lr} mov a1, #0 - bx lr + ret lr ENDPROC(setjmp) .popsection @@ -31,6 +31,6 @@ ENTRY(longjmp) bne 1f mov a1, #1 1: - bx lr + ret lr ENDPROC(longjmp) .popsection diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c index 53c8a15bf9..0952e73a45 100644 --- a/arch/arm/mach-aspeed/ast2600/spl.c +++ b/arch/arm/mach-aspeed/ast2600/spl.c @@ -56,9 +56,9 @@ out: return BOOT_DEVICE_RAM; } -struct image_header *spl_get_load_buffer(ssize_t offset, size_t size) +struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) { - return (struct image_header *)(CONFIG_SYS_LOAD_ADDR); + return (struct legacy_img_hdr *)(CONFIG_SYS_LOAD_ADDR); } #ifdef CONFIG_SPL_OS_BOOT diff --git a/arch/arm/mach-at91/phy.c b/arch/arm/mach-at91/phy.c index 6101eee358..f4484a77c7 100644 --- a/arch/arm/mach-at91/phy.c +++ b/arch/arm/mach-at91/phy.c @@ -42,7 +42,7 @@ void at91_phy_reset(void) /* Wait for end of hardware reset */ while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { /* avoid shutdown by watchdog */ - WATCHDOG_RESET(); + schedule(); mdelay(10); /* timeout for not getting stuck in an endless loop */ diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 0d1a7766be..c6747b257c 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -589,7 +589,7 @@ static ulong get_image_ivt_offset(ulong img_addr) switch (genimg_get_format(buf)) { #if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: - return (image_get_image_size((image_header_t *)img_addr) + return (image_get_image_size((struct legacy_img_hdr *)img_addr) + 0x1000 - 1) & ~(0x1000 - 1); #endif #if CONFIG_IS_ENABLED(FIT) diff --git a/arch/arm/mach-imx/i2c-mxv7.c b/arch/arm/mach-imx/i2c-mxv7.c index d36347d8e8..85d648b56e 100644 --- a/arch/arm/mach-imx/i2c-mxv7.c +++ b/arch/arm/mach-imx/i2c-mxv7.c @@ -46,7 +46,7 @@ int force_idle_bus(void *priv) scl = gpio_get_value(p->scl.gp); if ((sda & scl) == 1) break; - WATCHDOG_RESET(); + schedule(); elapsed = get_timer(start_time); if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */ ret = -EBUSY; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 5739546c02..a4863281e3 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -327,7 +327,7 @@ phys_size_t get_effective_memsize(void) } } -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { ulong top_addr; diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index 07bf07beee..aa5d23a6fb 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -72,7 +72,7 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image, int ret; u32 offset; u32 pagesize, size; - struct image_header *header; + struct legacy_img_hdr *header; u32 image_offset; ret = rom_api_query_boot_infor(QUERY_IVT_OFF, &offset); @@ -84,14 +84,14 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image, return -1; } - header = (struct image_header *)(CONFIG_SPL_IMX_ROMAPI_LOADADDR); + header = (struct legacy_img_hdr *)(CONFIG_SPL_IMX_ROMAPI_LOADADDR); printf("image offset 0x%x, pagesize 0x%x, ivt offset 0x%x\n", image_offset, pagesize, offset); offset = spl_romapi_get_uboot_base(image_offset, rom_bt_dev); - size = ALIGN(sizeof(struct image_header), pagesize); + size = ALIGN(sizeof(struct legacy_img_hdr), pagesize); ret = rom_api_download_image((u8 *)header, offset, size); if (ret != ROM_API_OKAY) { diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c index c51a75ee94..036fec93d7 100644 --- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c +++ b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c @@ -14,6 +14,8 @@ #include <dm.h> #include <errno.h> #include <asm/io.h> +#include <dm/device_compat.h> +#include <dm/lists.h> #include <dm/pinctrl.h> #include <linux/bitops.h> #include "pinctrl-snapdragon.h" @@ -110,6 +112,32 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, return 0; } +static int msm_pinctrl_bind(struct udevice *dev) +{ + ofnode node = dev_ofnode(dev); + const char *name; + int ret; + + ofnode_get_property(node, "gpio-controller", &ret); + if (ret < 0) + return 0; + + /* Get the name of gpio node */ + name = ofnode_get_name(node); + if (!name) + return -EINVAL; + + /* Bind gpio node */ + ret = device_bind_driver_to_node(dev, "gpio_msm", + name, node, NULL); + if (ret) + return ret; + + dev_dbg(dev, "bind %s\n", name); + + return 0; +} + static struct pinctrl_ops msm_pinctrl_ops = { .get_pins_count = msm_get_pins_count, .get_pin_name = msm_get_pin_name, @@ -123,7 +151,7 @@ static struct pinctrl_ops msm_pinctrl_ops = { }; static const struct udevice_id msm_pinctrl_ids[] = { - { .compatible = "qcom,tlmm-ipq4019", .data = (ulong)&ipq4019_data }, + { .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data }, { } }; @@ -134,4 +162,5 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = { .priv_auto = sizeof(struct msm_pinctrl_priv), .ops = &msm_pinctrl_ops, .probe = msm_pinctrl_probe, + .bind = msm_pinctrl_bind, }; diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 3962f2800f..14c37acbce 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -493,7 +493,7 @@ bool soc_is_j7200(void) } #ifdef CONFIG_ARM64 -void board_prep_linux(bootm_headers_t *images) +void board_prep_linux(struct bootm_headers *images) { debug("Linux kernel Image start = 0x%lx end = 0x%lx\n", images->os.start, images->os.end); diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index b3beeca947..aea640b570 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -88,10 +88,10 @@ static void *sysfw_load_address; * Populate SPL hook to override the default load address used by the SPL * loader function with a custom address for SYSFW loading. */ -struct image_header *spl_get_load_buffer(ssize_t offset, size_t size) +struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) { if (sysfw_loaded) - return (struct image_header *)(CONFIG_SYS_TEXT_BASE + offset); + return (struct legacy_img_hdr *)(CONFIG_SYS_TEXT_BASE + offset); else if (sysfw_load_address) return sysfw_load_address; else @@ -490,7 +490,7 @@ void k3_sysfw_loader(bool rom_loaded_sysfw, sysfw_loaded = true; /* Ensure the SYSFW image is in FIT format */ - if (image_get_magic((const image_header_t *)sysfw_load_address) != + if (image_get_magic((const struct legacy_img_hdr *)sysfw_load_address) != FDT_MAGIC) panic("SYSFW image not in FIT format!\n"); diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c index e26296b6da..4734e4c714 100644 --- a/arch/arm/mach-keystone/cmd_mon.c +++ b/arch/arm/mach-keystone/cmd_mon.c @@ -17,7 +17,7 @@ static int do_mon_install(struct cmd_tbl *cmdtp, int flag, int argc, { u32 addr, dpsc_base = 0x1E80000, freq, load_addr, size; int rcode = 0; - struct image_header *header; + struct legacy_img_hdr *header; u32 ecrypt_bm_addr = 0; if (argc < 2) @@ -27,7 +27,7 @@ static int do_mon_install(struct cmd_tbl *cmdtp, int flag, int argc, addr = hextoul(argv[1], NULL); - header = (struct image_header *)addr; + header = (struct legacy_img_hdr *)addr; if (image_get_magic(header) != IH_MAGIC) { printf("## Please update monitor image\n"); @@ -36,7 +36,7 @@ static int do_mon_install(struct cmd_tbl *cmdtp, int flag, int argc, load_addr = image_get_load(header); size = image_get_data_size(header); - memcpy((void *)load_addr, (void *)(addr + sizeof(struct image_header)), + memcpy((void *)load_addr, (void *)(addr + sizeof(struct legacy_img_hdr)), size); if (argc >= 3) diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index f79a5c62cd..04aa2fd97f 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -40,6 +40,24 @@ config TARGET_MT7629 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, switch, USB3.0, PCIe, UART, SPI, I2C and PWM. +config TARGET_MT7981 + bool "MediaTek MT7981 SoC" + select ARM64 + select CPU + help + The MediaTek MT7981 is a ARM64-based SoC with a dual-core Cortex-A53. + including UART, SPI, USB, NAND, SNFI, PWM, Gigabit Ethernet, I2C, + built-in Wi-Fi, and PCIe. + +config TARGET_MT7986 + bool "MediaTek MT7986 SoC" + select ARM64 + select CPU + help + The MediaTek MT7986 is a ARM64-based SoC with a quad-core Cortex-A53. + including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe, + Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe. + config TARGET_MT8183 bool "MediaTek MT8183 SoC" select ARM64 @@ -84,6 +102,8 @@ config SYS_BOARD default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 + default "mt7981" if TARGET_MT7981 + default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 @@ -99,6 +119,8 @@ config SYS_CONFIG_NAME default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 + default "mt7981" if TARGET_MT7981 + default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 @@ -113,6 +135,7 @@ config MTK_BROM_HEADER_INFO string default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 + default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 default "lk=1" if TARGET_MT7623 endif diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index 0f5b0c16d2..fc85293f71 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -7,6 +7,8 @@ obj-$(CONFIG_MT8512) += mt8512/ obj-$(CONFIG_TARGET_MT7622) += mt7622/ obj-$(CONFIG_TARGET_MT7623) += mt7623/ obj-$(CONFIG_TARGET_MT7629) += mt7629/ +obj-$(CONFIG_TARGET_MT7981) += mt7981/ +obj-$(CONFIG_TARGET_MT7986) += mt7986/ obj-$(CONFIG_TARGET_MT8183) += mt8183/ obj-$(CONFIG_TARGET_MT8516) += mt8516/ obj-$(CONFIG_TARGET_MT8518) += mt8518/ diff --git a/arch/arm/mach-mediatek/mt7981/Makefile b/arch/arm/mach-mediatek/mt7981/Makefile new file mode 100644 index 0000000000..007eb4a367 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7981/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c new file mode 100644 index 0000000000..4f77a3defb --- /dev/null +++ b/arch/arm/mach-mediatek/mt7981/init.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/system.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); + + return 0; +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} + +static struct mm_region mt7981_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = mt7981_mem_map; diff --git a/arch/arm/mach-mediatek/mt7981/lowlevel_init.S b/arch/arm/mach-mediatek/mt7981/lowlevel_init.S new file mode 100644 index 0000000000..85a1cea359 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7981/lowlevel_init.S @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/* + * Switch from AArch64 EL2 to AArch32 EL2 + * @param inputs: + * x0: argument, zero + * x1: machine nr + * x2: fdt address + * x3: input argument + * x4: kernel entry point + * @param outputs for secure firmware: + * x0: function id + * x1: kernel entry point + * x2: machine nr + * x3: fdt address + * + * [1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/mediatek/common/mtk_sip_svc.c +*/ + +.global armv8_el2_to_aarch32 +armv8_el2_to_aarch32: + mov x3, x2 + mov x2, x1 + mov x1, x4 + mov x4, #0 + ldr x0, =0x82000200 /* MTK_SIP_KERNEL_BOOT_AARCH32 */ + SMC #0 + ret diff --git a/arch/arm/mach-mediatek/mt7986/Makefile b/arch/arm/mach-mediatek/mt7986/Makefile new file mode 100644 index 0000000000..007eb4a367 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7986/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c new file mode 100644 index 0000000000..0fd459657d --- /dev/null +++ b/arch/arm/mach-mediatek/mt7986/init.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/system.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); + + return 0; +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} + +static struct mm_region mt7986_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = mt7986_mem_map; diff --git a/arch/arm/mach-mediatek/mt7986/lowlevel_init.S b/arch/arm/mach-mediatek/mt7986/lowlevel_init.S new file mode 100644 index 0000000000..85a1cea359 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7986/lowlevel_init.S @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/* + * Switch from AArch64 EL2 to AArch32 EL2 + * @param inputs: + * x0: argument, zero + * x1: machine nr + * x2: fdt address + * x3: input argument + * x4: kernel entry point + * @param outputs for secure firmware: + * x0: function id + * x1: kernel entry point + * x2: machine nr + * x3: fdt address + * + * [1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/mediatek/common/mtk_sip_svc.c +*/ + +.global armv8_el2_to_aarch32 +armv8_el2_to_aarch32: + mov x3, x2 + mov x2, x1 + mov x1, x4 + mov x4, #0 + ldr x0, =0x82000200 /* MTK_SIP_KERNEL_BOOT_AARCH32 */ + SMC #0 + ret diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index a81b8e2b0d..2ebe341ed1 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -14,6 +14,7 @@ config ARMADA_32BIT select SPL_SKIP_LOWLEVEL_INIT if SPL select SPL_SIMPLE_BUS if SPL select SUPPORT_SPL + select SYS_L2_PL310 if !SYS_L2CACHE_OFF select TRANSLATION_OFFSET select SPL_SYS_NO_VECTOR_TABLE if SPL select ARCH_VERY_EARLY_INIT diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index 238edbe6ba..63f6af5fe8 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; */ #define USABLE_RAM_SIZE 0x80000000ULL -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { unsigned long top = CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE); diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 4add0d9e10..2e06f2bdae 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -25,8 +25,6 @@ #define MV88F78X60 /* for the DDR training bin_hdr code */ #endif -#define CONFIG_SYS_L2_PL310 - #define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE /* Needed for SPI NOR booting in SPL */ @@ -41,9 +39,4 @@ #endif #endif -/* Use common timer */ -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) -#define CONFIG_SYS_TIMER_RATE 25000000 - #endif /* __MVEBU_CONFIG_H */ diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 914d43b049..78317e474d 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -96,6 +96,7 @@ config TI816X config AM43XX bool "AM43XX SoC" select SPECIFY_CONSOLE_INDEX + select SYS_L2_PL310 if !SYS_L2CACHE_OFF imply NAND_OMAP_ELM imply NAND_OMAP_GPMC imply SPL_DM diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 705ec7ba64..12f1d7ee56 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -205,7 +205,7 @@ int dram_init(void) return 0; } -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 0d31f10f68..cbaaf23f6b 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -16,6 +16,6 @@ obj-y += pinctrl-snapdragon.o obj-y += pinctrl-apq8016.o obj-y += pinctrl-apq8096.o obj-y += pinctrl-qcs404.o -obj-$(CONFIG_SDM845) += pinctrl-sdm845.o +obj-y += pinctrl-sdm845.o obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c b/arch/arm/mach-snapdragon/clock-apq8016.c index 6e4a0ccb90..23a37a1714 100644 --- a/arch/arm/mach-snapdragon/clock-apq8016.c +++ b/arch/arm/mach-snapdragon/clock-apq8016.c @@ -111,3 +111,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; } } + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c index e5011be8f2..66184596d5 100644 --- a/arch/arm/mach-snapdragon/clock-apq8096.c +++ b/arch/arm/mach-snapdragon/clock-apq8096.c @@ -93,3 +93,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; } } + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c b/arch/arm/mach-snapdragon/clock-qcs404.c index bb8a6fe067..6fe92afe8d 100644 --- a/arch/arm/mach-snapdragon/clock-qcs404.c +++ b/arch/arm/mach-snapdragon/clock-qcs404.c @@ -47,6 +47,14 @@ static struct pll_vote_clk gpll0_vote_clk = { .vote_bit = BIT(0), }; +static const struct bcr_regs usb30_master_regs = { + .cfg_rcgr = USB30_MASTER_CFG_RCGR, + .cmd_rcgr = USB30_MASTER_CMD_RCGR, + .M = USB30_MASTER_M, + .N = USB30_MASTER_N, + .D = USB30_MASTER_D, +}; + ulong msm_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -77,3 +85,35 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; } + +int msm_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case GCC_USB30_MASTER_CLK: + clk_enable_cbc(priv->base + USB30_MASTER_CBCR); + clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0, + CFG_CLK_SRC_GPLL0); + break; + case GCC_SYS_NOC_USB3_CLK: + clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR); + break; + case GCC_USB30_SLEEP_CLK: + clk_enable_cbc(priv->base + USB30_SLEEP_CBCR); + break; + case GCC_USB30_MOCK_UTMI_CLK: + clk_enable_cbc(priv->base + USB30_MOCK_UTMI_CBCR); + break; + case GCC_USB_HS_PHY_CFG_AHB_CLK: + clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR); + break; + case GCC_USB2A_PHY_SLEEP_CLK: + clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR); + break; + default: + return 0; + } + + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c b/arch/arm/mach-snapdragon/clock-sdm845.c index f69be80898..d6df0365af 100644 --- a/arch/arm/mach-snapdragon/clock-sdm845.c +++ b/arch/arm/mach-snapdragon/clock-sdm845.c @@ -91,3 +91,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; } } + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index 5652d2fa36..fda7098274 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -20,6 +20,7 @@ #define CBCR_BRANCH_OFF_BIT BIT(31) extern ulong msm_set_rate(struct clk *clk, ulong rate); +extern int msm_enable(struct clk *clk); /* Enable clock controlled by CBC soft macro */ void clk_enable_cbc(phys_addr_t cbcr) @@ -126,8 +127,14 @@ static ulong msm_clk_set_rate(struct clk *clk, ulong rate) return msm_set_rate(clk, rate); } +static int msm_clk_enable(struct clk *clk) +{ + return msm_enable(clk); +} + static struct clk_ops msm_clk_ops = { .set_rate = msm_clk_set_rate, + .enable = msm_clk_enable, }; static const struct udevice_id msm_clk_ids[] = { diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h index 4dc96b9fbc..e448faad2d 100644 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h @@ -37,4 +37,21 @@ #define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018) #define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C) +/* USB-3.0 controller clock control registers */ +#define SYS_NOC_USB3_CBCR (0x26014) +#define USB30_BCR (0x39000) +#define USB3PHY_BCR (0x39008) +#define USB30_MASTER_CBCR (0x3900C) +#define USB30_SLEEP_CBCR (0x39010) +#define USB30_MOCK_UTMI_CBCR (0x39014) +#define USB30_MOCK_UTMI_CMD_RCGR (0x3901C) +#define USB30_MOCK_UTMI_CFG_RCGR (0x39020) +#define USB30_MASTER_CMD_RCGR (0x39028) +#define USB30_MASTER_CFG_RCGR (0x3902C) +#define USB30_MASTER_M (0x39030) +#define USB30_MASTER_N (0x39034) +#define USB30_MASTER_D (0x39038) +#define USB2A_PHY_SLEEP_CBCR (0x4102C) +#define USB_HS_PHY_CFG_AHB_CBCR (0x41030) + #endif diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index c2148a5d0a..ab884ab6bf 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -10,6 +10,8 @@ #include <dm.h> #include <errno.h> #include <asm/io.h> +#include <dm/device_compat.h> +#include <dm/lists.h> #include <dm/pinctrl.h> #include <linux/bitops.h> #include "pinctrl-snapdragon.h" @@ -113,13 +115,37 @@ static struct pinctrl_ops msm_pinctrl_ops = { .get_function_name = msm_get_function_name, }; +static int msm_pinctrl_bind(struct udevice *dev) +{ + ofnode node = dev_ofnode(dev); + const char *name; + int ret; + + ofnode_get_property(node, "gpio-controller", &ret); + if (ret < 0) + return 0; + + /* Get the name of gpio node */ + name = ofnode_get_name(node); + if (!name) + return -EINVAL; + + /* Bind gpio node */ + ret = device_bind_driver_to_node(dev, "gpio_msm", + name, node, NULL); + if (ret) + return ret; + + dev_dbg(dev, "bind %s\n", name); + + return 0; +} + static const struct udevice_id msm_pinctrl_ids[] = { - { .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data }, - { .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data }, -#ifdef CONFIG_SDM845 - { .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data }, -#endif - { .compatible = "qcom,tlmm-qcs404", .data = (ulong)&qcs404_data }, + { .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data }, + { .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data }, + { .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data }, + { .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data }, { } }; @@ -130,4 +156,5 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = { .priv_auto = sizeof(struct msm_pinctrl_priv), .ops = &msm_pinctrl_ops, .probe = msm_pinctrl_probe, + .bind = msm_pinctrl_bind, }; diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 7267163222..b49006c6c8 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -114,7 +114,7 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, #endif #if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT) -void board_prep_linux(bootm_headers_t *images) +void board_prep_linux(struct bootm_headers *images) { if (!images->fit_uname_cfg) { if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) && diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index ec67a5b0eb..2c567edd50 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -117,7 +117,7 @@ void spl_board_init(void) /* enable console uart printing */ preloader_console_init(); - WATCHDOG_RESET(); + schedule(); arch_early_init_r(); @@ -203,7 +203,7 @@ void spl_board_init(void) */ set_regular_boot(true); - WATCHDOG_RESET(); + schedule(); reset_cpu(); } @@ -268,11 +268,11 @@ void board_init_f(ulong dummy) /* reconfigure and enable the watchdog */ hw_watchdog_init(); - WATCHDOG_RESET(); + schedule(); #endif /* CONFIG_HW_WATCHDOG */ config_dedicated_pins(gd->fdt_blob); - WATCHDOG_RESET(); + schedule(); } /* board specific function prior loading SSBL / U-Boot proper */ diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c index 68f28922d1..278253e472 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32key.c +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -11,13 +11,81 @@ #include <dm/device.h> #include <dm/uclass.h> -/* Closed device : bit 6 of OPT0*/ +/* + * Closed device: OTP0 + * STM32MP15x: bit 6 of OPT0 + * STM32MP13x: 0b111111 = 0x3F for OTP_SECURED closed device + */ #define STM32_OTP_CLOSE_ID 0 -#define STM32_OTP_CLOSE_MASK BIT(6) +#define STM32_OTP_STM32MP13x_CLOSE_MASK 0x3F +#define STM32_OTP_STM32MP15x_CLOSE_MASK BIT(6) + +/* PKH is the first element of the key list */ +#define STM32KEY_PKH 0 + +struct stm32key { + char *name; + char *desc; + u8 start; + u8 size; +}; + +const struct stm32key stm32mp13_list[] = { + [STM32KEY_PKH] = { + .name = "PKHTH", + .desc = "Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm)", + .start = 24, + .size = 8, + }, + { + .name = "EDMK", + .desc = "Encryption/Decryption Master Key", + .start = 92, + .size = 4, + } +}; + +const struct stm32key stm32mp15_list[] = { + [STM32KEY_PKH] = { + .name = "PKH", + .desc = "Hash of the ECC Public Key (ECDSA is the authentication algorithm)", + .start = 24, + .size = 8, + } +}; + +/* index of current selected key in stm32key list, 0 = PKH by default */ +static u8 stm32key_index; + +static u8 get_key_nb(void) +{ + if (IS_ENABLED(CONFIG_STM32MP13x)) + return ARRAY_SIZE(stm32mp13_list); -/* HASH of key: 8 OTPs, starting with OTP24) */ -#define STM32_OTP_HASH_KEY_START 24 -#define STM32_OTP_HASH_KEY_SIZE 8 + if (IS_ENABLED(CONFIG_STM32MP15x)) + return ARRAY_SIZE(stm32mp15_list); +} + +static const struct stm32key *get_key(u8 index) +{ + if (IS_ENABLED(CONFIG_STM32MP13x)) + return &stm32mp13_list[index]; + + if (IS_ENABLED(CONFIG_STM32MP15x)) + return &stm32mp15_list[index]; +} + +static u32 get_otp_close_mask(void) +{ + if (IS_ENABLED(CONFIG_STM32MP13x)) + return STM32_OTP_STM32MP13x_CLOSE_MASK; + + if (IS_ENABLED(CONFIG_STM32MP15x)) + return STM32_OTP_STM32MP15x_CLOSE_MASK; +} + +#define BSEC_LOCK_ERROR (-1) +#define BSEC_LOCK_PERM BIT(0) static int get_misc_dev(struct udevice **dev) { @@ -30,108 +98,115 @@ static int get_misc_dev(struct udevice **dev) return ret; } -static void read_hash_value(u32 addr) +static void read_key_value(const struct stm32key *key, u32 addr) { int i; - printf("Read KEY at 0x%x\n", addr); - for (i = 0; i < STM32_OTP_HASH_KEY_SIZE; i++) { - printf("OTP value %i: %x\n", STM32_OTP_HASH_KEY_START + i, - __be32_to_cpu(*(u32 *)addr)); + for (i = 0; i < key->size; i++) { + printf("%s OTP %i: [%08x] %08x\n", key->name, key->start + i, + addr, __be32_to_cpu(*(u32 *)addr)); addr += 4; } } -static int read_hash_otp(bool print, bool *locked, bool *closed) +static int read_key_otp(struct udevice *dev, const struct stm32key *key, bool print, bool *locked) { - struct udevice *dev; int i, word, ret; - int nb_invalid = 0, nb_zero = 0, nb_lock = 0; + int nb_invalid = 0, nb_zero = 0, nb_lock = 0, nb_lock_err = 0; u32 val, lock; bool status; - ret = get_misc_dev(&dev); - if (ret) - return ret; - - for (i = 0, word = STM32_OTP_HASH_KEY_START; i < STM32_OTP_HASH_KEY_SIZE; i++, word++) { + for (i = 0, word = key->start; i < key->size; i++, word++) { ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4); if (ret != 4) val = ~0x0; ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4); if (ret != 4) - lock = -1; + lock = BSEC_LOCK_ERROR; if (print) - printf("OTP HASH %i: %x lock : %d\n", word, val, lock); + printf("%s OTP %i: %08x lock : %08x\n", key->name, word, val, lock); if (val == ~0x0) nb_invalid++; else if (val == 0x0) nb_zero++; - if (lock == 1) + if (lock & BSEC_LOCK_PERM) nb_lock++; + if (lock & BSEC_LOCK_ERROR) + nb_lock_err++; } - word = STM32_OTP_CLOSE_ID; - ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4); - if (ret != 4) - val = 0x0; - ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4); - if (ret != 4) - lock = -1; - - status = (val & STM32_OTP_CLOSE_MASK) == STM32_OTP_CLOSE_MASK; - if (closed) - *closed = status; - if (print) - printf("OTP %d: closed status: %d lock : %d\n", word, status, lock); - - status = (nb_lock == STM32_OTP_HASH_KEY_SIZE); + status = nb_lock_err || (nb_lock == key->size); if (locked) *locked = status; - if (!status && print) - printf("Hash of key is not locked!\n"); + if (nb_lock_err && print) + printf("%s lock is invalid!\n", key->name); + else if (!status && print) + printf("%s is not locked!\n", key->name); - if (nb_invalid == STM32_OTP_HASH_KEY_SIZE) { + if (nb_invalid == key->size) { if (print) - printf("Hash of key is invalid!\n"); + printf("%s is invalid!\n", key->name); return -EINVAL; } - if (nb_zero == STM32_OTP_HASH_KEY_SIZE) { + if (nb_zero == key->size) { if (print) - printf("Hash of key is free!\n"); + printf("%s is free!\n", key->name); return -ENOENT; } return 0; } -static int fuse_hash_value(u32 addr, bool print) +static int read_close_status(struct udevice *dev, bool print, bool *closed) +{ + int word, ret, result; + u32 val, lock, mask; + bool status; + + result = 0; + word = STM32_OTP_CLOSE_ID; + ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4); + if (ret < 0) + result = ret; + if (ret != 4) + val = 0x0; + + ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4); + if (ret < 0) + result = ret; + if (ret != 4) + lock = BSEC_LOCK_ERROR; + + mask = get_otp_close_mask(); + status = (val & mask) == mask; + if (closed) + *closed = status; + if (print) + printf("OTP %d: closed status: %d lock : %08x\n", word, status, lock); + + return result; +} + +static int fuse_key_value(struct udevice *dev, const struct stm32key *key, u32 addr, bool print) { - struct udevice *dev; u32 word, val; int i, ret; - ret = get_misc_dev(&dev); - if (ret) - return ret; - - for (i = 0, word = STM32_OTP_HASH_KEY_START; - i < STM32_OTP_HASH_KEY_SIZE; - i++, word++, addr += 4) { + for (i = 0, word = key->start; i < key->size; i++, word++, addr += 4) { val = __be32_to_cpu(*(u32 *)addr); if (print) - printf("Fuse OTP %i : %x\n", word, val); + printf("Fuse %s OTP %i : %08x\n", key->name, word, val); ret = misc_write(dev, STM32_BSEC_OTP(word), &val, 4); if (ret != 4) { - log_err("Fuse OTP %i failed\n", word); + log_err("Fuse %s OTP %i failed\n", key->name, word); return ret; } - /* on success, lock the OTP for HASH key */ - val = 1; + /* on success, lock the OTP for the key */ + val = BSEC_LOCK_PERM; ret = misc_write(dev, STM32_BSEC_LOCK(word), &val, 4); if (ret != 4) { - log_err("Lock OTP %i failed\n", word); + log_err("Lock %s OTP %i failed\n", key->name, word); return ret; } } @@ -153,28 +228,103 @@ static int confirm_prog(void) return 0; } +static void display_key_info(const struct stm32key *key) +{ + printf("%s : %s\n", key->name, key->desc); + printf("\tOTP%d..%d\n", key->start, key->start + key->size); +} + +static int do_stm32key_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int i; + + for (i = 0; i < get_key_nb(); i++) + display_key_info(get_key(i)); + + return CMD_RET_SUCCESS; +} + +static int do_stm32key_select(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + const struct stm32key *key; + int i; + + if (argc == 1) { + printf("Selected key:\n"); + key = get_key(stm32key_index); + display_key_info(key); + return CMD_RET_SUCCESS; + } + + for (i = 0; i < get_key_nb(); i++) { + key = get_key(i); + if (!strcmp(key->name, argv[1])) { + printf("%s selected\n", key->name); + stm32key_index = i; + return CMD_RET_SUCCESS; + } + } + + printf("Unknown key %s\n", argv[1]); + + return CMD_RET_FAILURE; +} + static int do_stm32key_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + const struct stm32key *key; + struct udevice *dev; u32 addr; + int ret, i; + int result; + + ret = get_misc_dev(&dev); if (argc == 1) { - read_hash_otp(true, NULL, NULL); + if (ret) + return CMD_RET_FAILURE; + key = get_key(stm32key_index); + ret = read_key_otp(dev, key, true, NULL); + if (ret != -ENOENT) + return CMD_RET_FAILURE; return CMD_RET_SUCCESS; } + if (!strcmp("-a", argv[1])) { + if (ret) + return CMD_RET_FAILURE; + result = CMD_RET_SUCCESS; + for (i = 0; i < get_key_nb(); i++) { + key = get_key(i); + ret = read_key_otp(dev, key, true, NULL); + if (ret != -ENOENT) + result = CMD_RET_FAILURE; + } + ret = read_close_status(dev, true, NULL); + if (ret) + result = CMD_RET_FAILURE; + + return result; + } + addr = hextoul(argv[1], NULL); if (!addr) return CMD_RET_USAGE; - read_hash_value(addr); + key = get_key(stm32key_index); + printf("Read %s at 0x%08x\n", key->name, addr); + read_key_value(key, addr); return CMD_RET_SUCCESS; } static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + const struct stm32key *key = get_key(stm32key_index); + struct udevice *dev; u32 addr; - bool yes = false, lock, closed; + int ret; + bool yes = false, lock; if (argc < 2) return CMD_RET_USAGE; @@ -189,29 +339,38 @@ static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *con if (!addr) return CMD_RET_USAGE; - if (read_hash_otp(!yes, &lock, &closed) != -ENOENT) { + ret = get_misc_dev(&dev); + if (ret) + return CMD_RET_FAILURE; + + if (read_key_otp(dev, key, !yes, &lock) != -ENOENT) { printf("Error: can't fuse again the OTP\n"); return CMD_RET_FAILURE; } - - if (lock || closed) { - printf("Error: invalid OTP configuration (lock=%d, closed=%d)\n", lock, closed); + if (lock) { + printf("Error: %s is locked\n", key->name); return CMD_RET_FAILURE; } + if (!yes) { + printf("Writing %s with\n", key->name); + read_key_value(key, addr); + } + if (!yes && !confirm_prog()) return CMD_RET_FAILURE; - if (fuse_hash_value(addr, !yes)) + if (fuse_key_value(dev, key, addr, !yes)) return CMD_RET_FAILURE; - printf("Hash key updated !\n"); + printf("%s updated !\n", key->name); return CMD_RET_SUCCESS; } static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + const struct stm32key *key; bool yes, lock, closed; struct udevice *dev; u32 val; @@ -224,32 +383,36 @@ static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *co yes = true; } - ret = read_hash_otp(!yes, &lock, &closed); - if (ret) { - if (ret == -ENOENT) - printf("Error: OTP not programmed!\n"); + ret = get_misc_dev(&dev); + if (ret) + return CMD_RET_FAILURE; + + if (read_close_status(dev, !yes, &closed)) return CMD_RET_FAILURE; - } if (closed) { printf("Error: already closed!\n"); return CMD_RET_FAILURE; } + /* check PKH status before to close */ + key = get_key(STM32KEY_PKH); + ret = read_key_otp(dev, key, !yes, &lock); + if (ret) { + if (ret == -ENOENT) + printf("Error: %s not programmed!\n", key->name); + return CMD_RET_FAILURE; + } if (!lock) - printf("Warning: OTP not locked!\n"); + printf("Warning: %s not locked!\n", key->name); if (!yes && !confirm_prog()) return CMD_RET_FAILURE; - ret = get_misc_dev(&dev); - if (ret) - return CMD_RET_FAILURE; - - val = STM32_OTP_CLOSE_MASK; + val = get_otp_close_mask(); ret = misc_write(dev, STM32_BSEC_OTP(STM32_OTP_CLOSE_ID), &val, 4); if (ret != 4) { - printf("Error: can't update OTP\n"); + printf("Error: can't update OTP %d\n", STM32_OTP_CLOSE_ID); return CMD_RET_FAILURE; } @@ -259,11 +422,15 @@ static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *co } static char stm32key_help_text[] = - "read [<addr>]: Read the hash stored at addr in memory or in OTP\n" - "stm32key fuse [-y] <addr> : Fuse hash stored at addr in OTP\n" - "stm32key close [-y] : Close the device, the hash stored in OTP\n"; - -U_BOOT_CMD_WITH_SUBCMDS(stm32key, "Fuse ST Hash key", stm32key_help_text, + "list : list the supported key with description\n" + "stm32key select [<key>] : Select the key identified by <key> or display the key used for read/fuse command\n" + "stm32key read [<addr> | -a ] : Read the curent key at <addr> or current / all (-a) key in OTP\n" + "stm32key fuse [-y] <addr> : Fuse the current key at addr in OTP\n" + "stm32key close [-y] : Close the device\n"; + +U_BOOT_CMD_WITH_SUBCMDS(stm32key, "Manage key on STM32", stm32key_help_text, + U_BOOT_SUBCMD_MKENT(list, 1, 0, do_stm32key_list), + U_BOOT_SUBCMD_MKENT(select, 2, 0, do_stm32key_select), U_BOOT_SUBCMD_MKENT(read, 2, 0, do_stm32key_read), U_BOOT_SUBCMD_MKENT(fuse, 3, 0, do_stm32key_fuse), U_BOOT_SUBCMD_MKENT(close, 2, 0, do_stm32key_close)); diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index f59414e716..d2666b9775 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -61,7 +61,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, dev = (int)dectoul(argv[2], NULL); - addr = STM32_DDR_BASE; + addr = CONFIG_SYS_LOAD_ADDR; size = 0; if (argc > 3) { addr = hextoul(argv[3], NULL); @@ -126,21 +126,21 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, char *bootm_argv[5] = { "bootm", boot_addr_start, "-", dtb_addr, NULL }; - u32 uimage = data->uimage; - u32 dtb = data->dtb; - u32 initrd = data->initrd; + const void *uimage = (void *)data->uimage; + const void *dtb = (void *)data->dtb; + const void *initrd = (void *)data->initrd; if (!dtb) bootm_argv[3] = env_get("fdtcontroladdr"); else snprintf(dtb_addr, sizeof(dtb_addr) - 1, - "0x%x", dtb); + "0x%p", dtb); snprintf(boot_addr_start, sizeof(boot_addr_start) - 1, - "0x%x", uimage); + "0x%p", uimage); if (initrd) { - snprintf(initrd_addr, sizeof(initrd_addr) - 1, "0x%x:0x%x", + snprintf(initrd_addr, sizeof(initrd_addr) - 1, "0x%p:0x%zx", initrd, data->initrd_size); bootm_argv[2] = initrd_addr; } @@ -148,7 +148,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, printf("Booting kernel at %s %s %s...\n\n\n", boot_addr_start, bootm_argv[2], bootm_argv[3]); /* Try bootm for legacy and FIT format image */ - if (genimg_get_format((void *)uimage) != IMAGE_FORMAT_INVALID) + if (genimg_get_format(uimage) != IMAGE_FORMAT_INVALID) do_bootm(cmdtp, 0, 4, bootm_argv); else if (CONFIG_IS_ENABLED(CMD_BOOTZ)) do_bootz(cmdtp, 0, 4, bootm_argv); diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index c391b6c7ab..89552d2ad1 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -322,7 +322,7 @@ void stm32prog_header_check(uintptr_t raw_header, struct image_header_s *header) header->image_length = 0x0; } -static u32 stm32prog_header_checksum(u32 addr, struct image_header_s *header) +static u32 stm32prog_header_checksum(uintptr_t addr, struct image_header_s *header) { u32 i, checksum; u8 *payload; @@ -398,7 +398,7 @@ static int parse_name(struct stm32prog_data *data, if (strlen(p) < sizeof(part->name)) { strcpy(part->name, p); } else { - stm32prog_err("Layout line %d: partition name too long [%d]: %s", + stm32prog_err("Layout line %d: partition name too long [%zd]: %s", i, strlen(p), p); result = -EINVAL; } @@ -537,7 +537,7 @@ int (* const parse[COL_NB_STM32])(struct stm32prog_data *data, int i, char *p, }; static int parse_flash_layout(struct stm32prog_data *data, - ulong addr, + uintptr_t addr, ulong size) { int column = 0, part_nb = 0, ret; @@ -1090,7 +1090,6 @@ static int create_gpt_partitions(struct stm32prog_data *data) if (!buf) return -ENOMEM; - puts("partitions : "); /* initialize the selected device */ for (i = 0; i < data->dev_nb; i++) { /* create gpt partition support only for full update on MMC */ @@ -1098,6 +1097,7 @@ static int create_gpt_partitions(struct stm32prog_data *data) !data->dev[i].full_update) continue; + printf("partitions on mmc%d: ", data->dev[i].dev_id); offset = 0; rootfs_found = false; memset(buf, 0, buflen); @@ -1197,8 +1197,8 @@ static int create_gpt_partitions(struct stm32prog_data *data) sprintf(buf, "part list mmc %d", data->dev[i].dev_id); run_command(buf, 0); #endif + puts("done\n"); } - puts("done\n"); #ifdef DEBUG run_command("mtd list", 0); @@ -1342,10 +1342,22 @@ static int dfu_init_entities(struct stm32prog_data *data) struct stm32prog_part_t *part; struct dfu_entity *dfu; int alt_nb; + u32 otp_size = 0; alt_nb = 1; /* number of virtual = CMD*/ - if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) - alt_nb++; /* OTP*/ + + if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { + /* OTP_SIZE_SMC = 0 if SMC is not supported */ + otp_size = OTP_SIZE_SMC; + /* check if PTA BSEC is supported */ + ret = optee_ta_open(data); + log_debug("optee_ta_open(PTA_NVMEM) result %d\n", ret); + if (!ret && data->tee) + otp_size = OTP_SIZE_TA; + if (otp_size) + alt_nb++; /* OTP*/ + } + if (CONFIG_IS_ENABLED(DM_PMIC)) alt_nb++; /* PMIC NVMEM*/ @@ -1363,6 +1375,7 @@ static int dfu_init_entities(struct stm32prog_data *data) puts("DFU alt info setting: "); if (data->part_nb) { alt_id = 0; + ret = 0; for (phase = 1; (phase <= PHASE_LAST_USER) && (alt_id < alt_nb) && !ret; @@ -1388,7 +1401,7 @@ static int dfu_init_entities(struct stm32prog_data *data) char buf[ALT_BUF_LEN]; sprintf(buf, "@FlashLayout/0x%02x/1*256Ke ram %x 40000", - PHASE_FLASHLAYOUT, STM32_DDR_BASE); + PHASE_FLASHLAYOUT, CONFIG_SYS_LOAD_ADDR); ret = dfu_alt_add(dfu, "ram", NULL, buf); log_debug("dfu_alt_add(ram, NULL,%s) result %d\n", buf, ret); } @@ -1396,12 +1409,8 @@ static int dfu_init_entities(struct stm32prog_data *data) if (!ret) ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, CMD_SIZE); - if (!ret && IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { - ret = optee_ta_open(data); - log_debug("optee_ta result %d\n", ret); - ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, - data->tee ? OTP_SIZE_TA : OTP_SIZE_SMC); - } + if (!ret && IS_ENABLED(CONFIG_CMD_STM32PROG_OTP) && otp_size) + ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, otp_size); if (!ret && CONFIG_IS_ENABLED(DM_PMIC)) ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, PMIC_SIZE); @@ -1440,7 +1449,7 @@ int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer, if (offset + *size > otp_size) *size = otp_size - offset; - memcpy((void *)((u32)data->otp_part + offset), buffer, *size); + memcpy((void *)((uintptr_t)data->otp_part + offset), buffer, *size); return 0; } @@ -1479,7 +1488,7 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer, data->otp_part, OTP_SIZE_TA); else if (IS_ENABLED(CONFIG_ARM_SMCCC)) result = stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_READ_ALL, - (u32)data->otp_part, 0); + (unsigned long)data->otp_part, 0); if (result) goto end_otp_read; } @@ -1491,7 +1500,7 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer, if (offset + *size > otp_size) *size = otp_size - offset; - memcpy(buffer, (void *)((u32)data->otp_part + offset), *size); + memcpy(buffer, (void *)((uintptr_t)data->otp_part + offset), *size); end_otp_read: log_debug("%s: result %i\n", __func__, result); @@ -1521,7 +1530,7 @@ int stm32prog_otp_start(struct stm32prog_data *data) data->otp_part, OTP_SIZE_TA); } else if (IS_ENABLED(CONFIG_ARM_SMCCC)) { arm_smccc_smc(STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, - (u32)data->otp_part, 0, 0, 0, 0, 0, &res); + (uintptr_t)data->otp_part, 0, 0, 0, 0, 0, &res); if (!res.a0) { switch (res.a1) { @@ -1699,15 +1708,15 @@ static void stm32prog_end_phase(struct stm32prog_data *data, u64 offset) { if (data->phase == PHASE_FLASHLAYOUT) { #if defined(CONFIG_LEGACY_IMAGE_FORMAT) - if (genimg_get_format((void *)STM32_DDR_BASE) == IMAGE_FORMAT_LEGACY) { - data->script = STM32_DDR_BASE; + if (genimg_get_format((void *)CONFIG_SYS_LOAD_ADDR) == IMAGE_FORMAT_LEGACY) { + data->script = CONFIG_SYS_LOAD_ADDR; data->phase = PHASE_END; log_notice("U-Boot script received\n"); return; } #endif log_notice("\nFlashLayout received, size = %lld\n", offset); - if (parse_flash_layout(data, STM32_DDR_BASE, offset)) + if (parse_flash_layout(data, CONFIG_SYS_LOAD_ADDR, offset)) stm32prog_err("Layout: invalid FlashLayout"); return; } @@ -1823,7 +1832,7 @@ static int part_delete(struct stm32prog_data *data, * need to switch to associated hwpart 1 or 2 */ if (part->part_id < 0) - if (blk_select_hwpart_devnum(IF_TYPE_MMC, + if (blk_select_hwpart_devnum(UCLASS_MMC, part->dev->dev_id, -part->part_id)) return -1; @@ -1832,7 +1841,7 @@ static int part_delete(struct stm32prog_data *data, /* return to user partition */ if (part->part_id < 0) - blk_select_hwpart_devnum(IF_TYPE_MMC, + blk_select_hwpart_devnum(UCLASS_MMC, part->dev->dev_id, 0); if (blks != blks_size) { ret = -1; @@ -1884,6 +1893,10 @@ static void stm32prog_devices_init(struct stm32prog_data *data) if (ret) goto error; + /* empty flashlayout */ + if (!data->dev_nb) + return; + /* initialize the selected device */ for (i = 0; i < data->dev_nb; i++) { ret = init_device(data, &data->dev[i]); @@ -1947,7 +1960,7 @@ int stm32prog_dfu_init(struct stm32prog_data *data) return dfu_init_entities(data); } -int stm32prog_init(struct stm32prog_data *data, ulong addr, ulong size) +int stm32prog_init(struct stm32prog_data *data, uintptr_t addr, ulong size) { memset(data, 0x0, sizeof(*data)); data->read_phase = PHASE_RESET; diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h index ac300768ca..58f4b96fa7 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h @@ -20,7 +20,12 @@ #define DEFAULT_ADDRESS 0xFFFFFFFF #define CMD_SIZE 512 +/* SMC is only supported in SPMIN for STM32MP15x */ +#ifdef CONFIG_STM32MP15x #define OTP_SIZE_SMC 1024 +#else +#define OTP_SIZE_SMC 0 +#endif #define OTP_SIZE_TA 776 #define PMIC_SIZE 8 @@ -154,7 +159,7 @@ struct stm32prog_data { u32 offset; char error[255]; struct stm32prog_part_t *cur_part; - u32 *otp_part; + void *otp_part; u8 pmic_part[PMIC_SIZE]; /* SERIAL information */ @@ -165,12 +170,12 @@ struct stm32prog_data { u8 read_phase; /* bootm information */ - u32 uimage; - u32 dtb; - u32 initrd; - u32 initrd_size; + uintptr_t uimage; + uintptr_t dtb; + uintptr_t initrd; + size_t initrd_size; - u32 script; + uintptr_t script; /* OPTEE PTA NVMEM */ struct udevice *tee; @@ -209,7 +214,7 @@ char *stm32prog_get_error(struct stm32prog_data *data); } /* Main function */ -int stm32prog_init(struct stm32prog_data *data, ulong addr, ulong size); +int stm32prog_init(struct stm32prog_data *data, uintptr_t addr, ulong size); void stm32prog_clean(struct stm32prog_data *data); #ifdef CONFIG_CMD_STM32PROG_SERIAL diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c index 2932eae757..f1bed7d1a3 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c @@ -247,7 +247,7 @@ static int stm32prog_serial_getc_err(void) err = ops->getc(down_serial_dev); if (err == -EAGAIN) { ctrlc(); - WATCHDOG_RESET(); + schedule(); } } while ((err == -EAGAIN) && (!had_ctrlc())); @@ -276,7 +276,7 @@ static bool stm32prog_serial_get_buffer(u8 *buffer, u32 *count) *count -= 1; } else if (err == -EAGAIN) { ctrlc(); - WATCHDOG_RESET(); + schedule(); if (get_timer(start) > TIMEOUT_SERIAL_BUFFER) { err = -ETIMEDOUT; break; @@ -300,7 +300,7 @@ static void stm32prog_serial_putc(u8 w_byte) } /* Helper function ************************************************/ -static u8 stm32prog_start(struct stm32prog_data *data, u32 address) +static u8 stm32prog_start(struct stm32prog_data *data, uintptr_t address) { u8 ret = 0; struct dfu_entity *dfu_entity; @@ -353,7 +353,7 @@ static u8 stm32prog_start(struct stm32prog_data *data, u32 address) } else { void (*entry)(void) = (void *)address; - printf("## Starting application at 0x%x ...\n", address); + printf("## Starting application at 0x%p ...\n", (void *)address); (*entry)(); printf("## Application terminated\n"); ret = -ENOEXEC; @@ -368,9 +368,9 @@ static u8 stm32prog_start(struct stm32prog_data *data, u32 address) * @tmp_xor: Current xor value to update * Return: The address area */ -static u32 get_address(u8 *tmp_xor) +static uintptr_t get_address(u8 *tmp_xor) { - u32 address = 0x0; + uintptr_t address = 0x0; u8 data; data = stm32prog_serial_getc(); @@ -462,7 +462,7 @@ static void get_phase_command(struct stm32prog_data *data) length = strlen(err_msg); } if (phase == PHASE_FLASHLAYOUT) - destination = STM32_DDR_BASE; + destination = CONFIG_SYS_LOAD_ADDR; stm32prog_serial_putc(length + 5); /* Total length */ stm32prog_serial_putc(phase & 0xFF); /* partition ID */ @@ -487,7 +487,7 @@ static void get_phase_command(struct stm32prog_data *data) */ static void read_memory_command(struct stm32prog_data *data) { - u32 address = 0x0; + uintptr_t address = 0x0; u8 rcv_data = 0x0, tmp_xor = 0x0; u32 counter = 0x0; @@ -532,7 +532,7 @@ static void read_memory_command(struct stm32prog_data *data) */ static void start_command(struct stm32prog_data *data) { - u32 address = 0; + uintptr_t address = 0; u8 tmp_xor = 0x0; u8 ret, rcv_data; @@ -546,8 +546,7 @@ static void start_command(struct stm32prog_data *data) return; } /* validate partition */ - ret = stm32prog_start(data, - address); + ret = stm32prog_start(data, address); if (ret) stm32prog_serial_result(ABORT_BYTE); @@ -852,7 +851,7 @@ bool stm32prog_serial_loop(struct stm32prog_data *data) stm32prog_serial_result(ACK_BYTE); cmd_func[counter](data); } - WATCHDOG_RESET(); + schedule(); } /* clean device */ diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c index a8b57c4d8f..be38ff239b 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c @@ -41,7 +41,7 @@ static int stm32prog_set_phase(struct stm32prog_data *data, u8 phase, static int stm32prog_cmd_write(u64 offset, void *buf, long *len) { u8 phase; - u32 address; + uintptr_t address; u8 *pt = buf; void (*entry)(void); int ret; @@ -58,7 +58,7 @@ static int stm32prog_cmd_write(u64 offset, void *buf, long *len) address = (pt[1] << 24) | (pt[2] << 16) | (pt[3] << 8) | pt[4]; if (phase == PHASE_RESET) { entry = (void *)address; - printf("## Starting application at 0x%x ...\n", address); + printf("## Starting application at 0x%p ...\n", entry); (*entry)(); printf("## Application terminated\n"); return 0; @@ -90,7 +90,7 @@ static int stm32prog_cmd_read(u64 offset, void *buf, long *len) } phase = stm32prog_data->phase; if (phase == PHASE_FLASHLAYOUT) - destination = STM32_DDR_BASE; + destination = CONFIG_SYS_LOAD_ADDR; dfu_offset = stm32prog_data->offset; /* mandatory header, size = PHASE_MIN_SIZE */ diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 920b99bb68..9346fa8546 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -40,7 +40,7 @@ int dram_init(void) return 0; } -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { phys_size_t size; phys_addr_t reg; diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 8f7c894286..62bb40b8c8 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -65,7 +65,7 @@ static struct mm_region sunxi_mem_map[] = { }; struct mm_region *mem_map = sunxi_mem_map; -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { /* Some devices (like the EMAC) have a 32-bit DMA limit. */ if (gd->ram_top > (1ULL << 32)) diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index de9aa68c4a..925bf85f2d 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -335,10 +335,10 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { int ret = 0; - struct image_header *header; - header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); + struct legacy_img_hdr *header; uint32_t load_offset = sunxi_get_spl_size(); + header = (struct legacy_img_hdr *)CONFIG_SYS_TEXT_BASE; load_offset = max_t(uint32_t, load_offset, CONFIG_SYS_SPI_U_BOOT_OFFS); spi0_init(); diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 8950e678a6..1994db0e15 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -401,7 +401,7 @@ int dram_init_banksize(void) * This function is called before dram_init_banksize(), so we can't simply * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. */ -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { ulong ram_top; diff --git a/arch/arm/mach-tegra/xusb-padctl-common.c b/arch/arm/mach-tegra/xusb-padctl-common.c index 8bdd44ad7a..388ec49968 100644 --- a/arch/arm/mach-tegra/xusb-padctl-common.c +++ b/arch/arm/mach-tegra/xusb-padctl-common.c @@ -282,7 +282,7 @@ int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count, debug("%s: count=%d\n", __func__, count); for (i = 0; i < count; i++) { debug("%s: i=%d, node=%p\n", __func__, i, nodes[i].np); - if (!ofnode_is_available(nodes[i])) + if (!ofnode_is_enabled(nodes[i])) continue; padctl.socdata = socdata; diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig new file mode 100644 index 0000000000..62825e189f --- /dev/null +++ b/arch/arm/mach-versal-net/Kconfig @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0 + +if ARCH_VERSAL_NET + +config SYS_BOARD + string "Board name" + default "versal-net" + +config SYS_VENDOR + string "Vendor name" + default "xilinx" + +config SYS_SOC + default "versal-net" + +config SYS_CONFIG_NAME + string "Board configuration name" + default "xilinx_versal_net" + help + This option contains information about board configuration name. + Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header + will be used for board configuration. + +config SYS_MEM_RSVD_FOR_MMU + bool "Reserve memory for MMU Table" + help + If defined this option is used to setup different space for + MMU table than the one which will be allocated during + relocation. + +config GICV3 + def_bool y + +config SYS_MALLOC_LEN + default 0x2000000 + +config ZYNQ_SDHCI_MAX_FREQ + default 200000000 + +source "board/xilinx/Kconfig" +source "board/xilinx/versal-net/Kconfig" + +endif diff --git a/arch/arm/mach-versal-net/Makefile b/arch/arm/mach-versal-net/Makefile new file mode 100644 index 0000000000..e12c4c0e67 --- /dev/null +++ b/arch/arm/mach-versal-net/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2021 - 2022, Xilinx, Inc. +# Copyright (C) 2022, Advanced Micro Devices, Inc. +# +# Michal Simek <michal.simek@amd.com> +# + +obj-y += clk.o +obj-y += cpu.o diff --git a/arch/arm/mach-versal-net/clk.c b/arch/arm/mach-versal-net/clk.c new file mode 100644 index 0000000000..d097de7afa --- /dev/null +++ b/arch/arm/mach-versal-net/clk.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 - 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <common.h> +#include <init.h> +#include <time.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CLOCKS +/** + * set_cpu_clk_info - Initialize clock framework + * + * Return: 0 always. + * + * This function is called from common code after relocation and sets up the + * clock framework. The framework must not be used before this function had been + * called. + */ +int set_cpu_clk_info(void) +{ + gd->cpu_clk = get_tbclk(); + + gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; + gd->bd->bi_dsp_freq = 0; + + return 0; +} +#endif diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c new file mode 100644 index 0000000000..4c9b15411d --- /dev/null +++ b/arch/arm/mach-versal-net/cpu.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <common.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/cache.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <asm/cache.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define VERSAL_NET_MEM_MAP_USED 5 + +#define DRAM_BANKS CONFIG_NR_DRAM_BANKS + +/* +1 is end of list which needs to be empty */ +#define VERSAL_NET_MEM_MAP_MAX (VERSAL_NET_MEM_MAP_USED + DRAM_BANKS + 1) + +static struct mm_region versal_mem_map[VERSAL_NET_MEM_MAP_MAX] = { + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x70000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x0fe00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x400000000UL, + .phys = 0x400000000UL, + .size = 0x200000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x600000000UL, + .phys = 0x600000000UL, + .size = 0x800000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xe00000000UL, + .phys = 0xe00000000UL, + .size = 0xf200000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + } +}; + +void mem_map_fill(void) +{ + int banks = VERSAL_NET_MEM_MAP_USED; + + for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + /* Zero size means no more DDR that's this is end */ + if (!gd->bd->bi_dram[i].size) + break; + + versal_mem_map[banks].virt = gd->bd->bi_dram[i].start; + versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; + versal_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE; + banks = banks + 1; + } +} + +struct mm_region *mem_map = versal_mem_map; + +u64 get_page_table_size(void) +{ + return 0x14000; +} diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h b/arch/arm/mach-versal-net/include/mach/hardware.h new file mode 100644 index 0000000000..808ce48fd1 --- /dev/null +++ b/arch/arm/mach-versal-net/include/mach/hardware.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 - 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + */ + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#endif + +#define PMC_TAP 0xF11A0000 + +#define PMC_TAP_IDCODE (PMC_TAP + 0) +#define PMC_TAP_VERSION (PMC_TAP + 0x4) +# define PMC_VERSION_MASK GENMASK(7, 0) +# define PS_VERSION_MASK GENMASK(15, 8) +# define RTL_VERSION_MASK GENMASK(23, 16) +# define PLATFORM_MASK GENMASK(27, 24) +# define PLATFORM_VERSION_MASK GENMASK(31, 28) +#define PMC_TAP_USERCODE (PMC_TAP + 0x8) + +enum versal_net_platform { + VERSAL_NET_SILICON = 0, + VERSAL_NET_SPP = 1, + VERSAL_NET_EMU = 2, + VERSAL_NET_QEMU = 3, +}; + +#define VERSAL_SLCR_BASEADDR 0xF1060000 +#define VERSAL_AXI_MUX_SEL (VERSAL_SLCR_BASEADDR + 0x504) +#define VERSAL_OSPI_LINEAR_MODE BIT(1) diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h b/arch/arm/mach-versal-net/include/mach/sys_proto.h new file mode 100644 index 0000000000..5bba9030f2 --- /dev/null +++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + */ + +#include <linux/build_bug.h> + +void mem_map_fill(void); + +static inline int zynqmp_mmio_write(const u32 address, const u32 mask, + const u32 value) +{ + BUILD_BUG(); + return -EINVAL; +} diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index 05934c28d6..8e5712e0c9 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -3,6 +3,8 @@ * Copyright 2016 - 2018 Xilinx, Inc. */ +#include <linux/build_bug.h> + enum { TCM_LOCK, TCM_SPLIT, @@ -10,3 +12,9 @@ enum { void tcm_init(u8 mode); void mem_map_fill(void); + +static inline int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) +{ + BUILD_BUG(); + return -EINVAL; +} diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile index 8737f434d9..d9b2b999e1 100644 --- a/arch/arm/mach-zynq/Makefile +++ b/arch/arm/mach-zynq/Makefile @@ -6,7 +6,6 @@ # (C) Copyright 2008 # Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> -obj-y := timer.o obj-y += cpu.o obj-y += ddrc.o obj-y += slcr.o diff --git a/arch/arm/mach-zynq/clk.c b/arch/arm/mach-zynq/clk.c index 27f6bf2183..1945f60e08 100644 --- a/arch/arm/mach-zynq/clk.c +++ b/arch/arm/mach-zynq/clk.c @@ -52,10 +52,12 @@ int set_cpu_clk_info(void) return ret; rate = clk_get_rate(&clk) / 1000000; - if (i) + if (i) { gd->bd->bi_ddr_freq = rate; - else + } else { gd->bd->bi_arm_freq = rate; + gd->cpu_clk = clk_get_rate(&clk); + } clk_free(&clk); } diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c deleted file mode 100644 index a51822a530..0000000000 --- a/arch/arm/mach-zynq/timer.c +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Weidmüller Interface GmbH & Co. KG - * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> - * - * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> - * Copyright (C) 2011-2017 Xilinx, Inc. All rights reserved. - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. <philippe.robin@arm.com> - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * (C) Copyright 2003 - * Texas Instruments <www.ti.com> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - */ - -#include <clk.h> -#include <common.h> -#include <div64.h> -#include <dm.h> -#include <init.h> -#include <time.h> -#include <malloc.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/clk.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct scu_timer { - u32 load; /* Timer Load Register */ - u32 counter; /* Timer Counter Register */ - u32 control; /* Timer Control Register */ -}; - -static struct scu_timer *timer_base = - (struct scu_timer *)ZYNQ_SCUTIMER_BASEADDR; - -#define SCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /* Prescaler */ -#define SCUTIMER_CONTROL_PRESCALER_SHIFT 8 -#define SCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /* Auto-reload */ -#define SCUTIMER_CONTROL_ENABLE_MASK 0x00000001 /* Timer enable */ - -#define TIMER_LOAD_VAL 0xFFFFFFFF -#define TIMER_PRESCALE 255 - -int timer_init(void) -{ - const u32 emask = SCUTIMER_CONTROL_AUTO_RELOAD_MASK | - (TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) | - SCUTIMER_CONTROL_ENABLE_MASK; - - struct udevice *dev; - struct clk clk; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_DRIVER_GET(zynq_clk), &dev); - if (ret) - return ret; - - clk.id = cpu_6or4x_clk; - ret = clk_request(dev, &clk); - if (ret < 0) - return ret; - - gd->cpu_clk = clk_get_rate(&clk); - - clk_free(&clk); - - gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1); - - /* Load the timer counter register */ - writel(0xFFFFFFFF, &timer_base->load); - - /* - * Start the A9Timer device - * Enable Auto reload mode, Clear prescaler control bits - * Set prescaler value, Enable the decrementer - */ - clrsetbits_le32(&timer_base->control, SCUTIMER_CONTROL_PRESCALER_MASK, - emask); - - /* Reset time */ - gd->arch.lastinc = readl(&timer_base->counter) / - (gd->arch.timer_rate_hz / CONFIG_SYS_HZ); - gd->arch.tbl = 0; - - return 0; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return gd->arch.timer_rate_hz; -} diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds index a5169fd915..3b7c9d515f 100644 --- a/arch/arm/mach-zynq/u-boot.lds +++ b/arch/arm/mach-zynq/u-boot.lds @@ -75,7 +75,7 @@ SECTIONS *(.__efi_runtime_rel_stop) } - . = ALIGN(4); + . = ALIGN(8); .image_copy_end : { *(.__image_copy_end) @@ -114,7 +114,7 @@ SECTIONS .bss __bss_base (OVERLAY) : { *(.bss*) - . = ALIGN(4); + . = ALIGN(8); __bss_limit = .; } diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c index 9cade92954..c1c9bdceb5 100644 --- a/arch/m68k/lib/bootm.c +++ b/arch/m68k/lib/bootm.c @@ -36,7 +36,7 @@ void arch_lmb_reserve(struct lmb *lmb) } int do_bootm_linux(int flag, int argc, char *const argv[], - bootm_headers_t *images) + struct bootm_headers *images) { int ret; struct bd_info *kbd; diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c index ebb2ac54db..cd7437b3e2 100644 --- a/arch/m68k/lib/time.c +++ b/arch/m68k/lib/time.c @@ -72,7 +72,7 @@ void dtimer_interrupt(void *not_used) #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) if (CONFIG_SYS_WATCHDOG_FREQ && (timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) { - WATCHDOG_RESET (); + schedule(); } #endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ return; diff --git a/arch/microblaze/lib/Makefile b/arch/microblaze/lib/Makefile index 05f447abba..dfd8135f4f 100644 --- a/arch/microblaze/lib/Makefile +++ b/arch/microblaze/lib/Makefile @@ -4,4 +4,5 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BDI) += bdinfo.o obj-y += muldi3.o diff --git a/arch/microblaze/lib/bdinfo.c b/arch/microblaze/lib/bdinfo.c new file mode 100644 index 0000000000..41b7a216a4 --- /dev/null +++ b/arch/microblaze/lib/bdinfo.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022, Ovidiu Panait <ovpanait@gmail.com> + */ +#include <init.h> +#include <asm/cpuinfo.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +void arch_print_bdinfo(void) +{ + struct microblaze_cpuinfo *ci = gd_cpuinfo(); + + if (ci->icache_size) { + bdinfo_print_size("icache", ci->icache_size); + bdinfo_print_size("icache line", ci->icache_line_length); + } + + if (ci->dcache_size) { + bdinfo_print_size("dcache", ci->dcache_size); + bdinfo_print_size("dcache line", ci->dcache_line_length); + } +} diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 31b6659cdf..4a5421497e 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -37,7 +37,7 @@ void arch_lmb_reserve(struct lmb *lmb) arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); } -static void boot_jump_linux(bootm_headers_t *images, int flag) +static void boot_jump_linux(struct bootm_headers *images, int flag) { void (*thekernel)(char *cmdline, ulong rd, ulong dt); ulong dt = (ulong)images->ft_addr; @@ -71,7 +71,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) } } -static void boot_prep_linux(bootm_headers_t *images) +static void boot_prep_linux(struct bootm_headers *images) { if (CONFIG_IS_ENABLED(OF_LIBFDT) && CONFIG_IS_ENABLED(LMB) && images->ft_len) { debug("using: FDT\n"); @@ -83,7 +83,7 @@ static void boot_prep_linux(bootm_headers_t *images) } int do_bootm_linux(int flag, int argc, char *const argv[], - bootm_headers_t *images) + struct bootm_headers *images) { images->cmdline_start = (ulong)env_get("bootargs"); diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index cab8da4860..5fda914e6b 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -71,7 +71,7 @@ static void linux_cmdline_dump(void) debug(" arg %03d: %s\n", i, linux_argv[i]); } -static void linux_cmdline_legacy(bootm_headers_t *images) +static void linux_cmdline_legacy(struct bootm_headers *images) { const char *bootargs, *next, *quote; @@ -111,7 +111,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images) } } -static void linux_cmdline_append(bootm_headers_t *images) +static void linux_cmdline_append(struct bootm_headers *images) { char buf[24]; ulong mem, rd_start, rd_size; @@ -164,7 +164,7 @@ static void linux_env_set(const char *env_name, const char *env_val) } } -static void linux_env_legacy(bootm_headers_t *images) +static void linux_env_legacy(struct bootm_headers *images) { char env_buf[12]; const char *cp; @@ -213,7 +213,7 @@ static void linux_env_legacy(bootm_headers_t *images) } } -static int boot_reloc_fdt(bootm_headers_t *images) +static int boot_reloc_fdt(struct bootm_headers *images) { /* * In case of legacy uImage's, relocation of FDT is already done @@ -243,7 +243,7 @@ int arch_fixup_fdt(void *blob) } #endif -static int boot_setup_fdt(bootm_headers_t *images) +static int boot_setup_fdt(struct bootm_headers *images) { images->initrd_start = virt_to_phys((void *)images->initrd_start); images->initrd_end = virt_to_phys((void *)images->initrd_end); @@ -251,7 +251,7 @@ static int boot_setup_fdt(bootm_headers_t *images) &images->lmb); } -static void boot_prep_linux(bootm_headers_t *images) +static void boot_prep_linux(struct bootm_headers *images) { if (CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && images->ft_len) { boot_reloc_fdt(images); @@ -271,7 +271,7 @@ static void boot_prep_linux(bootm_headers_t *images) } } -static void boot_jump_linux(bootm_headers_t *images) +static void boot_jump_linux(struct bootm_headers *images) { typedef void __noreturn (*kernel_entry_t)(int, ulong, ulong, ulong); kernel_entry_t kernel = (kernel_entry_t) images->ep; @@ -302,7 +302,7 @@ static void boot_jump_linux(bootm_headers_t *images) } int do_bootm_linux(int flag, int argc, char *const argv[], - bootm_headers_t *images) + struct bootm_headers *images) { /* No need for those on MIPS */ if (flag & BOOTM_STATE_OS_BD_T) diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c index fefba12873..4c40bd86fd 100644 --- a/arch/mips/mach-jz47xx/jz4780/jz4780.c +++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c @@ -30,7 +30,7 @@ void board_init_f(ulong dummy) typedef void __noreturn (*image_entry_noargs_t)(void); struct mmc *mmc; unsigned long count; - struct image_header *header; + struct legacy_img_hdr *header; int ret; /* Set global data pointer */ @@ -58,8 +58,8 @@ void board_init_f(ulong dummy) if (ret) hang(); - header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - - sizeof(struct image_header)); + header = (struct legacy_img_hdr *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct legacy_img_hdr)); count = blk_dread(mmc_get_blk_desc(mmc), CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, @@ -76,7 +76,7 @@ void board_init_f(ulong dummy) } #endif /* CONFIG_SPL_BUILD */ -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { return CONFIG_SYS_SDRAM_BASE + (256 * 1024 * 1024); } diff --git a/arch/mips/mach-mtmips/mt7621/spl/spl.c b/arch/mips/mach-mtmips/mt7621/spl/spl.c index 91eebc6c1f..aa5b267bb9 100644 --- a/arch/mips/mach-mtmips/mt7621/spl/spl.c +++ b/arch/mips/mach-mtmips/mt7621/spl/spl.c @@ -64,7 +64,7 @@ void board_boot_order(u32 *spl_boot_list) unsigned long spl_nor_get_uboot_base(void) { const struct tpl_info *tpli; - const image_header_t *hdr; + const struct legacy_img_hdr *hdr; u32 addr; addr = FLASH_MMAP_BASE + TPL_INFO_OFFSET; @@ -72,7 +72,7 @@ unsigned long spl_nor_get_uboot_base(void) if (tpli->magic == TPL_INFO_MAGIC) { addr = FLASH_MMAP_BASE + tpli->size; - hdr = (const image_header_t *)KSEG1ADDR(addr); + hdr = (const struct legacy_img_hdr *)KSEG1ADDR(addr); if (image_get_magic(hdr) == IH_MAGIC) { addr += sizeof(*hdr) + image_get_size(hdr); diff --git a/arch/mips/mach-mtmips/mt7621/tpl/tpl.c b/arch/mips/mach-mtmips/mt7621/tpl/tpl.c index 2a828907a3..d77592da5f 100644 --- a/arch/mips/mach-mtmips/mt7621/tpl/tpl.c +++ b/arch/mips/mach-mtmips/mt7621/tpl/tpl.c @@ -116,7 +116,7 @@ static void mt7621_cache_init(void) void __noreturn tpl_main(void) { - const image_header_t *hdr = (const image_header_t *)__image_copy_end; + const struct legacy_img_hdr *hdr = (const struct legacy_img_hdr *)__image_copy_end; image_entry_noargs_t image_entry; u32 loadaddr, size; uintptr_t data; @@ -132,7 +132,7 @@ void __noreturn tpl_main(void) image_entry = (image_entry_noargs_t)image_get_ep(hdr); /* Load TPL image to L2 cache */ - data = (uintptr_t)__image_copy_end + sizeof(struct image_header); + data = (uintptr_t)__image_copy_end + sizeof(struct legacy_img_hdr); fill_lock_l2cache(data, loadaddr, size); /* Jump to SPL */ diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 4679260f17..9c5789b1c8 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -77,7 +77,7 @@ phys_size_t get_effective_memsize(void) return UBOOT_RAM_SIZE_MAX; } -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { if (IS_ENABLED(CONFIG_RAM_OCTEON)) { /* Map a maximum of 256MiB - return not size but address */ diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index 3cb59bd977..06c094d0f1 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR; #define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */ int do_bootm_linux(int flag, int argc, char *const argv[], - bootm_headers_t *images) + struct bootm_headers *images) { void (*kernel)(int, int, int, char *) = (void *)images->ep; char *commandline = env_get("bootargs"); diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index ab616497fa..e39fe14382 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -312,7 +312,10 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, if (size || memsize > CONFIG_MAX_MEM_MAPPED) { print_size(memsize > CONFIG_MAX_MEM_MAPPED ? memsize - CONFIG_MAX_MEM_MAPPED + size : size, - " left unmapped\n"); + " of DDR memory left unmapped in U-Boot\n"); +#ifndef CONFIG_SPL_BUILD + puts(" "); +#endif } return memsize_in_meg; diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index c8d06b0508..86b08a6174 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -31,7 +31,7 @@ void cpu_init_f(immap_t __iomem *immr) out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE); #endif - WATCHDOG_RESET(); + schedule(); /* SIUMCR - contains debug pin configuration (11-6) */ setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR); diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index e52aa75703..512787854c 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -45,7 +45,7 @@ static void set_clocks_in_mhz (struct bd_info *kbd); #define CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE (768*1024*1024) #endif -static void boot_jump_linux(bootm_headers_t *images) +static void boot_jump_linux(struct bootm_headers *images) { void (*kernel)(struct bd_info *, ulong r4, ulong r5, ulong r6, ulong r7, ulong r8, ulong r9); @@ -84,7 +84,7 @@ static void boot_jump_linux(bootm_headers_t *images) * r9: 0 */ debug(" Booting using OF flat tree...\n"); - WATCHDOG_RESET (); + schedule(); (*kernel) ((struct bd_info *)of_flat_tree, 0, 0, EPAPR_MAGIC, env_get_bootm_mapsize(), 0, 0); /* does not return */ @@ -108,7 +108,7 @@ static void boot_jump_linux(bootm_headers_t *images) struct bd_info *kbd = images->kbd; debug(" Booting using board info...\n"); - WATCHDOG_RESET (); + schedule(); (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end, 0, 0); /* does not return */ @@ -151,7 +151,7 @@ void arch_lmb_reserve(struct lmb *lmb) return ; } -static void boot_prep_linux(bootm_headers_t *images) +static void boot_prep_linux(struct bootm_headers *images) { #ifdef CONFIG_MP /* @@ -163,7 +163,7 @@ static void boot_prep_linux(bootm_headers_t *images) #endif } -static int boot_cmdline_linux(bootm_headers_t *images) +static int boot_cmdline_linux(struct bootm_headers *images) { ulong of_size = images->ft_len; struct lmb *lmb = &images->lmb; @@ -184,7 +184,7 @@ static int boot_cmdline_linux(bootm_headers_t *images) return ret; } -static int boot_bd_t_linux(bootm_headers_t *images) +static int boot_bd_t_linux(struct bootm_headers *images) { ulong of_size = images->ft_len; struct lmb *lmb = &images->lmb; @@ -205,7 +205,7 @@ static int boot_bd_t_linux(bootm_headers_t *images) return ret; } -static int boot_body_linux(bootm_headers_t *images) +static int boot_body_linux(struct bootm_headers *images) { int ret; @@ -224,7 +224,7 @@ static int boot_body_linux(bootm_headers_t *images) } noinline int do_bootm_linux(int flag, int argc, char *const argv[], - bootm_headers_t *images) + struct bootm_headers *images) { int ret; @@ -273,7 +273,7 @@ static void set_clocks_in_mhz (struct bd_info *kbd) } #if defined(CONFIG_BOOTM_VXWORKS) -void boot_prep_vxworks(bootm_headers_t *images) +void boot_prep_vxworks(struct bootm_headers *images) { #if defined(CONFIG_OF_LIBFDT) int off; @@ -305,7 +305,7 @@ void boot_prep_vxworks(bootm_headers_t *images) #endif } -void boot_jump_vxworks(bootm_headers_t *images) +void boot_jump_vxworks(struct bootm_headers *images) { /* PowerPC VxWorks boot interface conforms to the ePAPR standard * general purpuse registers: @@ -319,7 +319,7 @@ void boot_jump_vxworks(bootm_headers_t *images) * r9: 0 * TCR: WRC = 0, no watchdog timer reset will occur */ - WATCHDOG_RESET(); + schedule(); ((void (*)(void *, ulong, ulong, ulong, ulong, ulong, ulong))images->ep)(images->ft_addr, diff --git a/arch/powerpc/lib/cache.c b/arch/powerpc/lib/cache.c index 19162511ce..c4c5c2d451 100644 --- a/arch/powerpc/lib/cache.c +++ b/arch/powerpc/lib/cache.c @@ -13,7 +13,7 @@ static ulong maybe_watchdog_reset(ulong flushed) { flushed += CONFIG_SYS_CACHELINE_SIZE; if (flushed >= CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD) { - WATCHDOG_RESET(); + schedule(); flushed = 0; } return flushed; diff --git a/arch/powerpc/lib/interrupts.c b/arch/powerpc/lib/interrupts.c index 5ba4cd0c13..bdb8030c27 100644 --- a/arch/powerpc/lib/interrupts.c +++ b/arch/powerpc/lib/interrupts.c @@ -81,7 +81,7 @@ void timer_interrupt(struct pt_regs *regs) #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) if (CONFIG_SYS_WATCHDOG_FREQ && (timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) - WATCHDOG_RESET (); + schedule(); #endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ #ifdef CONFIG_LED_STATUS diff --git a/arch/powerpc/lib/ticks.S b/arch/powerpc/lib/ticks.S index c487f938fa..8647d77cc9 100644 --- a/arch/powerpc/lib/ticks.S +++ b/arch/powerpc/lib/ticks.S @@ -9,7 +9,6 @@ #include <ppc_asm.tmpl> #include <ppc_defs.h> #include <config.h> -#include <watchdog.h> /* * unsigned long long get_ticks(void); @@ -42,7 +41,9 @@ wait_ticks: addc r14, r4, r14 /* Compute end time lower */ addze r15, r3 /* and end time upper */ - WATCHDOG_RESET /* Trigger watchdog, if needed */ +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) + bl schedule /* Trigger watchdog, if needed */ +#endif 1: bl get_ticks /* Get current time */ subfc r4, r4, r14 /* Subtract current time from end time */ subfe. r3, r3, r15 diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 78e964db12..32a90b83b5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -269,6 +269,20 @@ config XIP from a NOR flash memory without copying the code to ram. Say yes here if U-Boot boots from flash directly. +config SPL_XIP + bool "Enable XIP mode for SPL" + help + If SPL starts in read-only memory (XIP for example) then we shouldn't + rely on lock variables (for example hart_lottery and available_harts_lock), + this affects only SPL, other stages should proceed as non-XIP. + +config AVAILABLE_HARTS + bool "Send IPI by available harts" + default y + help + By default, IPI sending mechanism will depend on available_harts. + If disable this, it will send IPI by CPUs node numbers of device tree. + config SHOW_REGS bool "Show registers on unhandled exception" diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 3ffcbbd23f..52ab02519f 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -19,15 +19,17 @@ * The variables here must be stored in the data section since they are used * before the bss section is available. */ -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) u32 hart_lottery __section(".data") = 0; +#ifdef CONFIG_AVAILABLE_HARTS /* * The main hart running U-Boot has acquired available_harts_lock until it has * finished initialization of global data. */ u32 available_harts_lock = 1; #endif +#endif static inline bool supports_extension(char ext) { diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c index 1fdc7837b8..44e11bd56c 100644 --- a/arch/riscv/cpu/fu540/dram.c +++ b/arch/riscv/cpu/fu540/dram.c @@ -21,7 +21,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { /* * Ensure that we run from first 4GB so that all diff --git a/arch/riscv/cpu/fu740/dram.c b/arch/riscv/cpu/fu740/dram.c index 1dc77efeca..d6d4a41d25 100644 --- a/arch/riscv/cpu/fu740/dram.c +++ b/arch/riscv/cpu/fu740/dram.c @@ -20,7 +20,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_64BIT /* diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c index 1fdc7837b8..44e11bd56c 100644 --- a/arch/riscv/cpu/generic/dram.c +++ b/arch/riscv/cpu/generic/dram.c @@ -21,7 +21,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { /* * Ensure that we run from first 4GB so that all diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index b7f21ab63e..4687bca3c9 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -122,7 +122,7 @@ call_board_init_f_0: call_harts_early_init: jal harts_early_init -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) /* * Pick hart to initialize global data and run U-Boot. The other harts * wait for initialization to complete. @@ -152,22 +152,24 @@ call_harts_early_init: /* save the boot hart id to global_data */ SREG tp, GD_BOOT_HART(gp) -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) +#ifdef CONFIG_AVAILABLE_HARTS la t0, available_harts_lock amoswap.w.rl zero, zero, 0(t0) +#endif wait_for_gd_init: - la t0, available_harts_lock - li t1, 1 -1: amoswap.w.aq t1, t1, 0(t0) - bnez t1, 1b - /* * Set the global data pointer only when gd_t has been initialized. * This was already set by arch_setup_gd on the boot hart, but all other * harts' global data pointers gets set here. */ mv gp, s0 +#ifdef CONFIG_AVAILABLE_HARTS + la t0, available_harts_lock + li t1, 1 +1: amoswap.w.aq t1, t1, 0(t0) + bnez t1, 1b /* register available harts in the available_harts mask */ li t1, 1 @@ -177,6 +179,7 @@ wait_for_gd_init: SREG t2, GD_AVAILABLE_HARTS(gp) amoswap.w.rl zero, zero, 0(t0) +#endif /* * Continue on hart lottery winner, others branch to diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 095484a635..858594a191 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -27,9 +27,11 @@ struct arch_global_data { #if CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS]; #endif -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) +#ifdef CONFIG_AVAILABLE_HARTS ulong available_harts; #endif +#endif }; #include <asm-generic/global_data.h> diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 5e113ee8c9..68514758a8 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -71,7 +71,7 @@ int riscv_init_ipi(void) continue; /* skip if hart is marked as not available */ - if (!ofnode_is_available(node)) + if (!ofnode_is_enabled(node)) continue; /* read hart ID of CPU */ diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index f1fe089b3d..452dfcea97 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -16,9 +16,11 @@ int main(void) { DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr)); -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) +#ifdef CONFIG_AVAILABLE_HARTS DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts)); #endif +#endif return 0; } diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 670d9c9ebc..f5f8b4c733 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -62,7 +62,7 @@ static void announce_and_cleanup(int fake) cleanup_before_linux(); } -static void boot_prep_linux(bootm_headers_t *images) +static void boot_prep_linux(struct bootm_headers *images) { if (CONFIG_IS_ENABLED(OF_LIBFDT) && CONFIG_IS_ENABLED(LMB) && images->ft_len) { debug("using: FDT\n"); @@ -76,7 +76,7 @@ static void boot_prep_linux(bootm_headers_t *images) } } -static void boot_jump_linux(bootm_headers_t *images, int flag) +static void boot_jump_linux(struct bootm_headers *images, int flag) { void (*kernel)(ulong hart, void *dtb); int fake = (flag & BOOTM_STATE_OS_FAKE_GO); @@ -107,7 +107,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) } int do_bootm_linux(int flag, int argc, char *const argv[], - bootm_headers_t *images) + struct bootm_headers *images) { /* No need for those on RISC-V */ if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE) @@ -129,7 +129,7 @@ int do_bootm_linux(int flag, int argc, char *const argv[], } int do_bootm_vxworks(int flag, int argc, char *const argv[], - bootm_headers_t *images) + struct bootm_headers *images) { return do_bootm_linux(flag, argc, argv, images); } diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index ba992100ad..4f073a016f 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -27,7 +27,7 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) ofnode_for_each_subnode(node, cpus) { /* skip if hart is marked as not available in the device tree */ - if (!ofnode_is_available(node)) + if (!ofnode_is_enabled(node)) continue; /* read hart ID of CPU */ @@ -45,11 +45,13 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) continue; } -#ifndef CONFIG_XIP +#if !CONFIG_IS_ENABLED(XIP) +#ifdef CONFIG_AVAILABLE_HARTS /* skip if hart is not available */ if (!(gd->arch.available_harts & (1 << reg))) continue; #endif +#endif gd->arch.ipi[reg].addr = ipi->addr; gd->arch.ipi[reg].arg0 = ipi->arg0; diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index d077948dd7..636d3545b9 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -3,19 +3,22 @@ * Copyright (c) 2011 The Chromium OS Authors. */ +#define LOG_CATEGORY LOGC_SANDBOX + #include <common.h> #include <bootstage.h> #include <cpu_func.h> #include <errno.h> #include <log.h> -#include <asm/global_data.h> -#include <linux/delay.h> -#include <linux/libfdt.h> #include <os.h> +#include <asm/global_data.h> #include <asm/io.h> #include <asm/malloc.h> #include <asm/setjmp.h> #include <asm/state.h> +#include <dm/ofnode.h> +#include <linux/delay.h> +#include <linux/libfdt.h> DECLARE_GLOBAL_DATA_PTR; @@ -373,3 +376,28 @@ ulong timer_get_boot_us(void) return (count - base_count) / 1000; } + +int sandbox_load_other_fdt(void **fdtp, int *sizep) +{ + const char *orig; + int ret, size; + void *fdt = *fdtp; + + ret = state_load_other_fdt(&orig, &size); + if (ret) { + log_err("Cannot read other FDT\n"); + return log_msg_ret("ld", ret); + } + + if (!*fdtp) { + fdt = os_malloc(size); + if (!fdt) + return log_msg_ret("mem", -ENOMEM); + *sizep = size; + } + + memcpy(fdt, orig, *sizep); + *fdtp = fdt; + + return 0; +} diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index f937991139..d6170adaf5 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -669,6 +669,11 @@ void os_puts(const char *str) os_putc(*str++); } +void os_flush(void) +{ + fflush(stdout); +} + int os_write_ram_buf(const char *fname) { struct sandbox_state *state = state_get_current(); @@ -1012,8 +1017,24 @@ void *os_find_text_base(void) return base; } +/** + * os_unblock_signals() - unblock all signals + * + * If we are relaunching the sandbox in a signal handler, we have to unblock + * the respective signal before calling execv(). See signal(7) man-page. + */ +static void os_unblock_signals(void) +{ + sigset_t sigs; + + sigfillset(&sigs); + sigprocmask(SIG_UNBLOCK, &sigs, NULL); +} + void os_relaunch(char *argv[]) { + os_unblock_signals(); + execv(argv[0], argv); os_exit(1); } diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index fe5d44d36e..1d49a9bd10 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -89,7 +89,7 @@ void spl_board_init(void) int ret; ret = ut_run_list("spl", NULL, tests, count, - state->select_unittests); + state->select_unittests, 1); /* continue execution into U-Boot */ } } diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 90a84e93c7..642be164a3 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -205,21 +205,19 @@ SANDBOX_CMDLINE_OPT_SHORT(default_fdt, 'D', 0, static int sandbox_cmdline_cb_test_fdt(struct sandbox_state *state, const char *arg) { - const char *fmt = "/arch/sandbox/dts/test.dtb"; - char *p; + char buf[256]; char *fname; int len; - len = strlen(state->argv[0]) + strlen(fmt) + 1; + len = state_get_rel_filename("arch/sandbox/dts/test.dtb", buf, + sizeof(buf)); + if (len < 0) + return len; + fname = os_malloc(len); if (!fname) return -ENOMEM; - strcpy(fname, state->argv[0]); - p = strrchr(fname, '/'); - if (!p) - p = fname + strlen(fname); - len -= p - fname; - snprintf(p, len, fmt); + strcpy(fname, buf); state->fdt_fname = fname; return 0; diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index e0d01125bb..fcc4a337e5 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -396,6 +396,54 @@ bool autoboot_set_keyed(bool autoboot_keyed) return old_val; } +int state_get_rel_filename(const char *rel_path, char *buf, int size) +{ + struct sandbox_state *state = state_get_current(); + int rel_len, prog_len; + char *p; + int len; + + rel_len = strlen(rel_path); + p = strrchr(state->argv[0], '/'); + prog_len = p ? p - state->argv[0] : 0; + + /* allow space for a / and a terminator */ + len = prog_len + 1 + rel_len + 1; + if (len > size) + return -ENOSPC; + strncpy(buf, state->argv[0], prog_len); + buf[prog_len] = '/'; + strcpy(buf + prog_len + 1, rel_path); + + return len; +} + +int state_load_other_fdt(const char **bufp, int *sizep) +{ + struct sandbox_state *state = state_get_current(); + char fname[256]; + int len, ret; + + /* load the file if needed */ + if (!state->other_fdt_buf) { + len = state_get_rel_filename("arch/sandbox/dts/other.dtb", + fname, sizeof(fname)); + if (len < 0) + return len; + + ret = os_read_file(fname, &state->other_fdt_buf, + &state->other_size); + if (ret) { + log_err("Cannot read file '%s'\n", fname); + return ret; + } + } + *bufp = state->other_fdt_buf; + *sizep = state->other_size; + + return 0; +} + int state_init(void) { state = &main_state; diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile index 6cbc9bbcaa..b6a88479b2 100644 --- a/arch/sandbox/dts/Makefile +++ b/arch/sandbox/dts/Makefile @@ -5,7 +5,7 @@ dtb-$(CONFIG_SANDBOX) += sandbox64.dtb else dtb-$(CONFIG_SANDBOX) += sandbox.dtb endif -dtb-$(CONFIG_UT_DM) += test.dtb +dtb-$(CONFIG_UT_DM) += test.dtb other.dtb dtb-$(CONFIG_CMD_EXTENSION) += overlay0.dtbo overlay1.dtbo include $(srctree)/scripts/Makefile.dts diff --git a/arch/sandbox/dts/other.dts b/arch/sandbox/dts/other.dts new file mode 100644 index 0000000000..395a792322 --- /dev/null +++ b/arch/sandbox/dts/other.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Other devicetree file for running sandbox tests + * + * This used for tests which want to check they can access multiple device + * trees. This one is loaded and checks are made that it is actually visible. + */ + +/dts-v1/; + +/ { + compatible = "sandbox-other"; + #address-cells = <1>; + #size-cells = <1>; + + node { + target = <&target 3 4>; + + subnode { + compatible = "sandbox-other2"; + str-prop = "other"; + }; + + subnode2 { + }; + }; + + target: target { + compatible = "sandbox-other2"; + #gpio-cells = <2>; + str-prop = "other"; + reg = <0x8000 0x100>; + status = "disabled"; + }; +}; diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index 56e6b38bfa..de7a218f45 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -245,6 +245,10 @@ compatible = "sandbox,sandbox-rng"; }; + scsi { + compatible = "sandbox,scsi"; + }; + sound { compatible = "sandbox,sound"; cpu { diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 2761588f0d..4ee471238e 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -233,6 +233,8 @@ test5-gpios = <&gpio_a 19>; bool-value; + int8-value = /bits/ 8 <0x12>; + int16-value = /bits/ 16 <0x1234>; int-value = <1234>; uint-value = <(-1234)>; int64-value = /bits/ 64 <0x1111222233334444>; @@ -1156,6 +1158,11 @@ backlight = <&backlight 0 100>; }; + scsi { + compatible = "sandbox,scsi"; + sandbox,filepath = "scsi.img"; + }; + smem@0 { compatible = "sandbox,smem"; }; diff --git a/arch/sandbox/include/asm/malloc.h b/arch/sandbox/include/asm/malloc.h index a1467b5ead..8aaaa9cb87 100644 --- a/arch/sandbox/include/asm/malloc.h +++ b/arch/sandbox/include/asm/malloc.h @@ -6,6 +6,7 @@ */ #ifndef __ASM_MALLOC_H +#define __ASM_MALLOC_H void *malloc(size_t size); void free(void *ptr); diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index 07c768ae5d..fd42daad51 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -108,6 +108,9 @@ struct sandbox_state { bool hwspinlock; /* Hardware Spinlock status */ bool allow_memio; /* Allow readl() etc. to work */ + void *other_fdt_buf; /* 'other' FDT blob used by tests */ + int other_size; /* size of other FDT blob */ + /* * This struct is getting large. * @@ -266,6 +269,33 @@ void state_reset_for_test(struct sandbox_state *state); void state_show(struct sandbox_state *state); /** + * state_get_rel_filename() - Get a filename relative to the executable + * + * This uses argv[0] to obtain a filename path + * + * @rel_path: Relative path to build, e.g. "arch/sandbox/dts/test.dtb". Must not + * have a trailing / + * @buf: Buffer to use to return the filename + * @size: Size of buffer + * @return length of filename (including terminator), -ENOSPC if @size is too + * small + */ +int state_get_rel_filename(const char *rel_path, char *buf, int size); + +/** + * state_load_other_fdt() - load the 'other' FDT into a buffer + * + * This loads the other.dtb file into a buffer. This is typically used in tests. + * + * @bufp: Place to put allocated buffer pointer. The buffer is read using + * os_read_file() which calls os_malloc(), so does affect U-Boot's own malloc() + * space + * @sizep: Returns the size of the buffer + * @return 0 if OK, -ve on error + */ +int state_load_other_fdt(const char **bufp, int *sizep); + +/** * Initialize the test system state */ int state_init(void); diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 53a036b3ab..0406085917 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -11,6 +11,8 @@ #include <video.h> #include <pci_ids.h> +struct unit_test_state; + /* The sandbox driver always permits an I2C device with this address */ #define SANDBOX_I2C_TEST_ADDR 0x59 @@ -315,4 +317,21 @@ int sandbox_sdl_set_bpp(struct udevice *dev, enum video_log2_bpp l2bpp); */ void sandbox_set_fake_efi_mgr_dev(struct udevice *dev, bool fake_dev); +/** + * sandbox_load_other_fdt() - load the 'other' FDT into the test state + * + * This copies the other.dtb file into the test state, so that a fresh version + * can be used for a test that is about to run. + * + * If @uts->other_fdt is NULL, as it is when first set up, this allocates a + * buffer for the other FDT and sets @uts->other_fdt_size to its size. + * + * In any case, the other FDT is copied from the sandbox state into + * @uts->other_fdt ready for use. + * + * @uts: Unit test state + * @return 0 if OK, -ve on error + */ +int sandbox_load_other_fdt(void **fdtp, int *sizep); + #endif diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c index d1d460b84a..c1742f94de 100644 --- a/arch/sandbox/lib/bootm.c +++ b/arch/sandbox/lib/bootm.c @@ -50,7 +50,7 @@ int bootz_setup(ulong image, ulong *start, ulong *end) return ret; } -int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) +int do_bootm_linux(int flag, int argc, char *argv[], struct bootm_headers *images) { if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) { bootstage_mark(BOOTSTAGE_ID_RUN_OS); diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index 7ea04442b8..a5fad6c46c 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -40,7 +40,7 @@ static unsigned long sh_check_cmd_arg(char *cmdline, char *key, int base) } int do_bootm_linux(int flag, int argc, char *const argv[], - bootm_headers_t *images) + struct bootm_headers *images) { /* Linux kernel load address */ void (*kernel) (void) = (void (*)(void))images->ep; diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c index c104a849a5..1295121ae5 100644 --- a/arch/x86/cpu/broadwell/sdram.c +++ b/arch/x86/cpu/broadwell/sdram.c @@ -25,7 +25,7 @@ #include <asm/arch/pei_data.h> #include <asm/arch/pm.h> -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { return mrc_common_board_get_usable_ram_top(total_size); } diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index 4a256bad44..f4ee4cdf5d 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -27,7 +27,7 @@ unsigned int install_e820_map(unsigned int max_entries, * address, and how far U-Boot is moved by relocation are set in the global * data structure. */ -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { uintptr_t dest_addr = 0; int i; diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c index b7778565b1..1c28a43778 100644 --- a/arch/x86/cpu/efi/payload.c +++ b/arch/x86/cpu/efi/payload.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; * the relocation address, and how far U-Boot is moved by relocation are * set in the global data structure. */ -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { struct efi_mem_desc *desc, *end; struct efi_entry_memmap *map; diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c index af65982fd0..f3086db42c 100644 --- a/arch/x86/cpu/efi/sdram.c +++ b/arch/x86/cpu/efi/sdram.c @@ -11,7 +11,7 @@ DECLARE_GLOBAL_DATA_PTR; -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { return (ulong)efi_get_ram_base() + gd->ram_size; } diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index a97b0b7ceb..a4918fbad6 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -25,7 +25,7 @@ static const char *const ecc_decoder[] = { "active" }; -ulong mrc_common_board_get_usable_ram_top(ulong total_size) +phys_size_t mrc_common_board_get_usable_ram_top(phys_size_t total_size) { struct memory_info *info = &gd->arch.meminfo; uintptr_t dest_addr = 0; @@ -50,7 +50,7 @@ ulong mrc_common_board_get_usable_ram_top(ulong total_size) dest_addr = largest->start + largest->size; - return (ulong)dest_addr; + return (phys_size_t)dest_addr; } void mrc_common_dram_init_banksize(void) diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index dd6b8753de..1a0ec433e6 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -44,7 +44,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CMOS_OFFSET_MRC_SEED_S3 156 #define CMOS_OFFSET_MRC_SEED_CHK 160 -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { return mrc_common_board_get_usable_ram_top(total_size); } diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c index c174550129..595c397d4a 100644 --- a/arch/x86/cpu/qemu/dram.c +++ b/arch/x86/cpu/qemu/dram.c @@ -71,7 +71,7 @@ int dram_init_banksize(void) * the relocation address, and how far U-Boot is moved by relocation are * set in the global data structure. */ -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { return qemu_get_low_memory_size(); } diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index 2287dce12b..8b1ee2d5ae 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -184,7 +184,7 @@ int dram_init_banksize(void) * the relocation address, and how far U-Boot is moved by relocation are * set in the global data structure. */ -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { return gd->ram_size; } diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c index c6f10e22e3..d748d5c7d4 100644 --- a/arch/x86/cpu/slimbootloader/sdram.c +++ b/arch/x86/cpu/slimbootloader/sdram.c @@ -48,7 +48,7 @@ static struct sbl_memory_map_info *get_memory_map_info(void) * @total_size: The memory size that u-boot occupies * Return: : The top available memory address lower than 4GB */ -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { struct sbl_memory_map_info *data; int i; diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c index afb08476ed..8a4b1c5d2d 100644 --- a/arch/x86/cpu/tangier/sdram.c +++ b/arch/x86/cpu/tangier/sdram.c @@ -204,7 +204,7 @@ unsigned int install_e820_map(unsigned int max_entries, * address, and how far U-Boot is moved by relocation are set in the global * data structure. */ -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { struct sfi_table_simple *sb; struct sfi_mem_entry *mentry; diff --git a/arch/x86/include/asm/mrc_common.h b/arch/x86/include/asm/mrc_common.h index 3d7f00c9f9..a7f260a707 100644 --- a/arch/x86/include/asm/mrc_common.h +++ b/arch/x86/include/asm/mrc_common.h @@ -47,7 +47,7 @@ int mrc_add_memory_area(struct memory_info *info, uint64_t start, * the relocation address, and how far U-Boot is moved by relocation are * set in the global data structure. */ -ulong mrc_common_board_get_usable_ram_top(ulong total_size); +phys_size_t mrc_common_board_get_usable_ram_top(phys_size_t total_size); void mrc_common_dram_init_banksize(void); diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index a1655e1cea..4cf41e9354 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -77,7 +77,7 @@ int x86_cleanup_before_linux(void); void x86_enable_caches(void); void x86_disable_caches(void); int x86_init_cache(void); -ulong board_get_usable_ram_top(ulong total_size); +phys_size_t board_get_usable_ram_top(phys_size_t total_size); int default_print_cpuinfo(void); /* Set up a UART which can be used with printch(), printhex8(), etc. */ diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 1bcdb3e30d..eafcddfa24 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -69,10 +69,10 @@ int arch_fixup_memory_node(void *blob) #endif /* Subcommand: PREP */ -static int boot_prep_linux(bootm_headers_t *images) +static int boot_prep_linux(struct bootm_headers *images) { char *cmd_line_dest = NULL; - image_header_t *hdr; + struct legacy_img_hdr *hdr; int is_zimage = 0; void *data = NULL; size_t len; @@ -201,7 +201,7 @@ int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit) } /* Subcommand: GO */ -static int boot_jump_linux(bootm_headers_t *images) +static int boot_jump_linux(struct bootm_headers *images) { debug("## Transferring control to Linux (at address %08lx, kernel %08lx) ...\n", images->ep, images->os.load); @@ -211,7 +211,7 @@ static int boot_jump_linux(bootm_headers_t *images) } int do_bootm_linux(int flag, int argc, char *const argv[], - bootm_headers_t *images) + struct bootm_headers *images) { /* No need for those on x86 */ if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE) diff --git a/arch/x86/lib/fsp1/fsp_dram.c b/arch/x86/lib/fsp1/fsp_dram.c index cfd9b9f48c..5825221d1e 100644 --- a/arch/x86/lib/fsp1/fsp_dram.c +++ b/arch/x86/lib/fsp1/fsp_dram.c @@ -34,7 +34,7 @@ int dram_init(void) * the relocation address, and how far U-Boot is moved by relocation are * set in the global data structure. */ -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { return fsp_get_usable_lowmem_top(gd->arch.hob_list); } diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c index 42d3892b76..f9ea1ab3ba 100644 --- a/arch/x86/lib/fsp2/fsp_dram.c +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -77,7 +77,7 @@ int dram_init(void) return 0; } -ulong board_get_usable_ram_top(ulong total_size) +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { if (!ll_boot_init()) return gd->ram_size; diff --git a/arch/xtensa/lib/bootm.c b/arch/xtensa/lib/bootm.c index 277af18168..fee3392815 100644 --- a/arch/xtensa/lib/bootm.c +++ b/arch/xtensa/lib/bootm.c @@ -134,7 +134,7 @@ static struct bp_tag *setup_fdt_tag(struct bp_tag *params, void *fdt_start) * Boot Linux. */ -int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) +int do_bootm_linux(int flag, int argc, char *argv[], struct bootm_headers *images) { struct bp_tag *params, *params_start; ulong initrd_start, initrd_end; |