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author | Tom Rini <trini@konsulko.com> | 2022-04-08 13:36:51 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2022-04-08 13:36:51 -0400 |
commit | d46e86d25c2a504b3e2e4ab17d70b2f0be440f34 (patch) | |
tree | 0d66c84d42423b3d82dfc547ba3966c61dcf486e /scripts | |
parent | 909d2120e27964a9cfdc8d254cd8fa5a0e1345a7 (diff) | |
download | u-boot-d46e86d25c2a504b3e2e4ab17d70b2f0be440f34.tar.gz u-boot-d46e86d25c2a504b3e2e4ab17d70b2f0be440f34.tar.bz2 u-boot-d46e86d25c2a504b3e2e4ab17d70b2f0be440f34.zip |
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'scripts')
-rw-r--r-- | scripts/config_whitelist.txt | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 12208c7a2f..3065da78e1 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1,8 +1,6 @@ CONFIG_ARM_GIC_BASE_ADDRESS CONFIG_AUTO_ZRELADDR CONFIG_BOARDDIR -CONFIG_BOARD_SIZE_LIMIT -CONFIG_BOOTROM_ERR_REG CONFIG_BOOTSCRIPT_ADDR CONFIG_BOOTSCRIPT_COPY_RAM CONFIG_BOOTSCRIPT_HDR_ADDR @@ -15,45 +13,18 @@ CONFIG_BS_HDR_ADDR_RAM CONFIG_BS_HDR_SIZE CONFIG_BS_SIZE CONFIG_CHAIN_BOOT_CMD -CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS -CONFIG_CI_UDC_HAS_HOSTPC -CONFIG_CM922T_XA10 -CONFIG_CMDLINE_PS_SUPPORT -CONFIG_CM_INIT -CONFIG_CM_MULTIPLE_SSRAM -CONFIG_CM_REMAP -CONFIG_CM_SPD_DETECT -CONFIG_CM_TCRAM -CONFIG_COMMON_BOOT -CONFIG_CONS_SCIF0 -CONFIG_CONS_SCIF1 -CONFIG_CONS_SCIF2 -CONFIG_CONS_SCIF4 -CONFIG_CQSPI_REF_CLK -CONFIG_CUSTOMER_BOARD_SUPPORT -CONFIG_DCACHE -CONFIG_DEBUG -CONFIG_DEBUG_LED CONFIG_DEFAULT -CONFIG_DEFAULT_IMMR -CONFIG_DESIGNWARE_ETH CONFIG_DFU_ALT CONFIG_DFU_ALT_BOOT_EMMC CONFIG_DFU_ALT_BOOT_SD CONFIG_DFU_ALT_SYSTEM CONFIG_DFU_ENV_SETTINGS -CONFIG_DIMM_SLOTS_PER_CTLR -CONFIG_DISCOVER_PHY CONFIG_DM9000_BASE CONFIG_DM9000_BYTE_SWAPPED CONFIG_DM9000_DEBUG CONFIG_DM9000_NO_SROM CONFIG_DM9000_USE_16BIT -CONFIG_DMA_COHERENT -CONFIG_DMA_COHERENT_SIZE -CONFIG_DP_DDR_CTRL CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR -CONFIG_DP_DDR_NUM_CTRLS CONFIG_DRIVER_DM9000 CONFIG_DSP_CLUSTER_START CONFIG_DWC_AHSATA_BASE_ADDR @@ -151,7 +122,6 @@ CONFIG_FSL_PMIC_BUS CONFIG_FSL_PMIC_CLK CONFIG_FSL_PMIC_CS CONFIG_FSL_PMIC_MODE -CONFIG_FSL_QIXIS CONFIG_FSL_SATA_V2 CONFIG_FSL_SDHC_V2_3 CONFIG_FSL_SERDES @@ -189,7 +159,6 @@ CONFIG_FTWDT010_WATCHDOG CONFIG_GATEWAYIP CONFIG_GLOBAL_TIMER CONFIG_GMII -CONFIG_GREEN_LED CONFIG_G_DNL_THOR_PRODUCT_NUM CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_UMS_PRODUCT_NUM @@ -355,7 +324,6 @@ CONFIG_I2C_MVTWSI_BASE CONFIG_I2C_MVTWSI_BASE0 CONFIG_I2C_MVTWSI_BASE1 CONFIG_I2C_RTC_ADDR -CONFIG_ICACHE CONFIG_ICS307_REFCLK_HZ CONFIG_IDE_PREINIT CONFIG_IMX @@ -561,15 +529,11 @@ CONFIG_PXA_PWR_I2C CONFIG_PXA_STD_I2C CONFIG_PXA_VGA CONFIG_QBMAN_CLK_DIV -CONFIG_QIXIS_I2C_ACCESS CONFIG_RAMBOOT_NAND CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE -CONFIG_RAMDISKFILE CONFIG_RAMDISK_ADDR -CONFIG_RAMDISK_BOOT CONFIG_RD_LVL -CONFIG_RED_LED CONFIG_RESERVED_01_BASE CONFIG_RESERVED_02_BASE CONFIG_RESERVED_03_BASE @@ -629,7 +593,6 @@ CONFIG_SH_ETHER_SH7734_MII CONFIG_SH_ETHER_USE_PORT CONFIG_SH_GPIO_PFC CONFIG_SH_QSPI_BASE -CONFIG_SH_SCIF_CLK_FREQ CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION CONFIG_SKIP_TRUNOFF_WATCHDOG CONFIG_SLIC @@ -943,8 +906,6 @@ CONFIG_SYS_DPAA_DCE CONFIG_SYS_DPAA_FMAN CONFIG_SYS_DPAA_PME CONFIG_SYS_DPAA_RMAN -CONFIG_SYS_DP_DDR_BASE -CONFIG_SYS_DP_DDR_BASE_PHY CONFIG_SYS_DRAM_BASE CONFIG_SYS_DRAM_SIZE CONFIG_SYS_DRAM_TEST @@ -1909,7 +1870,6 @@ CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_UEC_ETH CONFIG_UEC_ETH2 -CONFIG_UPDATEB CONFIG_USART_BASE CONFIG_USART_ID CONFIG_USBD_HS |