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| author | Andrew Bradford <andrew.bradford@kodakalaris.com> | 2015-08-07 08:36:35 -0400 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-08-14 03:24:21 -0600 |
| commit | f3b84a3032dd989a029320d9512846f48276db95 (patch) | |
| tree | 2735ce58ad07f8e8eabc38a9ac7547db50b447e3 /include | |
| parent | 44a8b96f6488bc0392f99e6caa424539813dee20 (diff) | |
| download | u-boot-f3b84a3032dd989a029320d9512846f48276db95.tar.gz u-boot-f3b84a3032dd989a029320d9512846f48276db95.tar.bz2 u-boot-f3b84a3032dd989a029320d9512846f48276db95.zip | |
x86: baytrail: Configure FSP UPD from device tree
Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.
Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.
Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay
Fixed lines >80col
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/fdtdec.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/fdtdec.h b/include/fdtdec.h index eac679e0e3..62acbd0840 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -182,6 +182,8 @@ enum fdt_compat_id { COMPAT_INTEL_PCH, /* Intel PCH */ COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */ COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */ + COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ + COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ COMPAT_COUNT, }; |