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author | Christophe Leroy <christophe.leroy@csgroup.eu> | 2022-10-14 12:54:50 +0200 |
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committer | Christophe Leroy <christophe.leroy@csgroup.eu> | 2023-02-11 08:47:58 +0100 |
commit | dac3c6f625e03be0b5017b0d436c73aeeb1a673e (patch) | |
tree | 933ff2a68dc33211a2e558dc2f082bf6f28c14d7 /include | |
parent | 773ad4ebb1d68471fda34352fce2970352be05a0 (diff) | |
download | u-boot-dac3c6f625e03be0b5017b0d436c73aeeb1a673e.tar.gz u-boot-dac3c6f625e03be0b5017b0d436c73aeeb1a673e.tar.bz2 u-boot-dac3c6f625e03be0b5017b0d436c73aeeb1a673e.zip |
board: cssi: Add new board MCR3000_2G
This adds a new board from CS GROUP. The board is called
MCR3000_2G, and has a CPU board called CMPC885.
That CPU board is shared with another equipment that will
be added in a later patch.
That board stores Ethernet MAC addresses in an EEPROM which
is accessed using SPI bus.
This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
Diffstat (limited to 'include')
-rw-r--r-- | include/configs/cmpc885.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/include/configs/cmpc885.h b/include/configs/cmpc885.h new file mode 100644 index 0000000000..4ce580cd14 --- /dev/null +++ b/include/configs/cmpc885.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 CS Group + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Definitions for initial stack pointer and data area (in DPRAM) */ +#define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) +#define CFG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800) + +/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */ +#define CFG_SYS_SDRAM_BASE 0x00000000 + +/* FLASH Configuration */ +#define CFG_SYS_FLASH_BASE 0x40000000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 24 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_SYS_BOOTMAPSZ (32 << 20) + +/* NAND configuration part */ +#define CFG_SYS_NAND_BASE 0xC0000000 + +#endif /* __CONFIG_H */ |