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authorGreen Wan <green.wan@sifive.com>2021-05-27 06:52:11 -0700
committerLeo Yu-Chi Liang <ycliang@andestech.com>2021-05-31 16:35:54 +0800
commit2113c0045c2abe1fb3bcd709a06968514c1f6407 (patch)
treefa2288bcf0057f9f9797edf43e328f80f2e75a76 /include
parent416395c772018c6bf52aad36aca163115001793f (diff)
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riscv: dts: add fu740 support
Add dts support for fu740. The HiFive Unmatched support is based on fu740 cpu and drivers in following patch set. Signed-off-by: Green Wan <green.wan@sifive.com> [greentime.hu: set fu740 speed to 1.2GHz] Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/sifive-fu740-prci.h25
-rw-r--r--include/dt-bindings/reset/sifive-fu740-prci.h19
2 files changed, 44 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h b/include/dt-bindings/clock/sifive-fu740-prci.h
new file mode 100644
index 0000000000..c1224783c0
--- /dev/null
+++ b/include/dt-bindings/clock/sifive-fu740-prci.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ * Zong Li
+ * Pragnesh Patel
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
+#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
+
+/* Clock indexes for use by Device Tree data and the PRCI driver */
+
+#define PRCI_CLK_COREPLL 0
+#define PRCI_CLK_DDRPLL 1
+#define PRCI_CLK_GEMGXLPLL 2
+#define PRCI_CLK_DVFSCOREPLL 3
+#define PRCI_CLK_HFPCLKPLL 4
+#define PRCI_CLK_CLTXPLL 5
+#define PRCI_CLK_TLCLK 6
+#define PRCI_CLK_PCLK 7
+#define PRCI_CLK_PCIEAUX 8
+
+#endif
diff --git a/include/dt-bindings/reset/sifive-fu740-prci.h b/include/dt-bindings/reset/sifive-fu740-prci.h
new file mode 100644
index 0000000000..02210f4105
--- /dev/null
+++ b/include/dt-bindings/reset/sifive-fu740-prci.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2020-2021 Sifive, Inc.
+ * Author: Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#ifndef __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H
+#define __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H
+
+/* Reset indexes for use by device tree data and the PRCI driver */
+#define PRCI_RST_DDR_CTRL_N 0
+#define PRCI_RST_DDR_AXI_N 1
+#define PRCI_RST_DDR_AHB_N 2
+#define PRCI_RST_DDR_PHY_N 3
+#define PRCI_RST_PCIE_POWER_UP_N 4
+#define PRCI_RST_GEMGXL_N 5
+#define PRCI_RST_CLTX_N 6
+
+#endif