powerpc: mpc824x: remove MPC824X cpu support

All the MPC824X boards are still non-generic boards:
A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Josef Wagner <Wagner@Microsys.de>
Cc: Torsten Demke <torsten.demke@fci.com>
Cc: Jim Thompson <jim@musenki.com>
Cc: Greg Allen <gallen@arlut.utexas.edu>

16 files changed, 2 insertions, 4513 deletions

diff --git a/include/configs/A3000.h b/include/configs/A3000.h
deleted file mode 100644
index 35e3e6fa8b..0000000000
--- a/include/configs/A3000.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * (C) Copyright 2001, 2002, 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* ------------------------------------------------------------------------- */
-/*
- * Configuration settings for the A-3000 board (Artis Microsystems Inc.).
- * http://artismicro.com
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8245		1
-#define CONFIG_A3000		1
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-
-#define CONFIG_BOOTDELAY	5
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#undef CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"A3000> "		/* Monitor Command Prompt	*/
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-
-/* Print Buffer Size
- */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	8		/* Max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_LOAD_ADDR	0x00400000	/* Default load address		*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_HARD_I2C		1		/* To enable I2C support */
-#undef	CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#undef	CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-
-/* #define CONFIG_TULIP */
-/* #define CONFIG_EEPRO100 */
-#define CONFIG_NATSEMI
-
-#define PCI_ENET0_IOADDR		0x80000000
-#define PCI_ENET0_MEMADDR		0x80000000
-#define PCI_ENET1_IOADDR		0x81000000
-#define PCI_ENET1_MEMADDR		0x81000000
-#define PCI_ENET2_IOADDR		0x82000000
-#define PCI_ENET2_MEMADDR		0x82000000
-#define PCI_ENET3_IOADDR		0x83000000
-#define PCI_ENET3_MEMADDR		0x83000000
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE			0x00000000
-
-#define CONFIG_SYS_FLASH_BASE0_PRELIM		0xFF000000	/* FLASH bank on RCS#0 */
-#define CONFIG_SYS_FLASH_BASE1_PRELIM		0xFF000000	/* FLASH bank on RCS#1 */
-#define CONFIG_SYS_FLASH_BASE			CONFIG_SYS_FLASH_BASE0_PRELIM
-#define CONFIG_SYS_FLASH_BANKS			{ CONFIG_SYS_FLASH_BASE0_PRELIM }
-
-/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
- * reset vector is actually located at FFB00100, but the 8245
- * takes care of us.
- */
-#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
-
-#define CONFIG_SYS_EUMB_ADDR	    0xFC000000
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
-
-#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
-
-	/* Maximum amount of RAM.
-	 */
-#define CONFIG_SYS_MAX_RAM_SIZE    0x04000000	/* 0 .. 128 MB of (S)DRAM */
-
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#undef CONFIG_SYS_RAMBOOT
-#else
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4600)
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/* #define CONFIG_SYS_MONITOR_BASE	   CONFIG_SYS_TEXT_BASE */
-#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
-
-	/* Bit-field values for MCCR1.
-	 */
-#define CONFIG_SYS_ROMNAL	    7
-#define CONFIG_SYS_ROMFAL	    11
-#define CONFIG_SYS_DBUS_SIZE	    0x3
-
-	/* Bit-field values for MCCR2.
-	 */
-#define CONFIG_SYS_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
-#define CONFIG_SYS_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
-
-	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
-	 */
-#define CONFIG_SYS_BSTOPRE	    121
-
-	/* Bit-field values for MCCR3.
-	 */
-#define CONFIG_SYS_REFREC	    8	    /* Refresh to activate interval */
-
-	/* Bit-field values for MCCR4.
-	 */
-#define CONFIG_SYS_PRETOACT	    3	    /* Precharge to activate interval FIXME: was 2	*/
-#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
-#define CONFIG_SYS_ACTORW	    3		/* FIXME was 2 */
-#define CONFIG_SYS_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
-#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM	    1
-#define CONFIG_SYS_REGDIMM	    0
-
-#define CONFIG_SYS_PGMAX	    0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
-
-#define CONFIG_SYS_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CONFIG_SYS_BANK0_START	    0x00000000
-#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE    1
-#define CONFIG_SYS_BANK1_START	    0x3ff00000
-#define CONFIG_SYS_BANK1_END	    0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE    0
-#define CONFIG_SYS_BANK2_START	    0x3ff00000
-#define CONFIG_SYS_BANK2_END	    0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE    0
-#define CONFIG_SYS_BANK3_START	    0x3ff00000
-#define CONFIG_SYS_BANK3_END	    0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE    0
-#define CONFIG_SYS_BANK4_START	    0x3ff00000
-#define CONFIG_SYS_BANK4_END	    0x3fffffff
-#define CONFIG_SYS_BANK4_ENABLE    0
-#define CONFIG_SYS_BANK5_START	    0x3ff00000
-#define CONFIG_SYS_BANK5_END	    0x3fffffff
-#define CONFIG_SYS_BANK5_ENABLE    0
-#define CONFIG_SYS_BANK6_START	    0x3ff00000
-#define CONFIG_SYS_BANK6_END	    0x3fffffff
-#define CONFIG_SYS_BANK6_ENABLE    0
-#define CONFIG_SYS_BANK7_START	    0x3ff00000
-#define CONFIG_SYS_BANK7_END	    0x3fffffff
-#define CONFIG_SYS_BANK7_ENABLE    0
-
-#define CONFIG_SYS_ODCR	    0xff
-
-#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* Max number of sectors per flash	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-
-
-	/* Warining: environment is not EMBEDDED in the U-Boot code.
-	 * It's stored in flash separately.
-	 */
-#define CONFIG_ENV_IS_IN_FLASH	    1
-#define CONFIG_ENV_ADDR		0xFFFE0000
-#define CONFIG_ENV_SIZE		0x00020000 /* Size of the Environment		*/
-#define CONFIG_ENV_SECT_SIZE	0x00020000 /* Size of the Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
deleted file mode 100644
index a75c52f2c7..0000000000
--- a/include/configs/CPC45.h
+++ /dev/null
@@ -1,489 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- *
- * Configuration settings for the CPC45 board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8245		1
-#define CONFIG_CPC45		1
-
-#define CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-
-#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#define CONFIG_BOOTDELAY	5
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-
-#if 1
-#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
-
-/* Print Buffer Size
- */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-
-#if defined(CONFIG_BOOT_ROM)
-#define CONFIG_SYS_FLASH_BASE		0xFF000000
-#else
-#define CONFIG_SYS_FLASH_BASE		0xFF800000
-#endif
-
-#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
-
-#define CONFIG_SYS_EUMB_ADDR		0xFCE00000
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM		*/
-
-/* Maximum amount of RAM.
- */
-#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000
-
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#undef CONFIG_SYS_RAMBOOT
-#else
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4600)
-#define DUART_DCR		(CONFIG_SYS_EUMB_ADDR + 0x4511)
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-
-#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR	0x51
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ	33000000
-
-
-/* Bit-field values for MCCR1.
- */
-#define CONFIG_SYS_ROMNAL		0
-#define CONFIG_SYS_ROMFAL		8
-
-#define CONFIG_SYS_BANK0_ROW		0	/* SDRAM bank 7-0 row address */
-#define CONFIG_SYS_BANK1_ROW		0
-#define CONFIG_SYS_BANK2_ROW		0
-#define CONFIG_SYS_BANK3_ROW		0
-#define CONFIG_SYS_BANK4_ROW		0
-#define CONFIG_SYS_BANK5_ROW		0
-#define CONFIG_SYS_BANK6_ROW		0
-#define CONFIG_SYS_BANK7_ROW		0
-
-/* Bit-field values for MCCR2.
- */
-
-#define CONFIG_SYS_REFINT		0x2ec
-
-/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
- */
-#define CONFIG_SYS_BSTOPRE		160
-
-/* Bit-field values for MCCR3.
- */
-#define CONFIG_SYS_REFREC		2	/* Refresh to activate interval		*/
-#define CONFIG_SYS_RDLAT		0	/* Data latancy from read command	*/
-
-/* Bit-field values for MCCR4.
- */
-#define CONFIG_SYS_PRETOACT		2	/* Precharge to activate interval	*/
-#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CONFIG_SYS_SDMODE_CAS_LAT	2	/* SDMODE CAS latancy			*/
-#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
-#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length			*/
-#define CONFIG_SYS_ACTORW		2
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM		0
-#define CONFIG_SYS_REGDIMM		0
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CONFIG_SYS_BANK0_START		0x00000000
-#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE	1
-#define CONFIG_SYS_BANK1_START		0x3ff00000
-#define CONFIG_SYS_BANK1_END		0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE	0
-#define CONFIG_SYS_BANK2_START		0x3ff00000
-#define CONFIG_SYS_BANK2_END		0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE	0
-#define CONFIG_SYS_BANK3_START		0x3ff00000
-#define CONFIG_SYS_BANK3_END		0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE	0
-#define CONFIG_SYS_BANK4_START		0x3ff00000
-#define CONFIG_SYS_BANK4_END		0x3fffffff
-#define CONFIG_SYS_BANK4_ENABLE	0
-#define CONFIG_SYS_BANK5_START		0x3ff00000
-#define CONFIG_SYS_BANK5_END		0x3fffffff
-#define CONFIG_SYS_BANK5_ENABLE	0
-#define CONFIG_SYS_BANK6_START		0x3ff00000
-#define CONFIG_SYS_BANK6_END		0x3fffffff
-#define CONFIG_SYS_BANK6_ENABLE	0
-#define CONFIG_SYS_BANK7_START		0x3ff00000
-#define CONFIG_SYS_BANK7_END		0x3fffffff
-#define CONFIG_SYS_BANK7_ENABLE	0
-
-#define CONFIG_SYS_ODCR		0xff
-#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
-					/* currently accessed page in memory	*/
-					/* see 8240 book for details		*/
-
-#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
-#define INTEL_ID_28F160F3T	0x88F388F3	/*  16M = 1M x 16 top boot sector	*/
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-	/* Warining: environment is not EMBEDDED in the ppcboot code.
-	 * It's stored in flash separately.
-	 */
-#define CONFIG_ENV_IS_IN_FLASH	    1
-
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x7F8000)
-#define CONFIG_ENV_SIZE		0x4000	/* Size of the Environment		*/
-#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning	*/
-#define CONFIG_ENV_SECT_SIZE	0x8000 /* Size of the Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*----------------------------------------------------------------------*/
-/* CPC45 Memory Map							*/
-/*----------------------------------------------------------------------*/
-#define SRAM_BASE	0x80000000	/* SRAM base address		*/
-#define SRAM_END	0x801FFFFF
-#define ST16552_A_BASE	0x80200000	/* ST16552 channel A		*/
-#define ST16552_B_BASE	0x80400000	/* ST16552 channel A		*/
-#define BCSR_BASE	0x80600000	/* board control / status registers */
-#define DISPLAY_BASE	0x80600040	/* DISPLAY base			*/
-#define PCMCIA_MEM_BASE 0x83000000	/* PCMCIA memory window base	*/
-#define PCMCIA_IO_BASE	0xFE000000	/* PCMCIA IO window base	*/
-
-#define	CONFIG_SYS_SRAM_BASE	SRAM_BASE
-#define	CONFIG_SYS_SRAM_SIZE	(SRAM_END - SRAM_BASE + 1)
-
-/*---------------------------------------------------------------------*/
-/* CPC45 Control/Status Registers				       */
-/*---------------------------------------------------------------------*/
-#define IRQ_ENA_1		*((volatile uchar*)(BCSR_BASE + 0x00))
-#define IRQ_STAT_1		*((volatile uchar*)(BCSR_BASE + 0x01))
-#define IRQ_ENA_2		*((volatile uchar*)(BCSR_BASE + 0x02))
-#define IRQ_STAT_2		*((volatile uchar*)(BCSR_BASE + 0x03))
-#define BOARD_CTRL		*((volatile uchar*)(BCSR_BASE + 0x04))
-#define BOARD_STAT		*((volatile uchar*)(BCSR_BASE + 0x05))
-#define WDG_START		*((volatile uchar*)(BCSR_BASE + 0x06))
-#define WDG_PRESTOP		*((volatile uchar*)(BCSR_BASE + 0x06))
-#define WDG_STOP		*((volatile uchar*)(BCSR_BASE + 0x06))
-#define BOARD_REV		*((volatile uchar*)(BCSR_BASE + 0x07))
-
-/* IRQ_ENA_1 bit definitions */
-#define I_ENA_1_IERA	0x80		/* INTA enable			*/
-#define I_ENA_1_IERB	0x40		/* INTB enable			*/
-#define I_ENA_1_IERC	0x20		/* INTC enable			*/
-#define I_ENA_1_IERD	0x10		/* INTD enable			*/
-
-/* IRQ_STAT_1 bit definitions */
-#define I_STAT_1_INTA	0x80		/* INTA status			*/
-#define I_STAT_1_INTB	0x40		/* INTB status			*/
-#define I_STAT_1_INTC	0x20		/* INTC status			*/
-#define I_STAT_1_INTD	0x10		/* INTD status			*/
-
-/* IRQ_ENA_2 bit definitions */
-#define I_ENA_2_IEAB	0x80		/* ABORT IRQ enable		*/
-#define I_ENA_2_IEK1	0x40		/* KEY1 IRQ enable		*/
-#define I_ENA_2_IEK2	0x20		/* KEY2 IRQ enable		*/
-#define I_ENA_2_IERT	0x10		/* RTC IRQ enable		*/
-#define I_ENA_2_IESM	0x08		/* LM81 IRQ enable		*/
-#define I_ENA_2_IEDG	0x04		/* DEGENERATING IRQ enable	*/
-#define I_ENA_2_IES2	0x02		/* ST16552/B IRQ enable		*/
-#define I_ENA_2_IES1	0x01		/* ST16552/A IRQ enable		*/
-
-/* IRQ_STAT_2 bit definitions */
-#define I_STAT_2_ABO	0x80		/* ABORT IRQ status		*/
-#define I_STAT_2_KY1	0x40		/* KEY1 IRQ status		*/
-#define I_STAT_2_KY2	0x20		/* KEY2 IRQ status		*/
-#define I_STAT_2_RTC	0x10		/* RTC IRQ status		*/
-#define I_STAT_2_SMN	0x08		/* LM81 IRQ status		*/
-#define I_STAT_2_DEG	0x04		/* DEGENERATING IRQ status	*/
-#define I_STAT_2_SIO2	0x02		/* ST16552/B IRQ status		*/
-#define I_STAT_2_SIO1	0x01		/* ST16552/A IRQ status		*/
-
-/* BOARD_CTRL bit definitions */
-#define USER_LEDS		2			/* 2 user LEDs	*/
-
-#if (USER_LEDS == 4)
-#define B_CTRL_WRSE		0x80
-#define B_CTRL_KRSE		0x40
-#define B_CTRL_FWRE		0x20		/* Flash write enable		*/
-#define B_CTRL_FWPT		0x10		/* Flash write protect		*/
-#define B_CTRL_LED3		0x08		/* LED 3 control		*/
-#define B_CTRL_LED2		0x04		/* LED 2 control		*/
-#define B_CTRL_LED1		0x02		/* LED 1 control		*/
-#define B_CTRL_LED0		0x01		/* LED 0 control		*/
-#else
-#define B_CTRL_WRSE		0x80
-#define B_CTRL_KRSE		0x40
-#define B_CTRL_FWRE_1		0x20		/* Flash write enable		*/
-#define B_CTRL_FWPT_1		0x10		/* Flash write protect		*/
-#define B_CTRL_LED1		0x08		/* LED 1 control		*/
-#define B_CTRL_LED0		0x04		/* LED 0 control		*/
-#define B_CTRL_FWRE_0		0x02		/* Flash write enable		*/
-#define B_CTRL_FWPT_0		0x01		/* Flash write protect		*/
-#endif
-
-/* BOARD_STAT bit definitions */
-#define B_STAT_WDGE		0x80
-#define B_STAT_WDGS		0x40
-#define B_STAT_WRST		0x20
-#define B_STAT_KRST		0x10
-#define B_STAT_CSW3		0x08		/* sitch bit 3 status		*/
-#define B_STAT_CSW2		0x04		/* sitch bit 2 status		*/
-#define B_STAT_CSW1		0x02		/* sitch bit 1 status		*/
-#define B_STAT_CSW0		0x01		/* sitch bit 0 status		*/
-
-/*---------------------------------------------------------------------*/
-/* Display addresses						       */
-/*---------------------------------------------------------------------*/
-#define DISP_UDC_RAM	(DISPLAY_BASE + 0x08)	/* UDC RAM	       */
-#define DISP_CHR_RAM	(DISPLAY_BASE + 0x18)	/* character Ram       */
-#define DISP_FLASH	(DISPLAY_BASE + 0x20)	/* Flash Ram	       */
-
-#define DISP_UDC_ADR	*((volatile uchar*)(DISPLAY_BASE + 0x00))	/* UDC Address Reg.    */
-#define DISP_CWORD	*((volatile uchar*)(DISPLAY_BASE + 0x10))	/* Control Word Reg.   */
-
-#define DISP_DIG0	*((volatile uchar*)(DISP_CHR_RAM + 0x00))	/* Digit 0 address     */
-#define DISP_DIG1	*((volatile uchar*)(DISP_CHR_RAM + 0x01))	/* Digit 0 address     */
-#define DISP_DIG2	*((volatile uchar*)(DISP_CHR_RAM + 0x02))	/* Digit 0 address     */
-#define DISP_DIG3	*((volatile uchar*)(DISP_CHR_RAM + 0x03))	/* Digit 0 address     */
-#define DISP_DIG4	*((volatile uchar*)(DISP_CHR_RAM + 0x04))	/* Digit 0 address     */
-#define DISP_DIG5	*((volatile uchar*)(DISP_CHR_RAM + 0x05))	/* Digit 0 address     */
-#define DISP_DIG6	*((volatile uchar*)(DISP_CHR_RAM + 0x06))	/* Digit 0 address     */
-#define DISP_DIG7	*((volatile uchar*)(DISP_CHR_RAM + 0x07))	/* Digit 0 address     */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI			/* include pci support			*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_SYS_EARLY_PCI_INIT
-#undef	CONFIG_PCI_PNP
-#undef	CONFIG_PCI_SCAN_SHOW
-
-
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
-
-#define PCI_ENET0_IOADDR	0x82000000
-#define PCI_ENET0_MEMADDR	0x82000000
-#define PCI_PLX9030_IOADDR	0x82100000
-#define PCI_PLX9030_MEMADDR	0x82100000
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_I82365
-
-#define CONFIG_SYS_PCMCIA_MEM_ADDR	PCMCIA_MEM_BASE
-#define CONFIG_SYS_PCMCIA_MEM_SIZE	0x1000
-
-#define CONFIG_PCMCIA_SLOT_A
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
-#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for IDE not supported	*/
-#define	CONFIG_IDE_LED			/* LED   for IDE is  supported	*/
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
-
-#define CONFIG_SYS_ATA_DATA_OFFSET	CONFIG_SYS_PCMCIA_MEM_SIZE
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400)
-
-#define CONFIG_DOS_PARTITION
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/CU824.h b/include/configs/CU824.h
deleted file mode 100644
index dc98a560c8..0000000000
--- a/include/configs/CU824.h
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- *
- * Configuration settings for the CU824 board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8240		1
-#define CONFIG_CU824		1
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-
-#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#define CONFIG_BOOTCOMMAND	"bootm FE020000"	/* autoboot command	*/
-#define CONFIG_BOOTDELAY	5
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-
-#if 1
-#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
-#endif
-
-/* Print Buffer Size
- */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE	    0x00000000
-#define CONFIG_SYS_FLASH_BASE	    0xFF000000
-
-#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
-
-#define CONFIG_SYS_EUMB_ADDR	    0xFCE00000
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
-
-#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
-
-	/* Maximum amount of RAM.
-	 */
-#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000
-
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#undef CONFIG_SYS_RAMBOOT
-#else
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE	4
-
-#define CONFIG_SYS_NS16550_CLK		(14745600 / 2)
-
-#define CONFIG_SYS_NS16550_COM1	0xFE800080
-#define CONFIG_SYS_NS16550_COM2	0xFE8000C0
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33000000
-
-	/* Bit-field values for MCCR1.
-	 */
-#define CONFIG_SYS_ROMNAL	    0
-#define CONFIG_SYS_ROMFAL	    7
-
-	/* Bit-field values for MCCR2.
-	 */
-#define CONFIG_SYS_REFINT	    430	    /* Refresh interval			*/
-
-	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
-	 */
-#define CONFIG_SYS_BSTOPRE	    192
-
-	/* Bit-field values for MCCR3.
-	 */
-#define CONFIG_SYS_REFREC	    2	    /* Refresh to activate interval	*/
-#define CONFIG_SYS_RDLAT	    3	    /* Data latancy from read command	*/
-
-	/* Bit-field values for MCCR4.
-	 */
-#define CONFIG_SYS_PRETOACT	    2	    /* Precharge to activate interval	*/
-#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
-#define CONFIG_SYS_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
-#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
-#define CONFIG_SYS_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
-#define CONFIG_SYS_ACTORW	    2
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CONFIG_SYS_BANK0_START	    0x00000000
-#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE    1
-#define CONFIG_SYS_BANK1_START	    0x3ff00000
-#define CONFIG_SYS_BANK1_END	    0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE    0
-#define CONFIG_SYS_BANK2_START	    0x3ff00000
-#define CONFIG_SYS_BANK2_END	    0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE    0
-#define CONFIG_SYS_BANK3_START	    0x3ff00000
-#define CONFIG_SYS_BANK3_END	    0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE    0
-#define CONFIG_SYS_BANK4_START	    0x3ff00000
-#define CONFIG_SYS_BANK4_END	    0x3fffffff
-#define CONFIG_SYS_BANK4_ENABLE    0
-#define CONFIG_SYS_BANK5_START	    0x3ff00000
-#define CONFIG_SYS_BANK5_END	    0x3fffffff
-#define CONFIG_SYS_BANK5_ENABLE    0
-#define CONFIG_SYS_BANK6_START	    0x3ff00000
-#define CONFIG_SYS_BANK6_END	    0x3fffffff
-#define CONFIG_SYS_BANK6_ENABLE    0
-#define CONFIG_SYS_BANK7_START	    0x3ff00000
-#define CONFIG_SYS_BANK7_END	    0x3fffffff
-#define CONFIG_SYS_BANK7_ENABLE    0
-
-#define CONFIG_SYS_ODCR	    0xff
-
-#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* Max number of flash banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-	/* Warining: environment is not EMBEDDED in the U-Boot code.
-	 * It's stored in flash separately.
-	 */
-#define CONFIG_ENV_IS_IN_FLASH	    1
-#if 0
-#define CONFIG_ENV_ADDR		0xFF008000
-#define CONFIG_ENV_SIZE		0x8000	/* Size of the Environment Sector	*/
-#else
-#define CONFIG_ENV_ADDR		0xFFFC0000
-#define CONFIG_ENV_SIZE		0x4000	/* Size of the Environment		*/
-#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning	*/
-#define CONFIG_ENV_SECT_SIZE	0x40000 /* Size of the Environment Sector	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI			/* include pci support			*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP
-
-
-#define CONFIG_TULIP
-#define CONFIG_TULIP_USE_IO
-
-#define CONFIG_SYS_ETH_DEV_FN	     0x7800
-#define CONFIG_SYS_ETH_IOBASE	     0x00104000
-
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
-#define PCI_ENET0_IOADDR	0x00104000
-#define PCI_ENET0_MEMADDR	0x80000000
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h
deleted file mode 100644
index c5c929002d..0000000000
--- a/include/configs/MUSENKI.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- *
- * Configuration settings for the MUSENKI board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8245		1
-#define CONFIG_MUSENKI		1
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-
-#define CONFIG_BOOTDELAY	5
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#undef CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-
-/* Print Buffer Size
- */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	8		/* Max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI			/* include pci support          */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP
-
-
-#define CONFIG_TULIP
-
-#define PCI_ENET0_IOADDR		0x80000000
-#define PCI_ENET0_MEMADDR		0x80000000
-#define PCI_ENET1_IOADDR		0x81000000
-#define PCI_ENET1_MEMADDR		0x81000000
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE	    0x00000000
-
-#define CONFIG_SYS_FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank on RCS#0 */
-#define CONFIG_SYS_FLASH_BASE1_PRELIM      0xFF000000      /* FLASH bank on RCS#1 */
-#define CONFIG_SYS_FLASH_BASE  CONFIG_SYS_FLASH_BASE0_PRELIM
-
-/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
- * reset vector is actually located at FFB00100, but the 8245
- * takes care of us.
- */
-#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
-
-#define CONFIG_SYS_EUMB_ADDR	    0xFC000000
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
-
-#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
-
-	/* Maximum amount of RAM.
-	 */
-#define CONFIG_SYS_MAX_RAM_SIZE    0x08000000	/* 0 .. 128 MB of (S)DRAM */
-
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#undef CONFIG_SYS_RAMBOOT
-#else
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4600)
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/* #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE */
-#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
-
-	/* Bit-field values for MCCR1.
-	 */
-#define CONFIG_SYS_ROMNAL	    7
-#define CONFIG_SYS_ROMFAL	    11
-#define CONFIG_SYS_DBUS_SIZE       0x3
-
-	/* Bit-field values for MCCR2.
-	 */
-#define CONFIG_SYS_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
-#define CONFIG_SYS_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
-
-	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
-	 */
-#define CONFIG_SYS_BSTOPRE	    121
-
-	/* Bit-field values for MCCR3.
-	 */
-#define CONFIG_SYS_REFREC	    8	    /* Refresh to activate interval */
-
-	/* Bit-field values for MCCR4.
-	 */
-#define CONFIG_SYS_PRETOACT	    3	    /* Precharge to activate interval FIXME: was 2	*/
-#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
-#define CONFIG_SYS_ACTORW	    3		/* FIXME was 2 */
-#define CONFIG_SYS_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
-#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM	    1
-#define CONFIG_SYS_REGDIMM	    0
-
-#define CONFIG_SYS_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
-
-#define CONFIG_SYS_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CONFIG_SYS_BANK0_START	    0x00000000
-#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE    1
-#define CONFIG_SYS_BANK1_START	    0x3ff00000
-#define CONFIG_SYS_BANK1_END	    0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE    0
-#define CONFIG_SYS_BANK2_START	    0x3ff00000
-#define CONFIG_SYS_BANK2_END	    0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE    0
-#define CONFIG_SYS_BANK3_START	    0x3ff00000
-#define CONFIG_SYS_BANK3_END	    0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE    0
-#define CONFIG_SYS_BANK4_START	    0x3ff00000
-#define CONFIG_SYS_BANK4_END	    0x3fffffff
-#define CONFIG_SYS_BANK4_ENABLE    0
-#define CONFIG_SYS_BANK5_START	    0x3ff00000
-#define CONFIG_SYS_BANK5_END	    0x3fffffff
-#define CONFIG_SYS_BANK5_ENABLE    0
-#define CONFIG_SYS_BANK6_START	    0x3ff00000
-#define CONFIG_SYS_BANK6_END	    0x3fffffff
-#define CONFIG_SYS_BANK6_ENABLE    0
-#define CONFIG_SYS_BANK7_START	    0x3ff00000
-#define CONFIG_SYS_BANK7_END	    0x3fffffff
-#define CONFIG_SYS_BANK7_ENABLE    0
-
-#define CONFIG_SYS_ODCR	    0xff
-
-#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* Max number of flash banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	64	/* Max number of sectors per flash	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-
-
-	/* Warining: environment is not EMBEDDED in the U-Boot code.
-	 * It's stored in flash separately.
-	 */
-#define CONFIG_ENV_IS_IN_FLASH	    1
-#define CONFIG_ENV_ADDR		0xFFFF0000
-#define CONFIG_ENV_SIZE		0x00010000 /* Size of the Environment		*/
-#define CONFIG_ENV_SECT_SIZE	0x20000 /* Size of the Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
deleted file mode 100644
index aa2d9c02de..0000000000
--- a/include/configs/MVBLUE.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define MV_VERSION	"v0.2.0"
-
-/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
-#define ERR_NONE		0
-#define ERR_ENV			1
-#define ERR_BOOTM_BADMAGIC	2
-#define ERR_BOOTM_BADCRC	3
-#define ERR_BOOTM_GUNZIP	4
-#define ERR_BOOTP_TIMEOUT	5
-#define ERR_DHCP		6
-#define ERR_TFTP		7
-#define ERR_NOLAN		8
-#define ERR_LANDRV		9
-
-#define CONFIG_BOARD_TYPES	1
-#define MVBLUE_BOARD_BOX	1
-#define MVBLUE_BOARD_LYNX	2
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-#define CONFIG_SYS_LDSCRIPT	"board/mvblue/u-boot.lds"
-
-#if 0
-#define ERR_LED(code)	do { if (code) \
-		*(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
-	else \
-		*(volatile char *)(0xff000003) = ( 1 ); \
-} while(0)
-#else
-#define ERR_LED(code)
-#endif
-
-#define CONFIG_MPC8245		1
-#define CONFIG_MVBLUE		1
-
-#define CONFIG_CLOCKS_IN_MHZ	1
-
-#define CONFIG_BOARD_TYPES	1
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOT_RETRY_TIME	-1
-
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT		\
-	"autoboot in %d seconds (stop with 's')...\n", bootdelay
-#define CONFIG_AUTOBOOT_STOP_STR	"s"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY		60
-
-
-/*
- * Command line configuration.
- */
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_RUN
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_NISDOMAIN
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_TIMEOFFSET
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	16		/* Max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address			*/
-
-#define CONFIG_BOOTCOMMAND	"run nfsboot"
-#define CONFIG_BOOTARGS			"root=/dev/mtdblock5 ro rootfstype=jffs2"
-
-#define CONFIG_NFSBOOTCOMMAND	"bootp; run nfsargs addcons;bootm"
-
-#define CONFIG_EXTRA_ENV_SETTINGS			\
-	"console_nr=0\0"				\
-    "dhcp_client_id=mvBOX-XP\0"				\
-    "dhcp_vendor-class-identifier=mvBOX\0"		\
-    "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
-    "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
-    "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0"	\
-    "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0"	\
-	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-			"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"	\
-	"addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
-    "mv_version=" MV_VERSION "\0"	\
-	"bootretry=30\0"
-
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-
-#define CONFIG_NET_RETRY_COUNT		5
-
-#define CONFIG_TULIP
-#define CONFIG_TULIP_FIX_DAVICOM	1
-#define CONFIG_ETHADDR			b6:b4:45:eb:fb:c0
-
-#define CONFIG_HW_WATCHDOG
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE	    0x00000000
-
-#define CONFIG_SYS_FLASH_BASE      0xFFF00000
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
-#define CONFIG_SYS_EUMB_ADDR	    0xFC000000
-
-#define CONFIG_SYS_MONITOR_LEN     0x00100000
-#define CONFIG_SYS_MALLOC_LEN      (512 << 10) /* Reserve some kB for malloc()  */
-
-#define CONFIG_SYS_MEMTEST_START   0x00100000	/* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END	    0x00800000	/* 1M ... 8M in DRAM		*/
-
-/* Maximum amount of RAM.  */
-#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000	/* 0 .. 256MB of (S)DRAM */
-
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#undef CONFIG_SYS_RAMBOOT
-#else
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_ISA_IO      0xFE000000
-
-/*
- * serial configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE    1
-
-#define CONFIG_SYS_NS16550_CLK     get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1    (CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2    (CONFIG_SYS_EUMB_ADDR + 0x4600)
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33000000
-
-/* Bit-field values for MCCR1.  */
-#define CONFIG_SYS_ROMNAL      7
-#define CONFIG_SYS_ROMFAL      11
-
-/* Bit-field values for MCCR2.  */
-#define CONFIG_SYS_TSWAIT      0x5
-#define CONFIG_SYS_REFINT      430
-
-/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.  */
-#define CONFIG_SYS_BSTOPRE     121
-
-/* Bit-field values for MCCR3.  */
-#define CONFIG_SYS_REFREC      8
-
-/* Bit-field values for MCCR4.  */
-#define CONFIG_SYS_PRETOACT    3
-#define CONFIG_SYS_ACTTOPRE    5
-#define CONFIG_SYS_ACTORW      3
-#define CONFIG_SYS_SDMODE_CAS_LAT  3
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM      1
-#define CONFIG_SYS_REGDIMM     0
-#define CONFIG_SYS_DBUS_SIZE2  1
-#define CONFIG_SYS_SDMODE_WRAP 0
-
-#define CONFIG_SYS_PGMAX       0x32
-#define CONFIG_SYS_SDRAM_DSCD  0x20
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CONFIG_SYS_BANK0_START	    0x00000000
-#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE    1
-#define CONFIG_SYS_BANK1_START     0x3ff00000
-#define CONFIG_SYS_BANK1_END       0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE    0
-#define CONFIG_SYS_BANK2_START     0x3ff00000
-#define CONFIG_SYS_BANK2_END       0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE    0
-#define CONFIG_SYS_BANK3_START     0x3ff00000
-#define CONFIG_SYS_BANK3_END       0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE    0
-#define CONFIG_SYS_BANK4_START     0x3ff00000
-#define CONFIG_SYS_BANK4_END       0x3fffffff
-#define CONFIG_SYS_BANK4_ENABLE    0
-#define CONFIG_SYS_BANK5_START     0x3ff00000
-#define CONFIG_SYS_BANK5_END       0x3fffffff
-#define CONFIG_SYS_BANK5_ENABLE    0
-#define CONFIG_SYS_BANK6_START     0x3ff00000
-#define CONFIG_SYS_BANK6_END       0x3fffffff
-#define CONFIG_SYS_BANK6_ENABLE    0
-#define CONFIG_SYS_BANK7_START     0x3ff00000
-#define CONFIG_SYS_BANK7_END       0x3fffffff
-#define CONFIG_SYS_BANK7_ENABLE    0
-
-#define CONFIG_SYS_ODCR	    0xff
-
-#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#undef  CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS		1	/* Max number of flash banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT		63	/* Max number of sectors per flash	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	12000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
-
-
-#define CONFIG_ENV_IS_IN_FLASH
-
-#define CONFIG_ENV_OFFSET		0x00010000
-#define CONFIG_ENV_SIZE		0x00010000
-#define CONFIG_ENV_SECT_SIZE	0x00010000
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-#endif	/* __CONFIG_H */
diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h
deleted file mode 100644
index 2c0cb89afa..0000000000
--- a/include/configs/Sandpoint8240.h
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8240		1
-#define CONFIG_SANDPOINT	1
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-#define CONFIG_SYS_LDSCRIPT	"board/sandpoint/u-boot.lds"
-
-#if 0
-#define USE_DINK32		1
-#else
-#undef USE_DINK32
-#endif
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		9600
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"net_self=tftp ${kernel_addr} ${bootfile};"			\
-		"tftp ${ramdisk_addr} ${ramdisk};"			\
-		"run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp ${kernel_addr} ${bootfile};"			\
-		"run nfsargs addip;bootm\0"				\
-	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"bootfile=/tftpboot/SP8240/uImage\0"				\
-	"ramdisk=/tftpboot/SP8240/uRamdisk\0"				\
-	"kernel_addr=200000\0"						\
-	"ramdisk_addr=400000\0"						\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_DRAM_SPEED	100		/* MHz				*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI				/* include pci support		*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP
-
-
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
-
-#define PCI_ENET0_IOADDR	0x80000000
-#define PCI_ENET0_MEMADDR	0x80000000
-#define	PCI_ENET1_IOADDR	0x81000000
-#define	PCI_ENET1_MEMADDR	0x81000000
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000
-
-#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
-
-#if defined (USE_DINK32)
-#define CONFIG_SYS_MONITOR_LEN		0x00030000
-#define CONFIG_SYS_MONITOR_BASE	0x00090000
-#define CONFIG_SYS_RAMBOOT		1
-#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-#else
-#undef	CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_MONITOR_LEN		0x00030000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-
-
-#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#endif
-
-#define CONFIG_SYS_FLASH_BASE		0xFFF00000
-#if 0
-#define CONFIG_SYS_FLASH_SIZE		(512 * 1024)	/* sandpoint has tiny eeprom	*/
-#else
-#define CONFIG_SYS_FLASH_SIZE		(1024 * 1024)	/* Unity has onboard 1MByte flash */
-#endif
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
-
-#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
-
-#define CONFIG_SYS_EUMB_ADDR		0xFC000000
-
-#define CONFIG_SYS_ISA_MEM		0xFD000000
-#define CONFIG_SYS_ISA_IO		0xFE000000
-
-#define CONFIG_SYS_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
-#define CONFIG_SYS_FLASH_RANGE_SIZE	0x01000000
-#define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
-#define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C		1		/* To enable I2C support */
-#undef  CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C_SLAVE	0x7F
-#define CONFIG_SYS_I2C_SPEED	400000
-
-#ifdef CONFIG_SYS_I2C_SOFT
-#error "Soft I2C is not configured properly.  Please review!"
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
-#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
-#define I2C_READ		((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
-				else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
-				else    iop->pdat &= ~0x00020000
-#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
-#endif /* CONFIG_SYS_I2C_SOFT */
-
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3	/* write page size		*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec		*/
-
-
-#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-
-/* #define CONFIG_WINBOND_83C553	1	/ *has a winbond bridge			*/
-#define CONFIG_SYS_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
-#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
-#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
-
-#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
-#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-/*
- * NS87308 Configuration
- */
-#define CONFIG_NS87308			/* Nat Semi super-io controller on ISA bus */
-
-#define CONFIG_SYS_NS87308_BADDR_10	1
-
-#define CONFIG_SYS_NS87308_DEVS	( CONFIG_SYS_NS87308_UART1   | \
-				  CONFIG_SYS_NS87308_UART2   | \
-				  CONFIG_SYS_NS87308_POWRMAN | \
-				  CONFIG_SYS_NS87308_RTC_APC )
-
-#undef  CONFIG_SYS_NS87308_PS2MOD
-
-#define CONFIG_SYS_NS87308_CS0_BASE	0x0076
-#define CONFIG_SYS_NS87308_CS0_CONF	0x30
-#define CONFIG_SYS_NS87308_CS1_BASE	0x0075
-#define CONFIG_SYS_NS87308_CS1_CONF	0x30
-#define CONFIG_SYS_NS87308_CS2_BASE	0x0074
-#define CONFIG_SYS_NS87308_CS2_CONF	0x30
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-
-#define CONFIG_SYS_NS16550_CLK		1843200
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
-#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  1
-
-#define CONFIG_SYS_ROMNAL		7	/*rom/flash next access time		*/
-#define CONFIG_SYS_ROMFAL		11	/*rom/flash access time			*/
-
-#define CONFIG_SYS_REFINT	430	/* no of clock cycles between CBR refresh cycles */
-
-/* the following are for SDRAM only*/
-#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
-#define CONFIG_SYS_REFREC		8	/* Refresh to activate interval		*/
-#define CONFIG_SYS_RDLAT		4	/* data latency from read command	*/
-#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
-#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
-#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
-#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
-
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
-
-/* memory bank settings*/
-/*
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CONFIG_SYS_BANK0_START		0x00000000
-#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE	1
-#define CONFIG_SYS_BANK1_START		0x3ff00000
-#define CONFIG_SYS_BANK1_END		0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE	0
-#define CONFIG_SYS_BANK2_START		0x3ff00000
-#define CONFIG_SYS_BANK2_END		0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE	0
-#define CONFIG_SYS_BANK3_START		0x3ff00000
-#define CONFIG_SYS_BANK3_END		0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE	0
-#define CONFIG_SYS_BANK4_START		0x00000000
-#define CONFIG_SYS_BANK4_END		0x00000000
-#define CONFIG_SYS_BANK4_ENABLE	0
-#define CONFIG_SYS_BANK5_START		0x00000000
-#define CONFIG_SYS_BANK5_END		0x00000000
-#define CONFIG_SYS_BANK5_ENABLE	0
-#define CONFIG_SYS_BANK6_START		0x00000000
-#define CONFIG_SYS_BANK6_END		0x00000000
-#define CONFIG_SYS_BANK6_ENABLE	0
-#define CONFIG_SYS_BANK7_START		0x00000000
-#define CONFIG_SYS_BANK7_END		0x00000000
-#define CONFIG_SYS_BANK7_ENABLE	0
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CONFIG_SYS_BANK_ENABLE		0x01
-
-#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
-					/* see 8240 book for bit definitions	*/
-#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
-					/* currently accessed page in memory	*/
-					/* see 8240 book for details		*/
-
-/* SDRAM 0 - 256MB */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#if defined(USE_DINK32)
-#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
-#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
-#else
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#endif
-
-/* PCI memory */
-#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/* values according to the manual */
-
-#define CONFIG_DRAM_50MHZ	1
-#define CONFIG_SDRAM_50MHZ
-
-#undef	NR_8259_INTS
-#define NR_8259_INTS		1
-
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h
deleted file mode 100644
index 2664d5b169..0000000000
--- a/include/configs/Sandpoint8245.h
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8245		1
-#define CONFIG_SANDPOINT	1
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-#define CONFIG_SYS_LDSCRIPT	"board/sandpoint/u-boot.lds"
-
-#if 0
-#define USE_DINK32		1
-#else
-#undef USE_DINK32
-#endif
-
-#define CONFIG_CONS_INDEX     3               /* set to '3' for on-chip DUART */
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_DRAM_SPEED	100		/* MHz				*/
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI				/* include pci support		*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP
-
-
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
-#define CONFIG_NATSEMI
-#define CONFIG_NS8382X
-
-#define PCI_ENET0_IOADDR	0x80000000
-#define PCI_ENET0_MEMADDR	0x80000000
-#define	PCI_ENET1_IOADDR	0x81000000
-#define	PCI_ENET1_MEMADDR	0x81000000
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000
-
-#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
-
-#if defined (USE_DINK32)
-#define CONFIG_SYS_MONITOR_LEN		0x00030000
-#define CONFIG_SYS_MONITOR_BASE	0x00090000
-#define CONFIG_SYS_RAMBOOT		1
-#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-#else
-#undef	CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_MONITOR_LEN		0x00030000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-
-
-#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#endif
-
-#define CONFIG_SYS_FLASH_BASE		0xFFF00000
-#if 0
-#define CONFIG_SYS_FLASH_SIZE		(512 * 1024)	/* sandpoint has tiny eeprom	*/
-#else
-#define CONFIG_SYS_FLASH_SIZE		(1024 * 1024)	/* Unity has onboard 1MByte flash */
-#endif
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
-
-#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
-
-#define CONFIG_SYS_EUMB_ADDR		0xFC000000
-
-#define CONFIG_SYS_ISA_MEM		0xFD000000
-#define CONFIG_SYS_ISA_IO		0xFE000000
-
-#define CONFIG_SYS_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
-#define CONFIG_SYS_FLASH_RANGE_SIZE	0x01000000
-#define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
-#define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C		1		/* To enable I2C support */
-#undef  CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C_SPEED	400000
-#define CONFIG_SYS_I2C_SLAVE	0x7F
-
-#ifdef CONFIG_SYS_I2C_SOFT
-#error "Soft I2C is not configured properly.  Please review!"
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
-#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
-#define I2C_READ		((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
-				else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
-				else    iop->pdat &= ~0x00020000
-#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
-#endif /* CONFIG_SYS_I2C_SOFT */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-
-/* #define CONFIG_WINBOND_83C553	1	/ *has a winbond bridge			*/
-#define CONFIG_SYS_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
-#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
-#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
-
-#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
-#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-/*
- * NS87308 Configuration
- */
-#define CONFIG_NS87308			/* Nat Semi super-io controller on ISA bus */
-
-#define CONFIG_SYS_NS87308_BADDR_10	1
-
-#define CONFIG_SYS_NS87308_DEVS	( CONFIG_SYS_NS87308_UART1   | \
-				  CONFIG_SYS_NS87308_UART2   | \
-				  CONFIG_SYS_NS87308_POWRMAN | \
-				  CONFIG_SYS_NS87308_RTC_APC )
-
-#undef  CONFIG_SYS_NS87308_PS2MOD
-
-#define CONFIG_SYS_NS87308_CS0_BASE	0x0076
-#define CONFIG_SYS_NS87308_CS0_CONF	0x30
-#define CONFIG_SYS_NS87308_CS1_BASE	0x0075
-#define CONFIG_SYS_NS87308_CS1_CONF	0x30
-#define CONFIG_SYS_NS87308_CS2_BASE	0x0074
-#define CONFIG_SYS_NS87308_CS2_CONF	0x30
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-
-#if (CONFIG_CONS_INDEX > 2)
-#define CONFIG_SYS_NS16550_CLK         CONFIG_DRAM_SPEED*1000000
-#else
-#define CONFIG_SYS_NS16550_CLK         1843200
-#endif
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
-#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_EUMB_ADDR + 0x4600)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
-
-#define CONFIG_SYS_ROMNAL		7	/*rom/flash next access time		*/
-#define CONFIG_SYS_ROMFAL		11	/*rom/flash access time			*/
-
-#define CONFIG_SYS_REFINT	430	/* no of clock cycles between CBR refresh cycles */
-
-/* the following are for SDRAM only*/
-#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
-#define CONFIG_SYS_REFREC		8	/* Refresh to activate interval		*/
-#define CONFIG_SYS_RDLAT		4	/* data latency from read command	*/
-#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
-#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
-#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
-#if 0
-#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
-#endif
-
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
-#define CONFIG_SYS_EXTROM 1
-#define CONFIG_SYS_REGDIMM 0
-
-
-/* memory bank settings*/
-/*
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CONFIG_SYS_BANK0_START		0x00000000
-#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE	1
-#define CONFIG_SYS_BANK1_START		0x3ff00000
-#define CONFIG_SYS_BANK1_END		0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE	0
-#define CONFIG_SYS_BANK2_START		0x3ff00000
-#define CONFIG_SYS_BANK2_END		0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE	0
-#define CONFIG_SYS_BANK3_START		0x3ff00000
-#define CONFIG_SYS_BANK3_END		0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE	0
-#define CONFIG_SYS_BANK4_START		0x00000000
-#define CONFIG_SYS_BANK4_END		0x00000000
-#define CONFIG_SYS_BANK4_ENABLE	0
-#define CONFIG_SYS_BANK5_START		0x00000000
-#define CONFIG_SYS_BANK5_END		0x00000000
-#define CONFIG_SYS_BANK5_ENABLE	0
-#define CONFIG_SYS_BANK6_START		0x00000000
-#define CONFIG_SYS_BANK6_END		0x00000000
-#define CONFIG_SYS_BANK6_ENABLE	0
-#define CONFIG_SYS_BANK7_START		0x00000000
-#define CONFIG_SYS_BANK7_END		0x00000000
-#define CONFIG_SYS_BANK7_ENABLE	0
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CONFIG_SYS_BANK_ENABLE		0x01
-
-#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
-					/* see 8240 book for bit definitions	*/
-#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
-					/* currently accessed page in memory	*/
-					/* see 8240 book for details		*/
-
-/* SDRAM 0 - 256MB */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#if defined(USE_DINK32)
-#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
-#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
-#else
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#endif
-
-/* PCI memory */
-#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/* values according to the manual */
-
-#define CONFIG_DRAM_50MHZ	1
-#define CONFIG_SDRAM_50MHZ
-
-#undef	NR_8259_INTS
-#define NR_8259_INTS		1
-
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h
deleted file mode 100644
index 940be1f5d0..0000000000
--- a/include/configs/eXalion.h
+++ /dev/null
@@ -1,433 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/* #define CONFIG_MPC8240	   1 */
-#define CONFIG_MPC8245		1
-#define CONFIG_EXALION		1
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-#if defined (CONFIG_MPC8240)
-    /* #warning	 ---------- eXalion with MPC8240 --------------- */
-#elif defined (CONFIG_MPC8245)
-    /* #warning	 ++++++++++ eXalion with MPC8245 +++++++++++++++ */
-#elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245)
-#error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245)
-#else
-#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-/* older kernels need clock in MHz newer in Hz */
-					/* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz	    */
-#undef CONFIG_CLOCKS_IN_MHZ
-
-#define CONFIG_BOOTDELAY	10
-
-
-						    /*#define CONFIG_DRAM_SPEED	      66   */ /* MHz			     */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_PCI
-
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		1	/* undef to save memory		*/
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
-#define CONFIG_SYS_MAXARGS		8	/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CONFIG_MISC_INIT_R	1
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000	/* 1 GBytes - initdram() will	   */
-					     /* return real value.		*/
-
-#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
-
-#undef	CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	    */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_DATA_SIZE	128
-
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_INIT_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-
-#if defined (CONFIG_MPC8240)
-#define CONFIG_SYS_FLASH_BASE	    0xFFE00000
-#define CONFIG_SYS_FLASH_SIZE	    (2 * 1024 * 1024)	/* onboard 2MByte flash	    */
-#elif defined (CONFIG_MPC8245)
-#define CONFIG_SYS_FLASH_BASE	    0xFFC00000
-#define CONFIG_SYS_FLASH_SIZE	    (4 * 1024 * 1024)	/* onboard 4MByte flash	    */
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SECT_SIZE	0x20000 /* Size of one Flash sector */
-#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE	/* Use one Flash sector for environment	*/
-#define CONFIG_ENV_ADDR		0xFFFC0000
-#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning  */
-
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-#define CONFIG_SYS_ALT_MEMTEST		1	/* use real memory test	    */
-#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on	    */
-#define CONFIG_SYS_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM	    */
-
-#define CONFIG_SYS_EUMB_ADDR		0xFC000000
-
-/* #define CONFIG_SYS_ISA_MEM		   0xFD000000 */
-#define CONFIG_SYS_ISA_IO		0xFE000000
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks	    */
-#define CONFIG_SYS_MAX_FLASH_SECT	64	/* Max number of sectors per flash  */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-
-#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define FLASH_BASE1_PRELIM	0
-
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_FLASH_INCREMENT	0	/* there is only one bank		*/
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware protection		*/
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- */
-#define CONFIG_PCI		1	/* include pci support		*/
-#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#undef	CONFIG_PCI_PNP
-
-
-#define CONFIG_EEPRO100		1
-
-#define PCI_ENET0_MEMADDR	0x80000000	/* Intel 82559ER */
-#define PCI_ENET0_IOADDR	0x80000000
-#define PCI_ENET1_MEMADDR	0x81000000	/* Intel 82559ER */
-#define PCI_ENET1_IOADDR	0x81000000
-#define PCI_ENET2_MEMADDR	0x82000000	/* Broadcom BCM569xx */
-#define PCI_ENET2_IOADDR	0x82000000
-#define PCI_ENET3_MEMADDR	0x83000000	/* Broadcom BCM56xx */
-#define PCI_ENET3_IOADDR	0x83000000
-
-/*-----------------------------------------------------------------------
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550		1
-#define CONFIG_SYS_NS16550_SERIAL	1
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		38400
-
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-
-#if (CONFIG_CONS_INDEX == 1)
-#define CONFIG_SYS_NS16550_CLK		1843200 /* COM1 only !	*/
-#else
-#define CONFIG_SYS_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); })
-#endif
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_ISA_IO + 0x3F8)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_EUMB_ADDR + 0x4600)
-
-/*-----------------------------------------------------------------------
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
-#undef	CONFIG_SYS_I2C_SOFT		/* I2C bit-banged		*/
-#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-
-/*-----------------------------------------------------------------------
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
-#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2	/* for MPC8240 only		*/
-
-				       /*#define CONFIG_133MHZ_DRAM	 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!!    */
-
-#if defined (CONFIG_MPC8245)
-/* Bit-field values for PMCR2.							*/
-#if defined (CONFIG_133MHZ_DRAM)
-#define CONFIG_SYS_DLL_EXTEND		0x80	/* use DLL extended range - 133MHz only */
-#define CONFIG_SYS_PCI_HOLD_DEL	0x20	/* delay and hold timing - 133MHz only	*/
-#endif
-
-/* Bit-field values for MIOCR1.							*/
-#if !defined (CONFIG_133MHZ_DRAM)
-#define CONFIG_SYS_DLL_MAX_DELAY	0x04	/*  longer DLL delay line - 66MHz only	*/
-#endif
-/* Bit-field values for MIOCR2.							*/
-#define CONFIG_SYS_SDRAM_DSCD		0x20	/* SDRAM data in sample clock delay	*/
-					/*	- note bottom 3 bits MUST be 0	*/
-#endif
-
-/* Bit-field values for MCCR1.							*/
-#define CONFIG_SYS_ROMNAL		7	/*rom/flash next access time		*/
-#define CONFIG_SYS_ROMFAL	       11	/*rom/flash access time			*/
-
-/* Bit-field values for MCCR2.							*/
-#define CONFIG_SYS_TSWAIT		0x5	/* Transaction Start Wait States timer	*/
-#if defined (CONFIG_133MHZ_DRAM)
-#define CONFIG_SYS_REFINT		1300	/* no of clock cycles between CBR	*/
-#else  /* refresh cycles */
-#define CONFIG_SYS_REFINT		750
-#endif
-
-/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.		*/
-#if defined (CONFIG_133MHZ_DRAM)
-#define CONFIG_SYS_BSTOPRE		1023
-#else
-#define CONFIG_SYS_BSTOPRE		250
-#endif
-
-/* Bit-field values for MCCR3.							*/
-/* the following are for SDRAM only						*/
-
-#if defined (CONFIG_133MHZ_DRAM)
-#define CONFIG_SYS_REFREC		9	/* Refresh to activate interval		*/
-#else
-#define CONFIG_SYS_REFREC		5	/* Refresh to activate interval		*/
-#endif
-#if defined (CONFIG_MPC8240)
-#define CONFIG_SYS_RDLAT		2	/* data latency from read command	*/
-#endif
-
-/* Bit-field values for MCCR4.	*/
-#if defined (CONFIG_133MHZ_DRAM)
-#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
-#define CONFIG_SYS_ACTTOPRE		7	/* Activate to Precharge interval	*/
-#define CONFIG_SYS_ACTORW		5	/* Activate to R/W			*/
-#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#else
-#if 0
-#define CONFIG_SYS_PRETOACT		2	/* Precharge to activate interval	*/
-#define CONFIG_SYS_ACTTOPRE		3	/* Activate to Precharge interval	*/
-#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
-#define CONFIG_SYS_SDMODE_CAS_LAT	2	/* SDMODE CAS latency			*/
-#endif
-#define CONFIG_SYS_PRETOACT		2	/* Precharge to activate interval	*/
-#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
-#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#endif
-#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
-#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
-#define CONFIG_SYS_REGDIMM		0
-#if defined (CONFIG_MPC8240)
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   0
-#elif defined (CONFIG_MPC8245)
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
-#define CONFIG_SYS_EXTROM		    0
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-
-
-/*-----------------------------------------------------------------------
- memory bank settings
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CONFIG_SYS_BANK0_START		0x00000000
-#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE	1
-#define CONFIG_SYS_BANK1_START		0x3ff00000
-#define CONFIG_SYS_BANK1_END		0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE	0
-#define CONFIG_SYS_BANK2_START		0x3ff00000
-#define CONFIG_SYS_BANK2_END		0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE	0
-#define CONFIG_SYS_BANK3_START		0x3ff00000
-#define CONFIG_SYS_BANK3_END		0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE	0
-#define CONFIG_SYS_BANK4_START		0x00000000
-#define CONFIG_SYS_BANK4_END		0x00000000
-#define CONFIG_SYS_BANK4_ENABLE	0
-#define CONFIG_SYS_BANK5_START		0x00000000
-#define CONFIG_SYS_BANK5_END		0x00000000
-#define CONFIG_SYS_BANK5_ENABLE	0
-#define CONFIG_SYS_BANK6_START		0x00000000
-#define CONFIG_SYS_BANK6_END		0x00000000
-#define CONFIG_SYS_BANK6_ENABLE	0
-#define CONFIG_SYS_BANK7_START		0x00000000
-#define CONFIG_SYS_BANK7_END		0x00000000
-#define CONFIG_SYS_BANK7_ENABLE	0
-
-/*-----------------------------------------------------------------------
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CONFIG_SYS_BANK_ENABLE		0x01
-
-#if defined (CONFIG_MPC8240)
-#define CONFIG_SYS_ODCR		0xDF	/* configures line driver impedances,	*/
-					/* see 8240 book for bit definitions	*/
-#elif defined (CONFIG_MPC8245)
-#if defined (CONFIG_133MHZ_DRAM)
-#define CONFIG_SYS_ODCR		0xFE	/* configures line driver impedances - 133MHz	*/
-#else
-#define CONFIG_SYS_ODCR		0xDE	/* configures line driver impedances - 66MHz	*/
-#endif
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-
-#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
-					/* currently accessed page in memory	*/
-					/* see 8240 book for details		*/
-
-/*-----------------------------------------------------------------------
- * Block Address Translation (BAT) register settings.
- */
-/* SDRAM 0 - 256MB */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-/* PCI memory */
-#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/* values according to the manual */
-#define CONFIG_DRAM_50MHZ	1
-#define CONFIG_SDRAM_50MHZ
-
-#undef	NR_8259_INTS
-#define NR_8259_INTS		1
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- */
-#define CONFIG_SYS_IDE_MAXBUS	    1	/* max. 2 IDE busses	*/
-#define CONFIG_SYS_IDE_MAXDEVICE   (CONFIG_SYS_IDE_MAXBUS*1)	/* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR   CONFIG_SYS_ISA_IO	/* base address */
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0	/* ide0 offste */
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170	/* ide1 offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0	/* data reg offset  */
-#define CONFIG_SYS_ATA_REG_OFFSET  0	/* reg offset */
-#define CONFIG_SYS_ATA_ALT_OFFSET  0x200	/* alternate register offset */
-
-#define CONFIG_ATAPI
-
-#undef	CONFIG_IDE_8xx_DIRECT	/* no pcmcia interface required */
-#undef	CONFIG_IDE_LED		/* no led for ide supported	*/
-#undef	CONFIG_IDE_RESET	/* reset for ide supported...	 */
-#undef	CONFIG_IDE_RESET_ROUTINE	/* with a special reset function */
-
-/*-----------------------------------------------------------------------
- * DISK Partition support
- */
-#define CONFIG_DOS_PARTITION
-
-/*-----------------------------------------------------------------------
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h
deleted file mode 100644
index 5be62ecb2d..0000000000
--- a/include/configs/utx8245.h
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * Gregory E. Allen, gallen@arlut.utexas.edu
- * Matthew E. Karger, karger@arlut.utexas.edu
- * Applied Research Laboratories, The University of Texas at Austin
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- *
- * Configuration settings for the utx8245 board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8245		1
-#define CONFIG_UTX8245		1
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-#define DEBUG				1
-
-#define CONFIG_IDENT_STRING     " [UTX5] "
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		57600
-
-#define CONFIG_BOOTDELAY	2
-#define CONFIG_AUTOBOOT_PROMPT	"autoboot in %d seconds\n", bootdelay
-#define CONFIG_BOOTCOMMAND	"run nfsboot"	/* autoboot command	*/
-#define CONFIG_BOOTARGS		"root=/dev/ram console=ttyS0,57600" /* RAMdisk */
-#define CONFIG_ETHADDR		00:AA:00:14:00:05	/* UTX5 */
-#define CONFIG_SERVERIP		10.8.17.105	/* Spree */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"kernel_addr=FFA00000\0" \
-	"ramdisk_addr=FF800000\0" \
-	"u-boot_startaddr=FFB00000\0" \
-	"u-boot_endaddr=FFB2FFFF\0" \
-	"nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \
-nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \
-	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \
-	"smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \
-	"fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \
-	"nfsboot=run nfsargs;bootm ${kernel_addr}\0" \
-	"ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
-	"smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
-	"fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
-	"update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \
-${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \
-${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\
-protect on ${u-boot_startaddr} ${u-boot_endaddr}"
-
-#define CONFIG_ENV_OVERWRITE
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DATE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#define CONFIG_SYS_CBSIZE	256				/* Console I/O Buffer Size	*/
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
-
-
-/*-----------------------------------------------------------------------
- * PCI configuration
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI				/* include pci support		*/
-#define	CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
-#define CONFIG_EEPRO100_SROM_WRITE
-
-#define PCI_ENET0_IOADDR	0xF0000000
-#define PCI_ENET0_MEMADDR	0xF0000000
-
-#define PCI_FIREWIRE_IOADDR		0xF1000000
-#define PCI_FIREWIRE_MEMADDR	0xF1000000
-/*
-#define PCI_ENET0_IOADDR	0xFE000000
-#define PCI_ENET0_MEMADDR	0x80000000
-
-#define PCI_FIREWIRE_IOADDR	0x81000000
-#define PCI_FIREWIRE_MEMADDR	0x81000000
-*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE	    0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000	/* 256MB  */
-/*#define CONFIG_SYS_VERY_BIG_RAM	1 */
-
-/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
- * is actually located at FFF00100.  Therefore, U-Boot is
- * physically located at 0xFFB0_0000, but is also mirrored at
- * 0xFFF0_0000.
- */
-#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
-
-#define CONFIG_SYS_EUMB_ADDR	    0xFC000000
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
-
-/*#define CONFIG_SYS_DRAM_TEST		1 */
-#define CONFIG_SYS_MEMTEST_START   0x00003000	/* memtest works on	0...256 MB	*/
-#define CONFIG_SYS_MEMTEST_END	    0x0ff8ffa7	/* in SDRAM, skips exception */
-										/* vectors and U-Boot */
-
-
-/*--------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- *------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_DATA_SIZE    128	/* Size in bytes reserved for */
-									/* initial data */
-#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
-#define CONFIG_SYS_INIT_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*--------------------------------------------------------------------
- * NS16550 Configuration
- *------------------------------------------------------------------*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-
-#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2)
-#	define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-#else
-#	define CONFIG_SYS_NS16550_CLK 33000000
-#endif
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4600)
-#define CONFIG_SYS_NS16550_COM3	0xFF000000
-#define CONFIG_SYS_NS16550_COM4	0xFF000008
-
-/*--------------------------------------------------------------------
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- *------------------------------------------------------------------*/
-
-#define CONFIG_SYS_CLK_FREQ  33000000
-
-/*#define CONFIG_SYS_ETH_DEV_FN	     0x7800 */
-/*#define CONFIG_SYS_ETH_IOBASE	     0x00104000 */
-
-/*--------------------------------------------------------------------
- * I2C Configuration
- *------------------------------------------------------------------*/
-#if 1
-#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
-#define CONFIG_SYS_I2C_SPEED		400000
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-#endif
-
-#define CONFIG_RTC_PCF8563	1		/* enable I2C support for */
-									/* Philips PCF8563 RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* Philips PCF8563 RTC address */
-
-/*--------------------------------------------------------------------
- *	Memory Control Configuration Register values
- *	- see sec. 4.12 of MPC8245 UM
- *------------------------------------------------------------------*/
-
-/**** MCCR1 ****/
-#define CONFIG_SYS_ROMNAL	    0
-#define CONFIG_SYS_ROMFAL	    10		/* (tacc=70ns)*mem_freq - 2,
-									mem_freq = 100MHz */
-
-#define CONFIG_SYS_BANK7_ROW	0		/* SDRAM bank 7-0 row address */
-#define CONFIG_SYS_BANK6_ROW	0		/*	bit count */
-#define CONFIG_SYS_BANK5_ROW	0
-#define CONFIG_SYS_BANK4_ROW	0
-#define CONFIG_SYS_BANK3_ROW	0
-#define CONFIG_SYS_BANK2_ROW	0
-#define CONFIG_SYS_BANK1_ROW	2
-#define CONFIG_SYS_BANK0_ROW	2
-
-/**** MCCR2, refresh interval clock cycles ****/
-#define CONFIG_SYS_REFINT	    480	    /* 33 MHz SDRAM clock was 480 */
-
-/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
-#define CONFIG_SYS_BSTOPRE	    1023	/* burst to precharge[0..9], */
-								/* sets open page interval */
-
-/**** MCCR3 ****/
-#define CONFIG_SYS_REFREC	    7	    /* Refresh to activate interval, trc */
-
-/**** MCCR4 ****/
-#define CONFIG_SYS_PRETOACT	    2	    /* trp */
-#define CONFIG_SYS_ACTTOPRE	    7	    /* trcd + (burst length - 1) + trdl */
-#define CONFIG_SYS_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
-#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type, sequential */
-#define CONFIG_SYS_ACTORW		2		/* trcd min */
-#define CONFIG_SYS_DBUS_SIZE2		1		/* set for 8-bit RCS1, clear for 32,64 */
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM	    0			/* we don't need extended ROM space */
-#define CONFIG_SYS_REGDIMM	    0
-
-/* calculate according to formula in sec. 6-22 of 8245 UM */
-#define CONFIG_SYS_PGMAX           50		/* how long the 8245 retains the */
-									/* currently accessed page in memory */
-									/* was 45 */
-
-#define CONFIG_SYS_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note */
-								/* bits 7,6, and 3-0 MUST be 0 */
-
-#if 0
-#define CONFIG_SYS_DLL_MAX_DELAY	0x04
-#else
-#define CONFIG_SYS_DLL_MAX_DELAY	0
-#endif
-#if 0							/* need for 33MHz SDRAM */
-#define CONFIG_SYS_DLL_EXTEND	0x80
-#else
-#define CONFIG_SYS_DLL_EXTEND	0
-#endif
-#define CONFIG_SYS_PCI_HOLD_DEL 0x20
-
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these values to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8245 user manual.
- */
-
-#define CONFIG_SYS_BANK0_START	    0x00000000
-#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE/2 - 1)
-#define CONFIG_SYS_BANK0_ENABLE    1
-#define CONFIG_SYS_BANK1_START	    CONFIG_SYS_MAX_RAM_SIZE/2
-#define CONFIG_SYS_BANK1_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK1_ENABLE    1
-#define CONFIG_SYS_BANK2_START	    0x3ff00000		/* not available in this design */
-#define CONFIG_SYS_BANK2_END	    0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE    0
-#define CONFIG_SYS_BANK3_START	    0x3ff00000
-#define CONFIG_SYS_BANK3_END	    0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE    0
-#define CONFIG_SYS_BANK4_START	    0x3ff00000
-#define CONFIG_SYS_BANK4_END	    0x3fffffff
-#define CONFIG_SYS_BANK4_ENABLE    0
-#define CONFIG_SYS_BANK5_START	    0x3ff00000
-#define CONFIG_SYS_BANK5_END	    0x3fffffff
-#define CONFIG_SYS_BANK5_ENABLE    0
-#define CONFIG_SYS_BANK6_START	    0x3ff00000
-#define CONFIG_SYS_BANK6_END	    0x3fffffff
-#define CONFIG_SYS_BANK6_ENABLE    0
-#define CONFIG_SYS_BANK7_START	    0x3ff00000
-#define CONFIG_SYS_BANK7_END	    0x3fffffff
-#define CONFIG_SYS_BANK7_ENABLE    0
-
-/*--------------------------------------------------------------------*/
-/* 4.4 - Output Driver Control Register */
-/*--------------------------------------------------------------------*/
-#define CONFIG_SYS_ODCR	    0xe5
-
-/*--------------------------------------------------------------------*/
-/* 4.8 - Error Handling Registers */
-/*-------------------------------CONFIG_SYS_SDMODE_BURSTLEN-------------------------------------*/
-#define CONFIG_SYS_ERRENR1	0x11	/* enable SDRAM refresh overflow error */
-
-/* SDRAM 0-256 MB */
-#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-/*#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
-#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in dcache */
-#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-
-#define CONFIG_SYS_IBAT2L  (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U  (CONFIG_SYS_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* PCI memory */
-/*#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
-/*#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */
-
-/*Flash, config addrs, etc. */
-#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE	    0xFF800000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1			/* Max number of flash banks */
-
-/*	NOTE: environment is not EMBEDDED in the u-boot code.
-	It's stored in flash in its own separate sector.  */
-#define CONFIG_ENV_IS_IN_FLASH	    1
-
-#if 1	/* AMD AM29LV033C */
-#define CONFIG_SYS_MAX_FLASH_SECT	64		/* Max number of sectors in one bank */
-#define CONFIG_ENV_ADDR		0xFFBF0000	/* flash sector SA63 */
-#define CONFIG_ENV_SECT_SIZE	(64*1024)	/* Size of the Environment Sector */
-#else	/* AMD AM29LV116D */
-#define CONFIG_SYS_MAX_FLASH_SECT	35	/* Max number of sectors in one bank */
-#define CONFIG_ENV_ADDR		0xFF9FA000	/* flash sector SA33 */
-#define CONFIG_ENV_SECT_SIZE	(8*1024)	/* Size of the Environment Sector */
-#endif /* #if */
-
-#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE		/* Size of the Environment */
-#define CONFIG_ENV_OFFSET		0			/* starting right at the beginning */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#undef CONFIG_SYS_RAMBOOT
-#else
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-#endif	/* __CONFIG_H */
diff --git a/include/mpc824x.h b/include/mpc824x.h
deleted file mode 100644
index 31d6f693da..0000000000
--- a/include/mpc824x.h
+++ /dev/null
@@ -1,523 +0,0 @@
-/*
- * Copyright Rob Taylor, Flying Pig Systems Ltd. 2000.
- * Copyright (C) 2001, James Dougherty, jfd@cs.stanford.edu
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MPC824X_H__
-#define __MPC824X_H__
-
-#include <config.h>
-
-/* CPU Types */
-#define CPU_TYPE_601		0x01		/* PPC 601	 CPU */
-#define CPU_TYPE_602		0x02		/* PPC 602	 CPU */
-#define CPU_TYPE_603		0x03		/* PPC 603	 CPU */
-#define CPU_TYPE_603E		0x06		/* PPC 603e	 CPU */
-#define CPU_TYPE_603P		0x07		/* PPC 603p	 CPU */
-#define CPU_TYPE_604		0x04		/* PPC 604	 CPU */
-#define CPU_TYPE_604E		0x09		/* PPC 604e	 CPU */
-#define CPU_TYPE_604R		0x0a		/* PPC 604r	 CPU */
-#define CPU_TYPE_750		0x08		/* PPC 750	 CPU */
-#define CPU_TYPE_8240		0x81		/* PPC 8240	 CPU */
-#define CPU_TYPE_8245		0x8081		/* PPC 8245/8241 CPU */
-#define _CACHE_ALIGN_SIZE	32		/* cache line size */
-
-/* spr976 - DMISS data tlb miss address register
- * spr977 - DCMP data tlb miss compare register
- * spr978 - HASH1 PTEG1 address register
- * spr980 - HASH2 PTEG2 address register
- * IMISS  - instruction tlb miss address register
- * ICMP	  - instruction TLB mis compare register
- * RPA	  - real page address register
- * HID0	  - hardware implemntation register
- * HID2	  - instruction address breakpoint register
- */
-
-/* Kahlua/MPC8240 defines */
-#define VEN_DEV_ID		0x00021057	/* Vendor and Dev. ID for MPC106 */
-#define KAHLUA_ID		0x00031057	/* Vendor & Dev Id for Kahlua's PCI */
-#define KAHLUA2_ID	        0x00061057      /* 8245 is aka Kahlua-2 */
-#define BMC_BASE		0x80000000	/* Kahlua ID in PCI Memory space */
-#define CHRP_REG_ADDR		0xfec00000	/* MPC107 Config, Map B */
-#define CHRP_REG_DATA		0xfee00000	/* MPC107 Config, Map B */
-#define CHRP_ISA_MEM_PHYS	0xfd000000
-#define CHRP_ISA_MEM_BUS	0x00000000
-#define CHRP_ISA_MEM_SIZE	0x01000000
-#define CHRP_ISA_IO_PHYS	0xfe000000
-#define CHRP_ISA_IO_BUS		0x00000000
-#define CHRP_ISA_IO_SIZE	0x00800000
-#define CHRP_PCI_IO_PHYS	0xfe800000
-#define CHRP_PCI_IO_BUS		0x00800000
-#define CHRP_PCI_IO_SIZE	0x00400000
-#define CHRP_PCI_MEM_PHYS	0x80000000
-#define CHRP_PCI_MEM_BUS	0x80000000
-#define CHRP_PCI_MEM_SIZE	0x7d000000
-#define	CHRP_PCI_MEMORY_PHYS	0x00000000
-#define	CHRP_PCI_MEMORY_BUS	0x00000000
-#define CHRP_PCI_MEMORY_SIZE	0x40000000
-#define PREP_REG_ADDR		0x80000cf8	/* MPC107 Config, Map A */
-#define PREP_REG_DATA		0x80000cfc	/* MPC107 Config, Map A */
-#define PREP_ISA_IO_PHYS	0x80000000
-#define PREP_ISA_IO_BUS		0x00000000
-#define PREP_ISA_IO_SIZE	0x00800000
-#define PREP_PCI_IO_PHYS	0x81000000
-#define PREP_PCI_IO_BUS		0x01000000
-#define PREP_PCI_IO_SIZE	0x3e800000
-#define PREP_PCI_MEM_PHYS	0xc0000000
-#define PREP_PCI_MEM_BUS	0x00000000
-#define PREP_PCI_MEM_SIZE	0x3f000000
-#define	PREP_PCI_MEMORY_PHYS	0x00000000
-#define	PREP_PCI_MEMORY_BUS	0x80000000
-#define	PREP_PCI_MEMORY_SIZE	0x80000000
-#define MPC107_PCI_CMD		0x80000004	/* MPC107 PCI cmd reg */
-#define MPC107_PCI_STAT		0x80000006	/* MPC107 PCI status reg */
-#define PROC_INT1_ADR		0x800000a8	/* MPC107 Processor i/f cfg1 */
-#define PROC_INT2_ADR		0x800000ac	/* MPC107 Processor i/f cfg2 */
-#define MEM_CONT1_ADR		0x800000f0	/* MPC107 Memory control config. 1 */
-#define MEM_CONT2_ADR		0x800000f4	/* MPC107 Memory control config. 2 */
-#define MEM_CONT3_ADR		0x800000f8	/* MPC107 Memory control config. 3 */
-#define MEM_CONT4_ADR		0x800000fc	/* MPC107 Memory control config. 4 */
-#define MEM_ERREN1_ADR		0x800000c0	/* MPC107 Memory error enable 1 */
-#define MEM_START1_ADR		0x80000080	/* MPC107 Memory starting addr */
-#define MEM_START2_ADR		0x80000084	/* MPC107 Memory starting addr-lo */
-#define XMEM_START1_ADR		0x80000088	/* MPC107 Extended mem. start addr-hi*/
-#define XMEM_START2_ADR		0x8000008c	/* MPC107 Extended mem. start addr-lo*/
-#define MEM_END1_ADR		0x80000090	/* MPC107 Memory ending address */
-#define MEM_END2_ADR		0x80000094	/* MPC107 Memory ending addr-lo */
-#define XMEM_END1_ADR		0x80000098	/* MPC107 Extended mem. end addrs-hi */
-#define XMEM_END2_ADR		0x8000009c	/* MPC107 Extended mem. end addrs-lo*/
-#define OUT_DRV_CONT		0x80000073	/* MPC107 Output Driver Control reg */
-#define MEM_EN_ADR		0x800000a0	/* Memory bank enable */
-#define PAGE_MODE		0x800000a3	/* MPC107 Page Mode Counter/Timer */
-
-/*-----------------------------------------------------------------------
- * Exception offsets (PowerPC standard)
- */
-#define EXC_OFF_RESERVED0	0x0000	/* Reserved */
-#define EXC_OFF_SYS_RESET	0x0100	/* System reset */
-#define EXC_OFF_MACH_CHCK	0x0200	/* Machine Check */
-#define EXC_OFF_DATA_STOR	0x0300	/* Data Storage */
-#define EXC_OFF_INS_STOR	0x0400	/* Instruction Storage */
-#define EXC_OFF_EXTERNAL	0x0500	/* External */
-#define EXC_OFF_ALIGN		0x0600	/* Alignment */
-#define EXC_OFF_PROGRAM		0x0700	/* Program */
-#define EXC_OFF_FPUNAVAIL	0x0800	/* Floating-point Unavailable */
-#define EXC_OFF_DECR		0x0900	/* Decrementer */
-#define EXC_OFF_RESERVED1	0x0A00	/* Reserved */
-#define EXC_OFF_RESERVED2	0x0B00	/* Reserved */
-#define EXC_OFF_SYS_CALL	0x0C00	/* System Call */
-#define EXC_OFF_TRACE		0x0D00	/* Trace */
-#define EXC_OFF_FPUNASSIST	0x0E00	/* Floating-point Assist */
-
-	/* 0x0E10 - 0x0FFF are marked reserved in The PowerPC Architecture book */
-	/* these found in DINK code  - may not apply to 8240*/
-#define EXC_OFF_PMI		0x0F00	/* Performance Monitoring Interrupt */
-#define EXC_OFF_VMXUI		0x0F20	/* VMX (AltiVec) Unavailable Interrupt */
-
-	/* 0x1000 - 0x2FFF are implementation specific */
-	/* these found in DINK code  - may not apply to 8240 */
-#define EXC_OFF_ITME		0x1000	/* Instruction Translation Miss Exception */
-#define EXC_OFF_DLTME		0x1100	/* Data Load Translation Miss Exception */
-#define EXC_OFF_DSTME		0x1200	/* Data Store Translation Miss Exception */
-#define EXC_OFF_IABE		0x1300	/* Instruction Addr Breakpoint Exception */
-#define EXC_OFF_SMIE		0x1400	/* System Management Interrupt Exception */
-#define EXC_OFF_JMDDI		0x1600	/* Java Mode denorm detect Interr -- WTF??*/
-#define EXC_OFF_RMTE		0x2000	/* Run Mode or Trace Exception */
-
-#define _START_OFFSET		EXC_OFF_SYS_RESET
-
-#define MAP_A_CONFIG_ADDR_HIGH	0x8000	/* Upper half of CONFIG_ADDR for Map A */
-#define MAP_A_CONFIG_ADDR_LOW	0x0CF8	/* Lower half of CONFIG_ADDR for Map A */
-#define MAP_A_CONFIG_DATA_HIGH	0x8000	/* Upper half of CONFIG_DAT for Map A */
-#define MAP_A_CONFIG_DATA_LOW	0x0CFC	/* Lower half of CONFIG_DAT for Map A */
-#define MAP_B_CONFIG_ADDR_HIGH	0xfec0	/* Upper half of CONFIG_ADDR for Map B */
-#define MAP_B_CONFIG_ADDR_LOW	0x0000	/* Lower half of CONFIG_ADDR for Map B */
-#define MAP_B_CONFIG_DATA_HIGH	0xfee0	/* Upper half of CONFIG_DAT for Map B */
-#define MAP_B_CONFIG_DATA_LOW	0x0000	/* Lower half of CONFIG_DAT for Map B */
-
-
-#if defined(CONFIG_SYS_ADDR_MAP_A)
-#define CONFIG_ADDR_HIGH    MAP_A_CONFIG_ADDR_HIGH  /* Upper half of CONFIG_ADDR */
-#define CONFIG_ADDR_LOW	    MAP_A_CONFIG_ADDR_LOW   /* Lower half of CONFIG_ADDR */
-#define CONFIG_DATA_HIGH    MAP_A_CONFIG_DATA_HIGH  /* Upper half of CONFIG_DAT */
-#define CONFIG_DATA_LOW	    MAP_A_CONFIG_DATA_LOW   /* Lower half of CONFIG_DAT */
-#else /* Assume Map B, default */
-#define CONFIG_ADDR_HIGH    MAP_B_CONFIG_ADDR_HIGH  /* Upper half of CONFIG_ADDR */
-#define CONFIG_ADDR_LOW	    MAP_B_CONFIG_ADDR_LOW   /* Lower half of CONFIG_ADDR */
-#define CONFIG_DATA_HIGH    MAP_B_CONFIG_DATA_HIGH  /* Upper half of CONFIG_DAT */
-#define CONFIG_DATA_LOW	    MAP_B_CONFIG_DATA_LOW   /* Lower half of CONFIG_DAT */
-#endif
-
-#define CONFIG_ADDR	(CONFIG_ADDR_HIGH << 16 | CONFIG_ADDR_LOW)
-
-#define CONFIG_DATA	(CONFIG_DATA_HIGH << 16 | CONFIG_DATA_LOW)
-
-/* Macros to write to config registers. addr should be a constant in all cases */
-
-#define CONFIG_WRITE_BYTE( addr, data ) \
-  __asm__ __volatile__( \
-  " stwbrx %1, 0, %0\n \
-    sync\n \
-    stb %3, %4(%2)\n \
-    sync " \
-  : /* no output */ \
-  : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
-    "b" (CONFIG_DATA), "r" (data), \
-    "n" ((addr) & 3));
-
-#define CONFIG_WRITE_HALFWORD( addr, data ) \
-  __asm__ __volatile__( \
-  " stwbrx %1, 0, %0\n \
-    sync\n \
-    sthbrx %3, %4, %2\n \
-    sync " \
-  : /* no output */ \
-  : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
-    "r" (CONFIG_DATA), "r" (data), \
-    "b" ((addr) & 3));
-
-/* this assumes it's writeing on word boundaries*/
-#define CONFIG_WRITE_WORD( addr, data ) \
-  __asm__ __volatile__( \
-  " stwbrx %1, 0, %0\n \
-    sync\n \
-    stwbrx %3, 0, %2\n \
-    sync " \
-  : /* no output */ \
-  : "r" (CONFIG_ADDR), "r" (addr), \
-    "r" (CONFIG_DATA), "r" (data));
-
-/* Configuration register reads*/
-
-#define CONFIG_READ_BYTE( addr, reg ) \
-  __asm__ ( \
-  " stwbrx %1, 0, %2\n \
-    sync\n \
-    lbz	  %0, %4(%3)\n \
-    sync " \
-  : "=r" (reg) \
-  : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
-    "b" (CONFIG_DATA), "n" ((addr) & 3));
-
-
-#define CONFIG_READ_HALFWORD( addr, reg ) \
-  __asm__ ( \
-  " stwbrx %1, 0, %2\n \
-    sync\n \
-    lhbrx %0, %4, %3\n \
-    sync " \
-  : "=r" (reg) \
-  : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
-    "r" (CONFIG_DATA), \
-    "b" ((addr) & 3));
-
-/* this assumes it's reading on word boundaries*/
-#define CONFIG_READ_WORD( addr, reg ) \
-  __asm__ ( \
-  " stwbrx %1, 0, %2\n \
-    sync\n \
-    lwbrx %0, 0, %3\n \
-    sync " \
-  : "=r" (reg) \
-  : "r" (addr), "r" (CONFIG_ADDR),\
-    "r" (CONFIG_DATA));
-
-/*
- *  configuration register 'addresses'.
- *  These are described in chaper 5 of the 8240 users manual.
- *  Where the register has an abreviation in the manual, this has
- *  been usaed here, otherwise a name in keeping with the norm has
- *  been invented.
- *  Note that some of these registers aren't documented in the manual.
- */
-
-#define PCICR		0x80000004  /* PCI Command Register */
-#define PCISR		0x80000006  /* PCI Status Register */
-#define REVID		0x80000008  /* CPU revision id */
-#define PIR		0x80000009  /* PCI Programming Interface Register */
-#define PBCCR		0x8000000b  /* PCI Base Class Code Register */
-#define PCLSR		0x8000000c  /* Processor Cache Line Size Register */
-#define PLTR		0x8000000d  /* PCI Latancy Timer Register */
-#define PHTR		0x8000000e  /* PCI Header Type Register */
-#define BISTCTRL	0x8000000f  /* BIST Control */
-#define LMBAR		0x80000010  /* Local Base Address Register */
-#define PCSRBAR		0x80000014  /* PCSR Base Address Register */
-#define ILR		0x8000003c  /* PCI Interrupt Line Register */
-#define IPR		0x8000003d  /* Interrupt Pin Register */
-#define MINGNT		0x8000003e  /* MIN GNI */
-#define MAXLAT		0x8000003f  /* MAX LAT */
-#define PCIACR		0x80000046  /* PCI Arbiter Control Register */
-#define PMCR1		0x80000070  /* Power management config. 1 */
-#define PMCR2		0x80000072  /* Power management config. 2 */
-#define ODCR		0x80000073  /* Output Driver Control Register */
-#define CLKDCR		0x80000074  /* CLK Driver Control Register */
-#if defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
-#define MIOCR1		0x80000076  /* Miscellaneous I/O Control Register 1 */
-#define MIOCR2		0x80000077  /* Miscellaneous I/O Control Register 2 */
-#endif
-#define EUMBBAR		0x80000078  /* Embedded Utilities Memory Block Base Address Register */
-#define EUMBBAR_VAL	0x80500000  /* PCI Relocation offset for EUMB region */
-#define EUMBSIZE	0x00100000  /* Size of EUMB region */
-
-#define MSAR1		0x80000080  /* Memory Starting Address Register 1 */
-#define MSAR2		0x80000084  /* Memory Starting Address Register 2 */
-#define EMSAR1		0x80000088  /* Extended Memory Starting Address Register 1*/
-#define EMSAR2		0x8000008c  /* Extended Memory Starting Address Register 2*/
-#define MEAR1		0x80000090  /* Memory Ending Address Register 1 */
-#define MEAR2		0x80000094  /* Memory Ending Address Register 2 */
-#define EMEAR1		0x80000098  /* Extended Memory Ending Address Register 1 */
-#define EMEAR2		0x8000009c  /* Extended Memory Ending Address Register 2 */
-#define MBER		0x800000a0  /* Memory bank Enable Register*/
-#define MPMR		0x800000a3  /* Memory Page Mode Register (stores PGMAX) */
-#define PICR1		0x800000a8  /* Processor Interface Configuration Register 1 */
-#define PICR2		0x800000ac  /* Processor Interface Configuration Register 2 */
-#define ECCSBECR	0x800000b8  /* ECC Single-Bit Error Counter Register */
-#define ECCSBETR	0x800000b8  /* ECC Single-Bit Error Trigger Register */
-#define ERRENR1		0x800000c0  /* Error Enableing Register 1 */
-#define ERRENR2		0x800000c4  /* Error Enableing Register 2 */
-#define ERRDR1		0x800000c1  /* Error Detection Register 1 */
-#define IPBESR		0x800000c3  /* Internal Processor Error Status Register */
-#define ERRDR2		0x800000c5  /* Error Detection Register 2 */
-#define PBESR		0x800000c7  /* PCI Bus Error Status Register */
-#define PBEAR		0x800000c8  /* Processor/PCI Bus Error Status Register */
-#define AMBOR		0x800000e0  /* Address Map B Options Register */
-#define PCMBCR		0x800000e1  /* PCI/Memory Buffer Configuration */
-#define MCCR1		0x800000f0  /* Memory Control Configuration Register 1 */
-#define MCCR2		0x800000f4  /* Memory Control Configuration Register 2 */
-#define MCCR3		0x800000f8  /* Memory Control Configuration Register 3 */
-#define MCCR4		0x800000fc  /* Memory Control Configuration Register 4 */
-
-/* some values for some of the above */
-
-#define PICR1_CF_APARK		0x00000008
-#define PICR1_LE_MODE		0x00000020
-#define PICR1_ST_GATH_EN	0x00000040
-#if defined(CONFIG_MPC8240)
-#define PICR1_EN_PCS		0x00000080 /* according to dink code, sets the 8240 to handle pci config space */
-#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
-#define PICR1_NO_BUSW_CK	0x00000080 /* no bus width check for flash writes */
-#define PICR1_DEC		0x00000100 /* Time Base enable on 8245/8241 */
-#define ERCR1		        0x800000d0  /* Extended ROM Configuration Register 1 */
-#define ERCR2		        0x800000d4  /* Extended ROM Configuration Register 2 */
-#define ERCR3		        0x800000d8  /* Extended ROM Configuration Register 3 */
-#define ERCR4		        0x800000dc  /* Extended ROM Configuration Register 4 */
-#define MIOCR1		        0x80000076  /* Miscellaneous I/O Control Register 1 */
-#define MIOCR1_ADR_X	        0x80000074  /* Miscellaneous I/O Control Register 1 */
-#define MIOCR1_SHIFT	        2
-#define MIOCR2		        0x80000077  /* Miscellaneous I/O Control Register 2 */
-#define MIOCR2_ADR_X	        0x80000074  /* Miscellaneous I/O Control Register 1 */
-#define MIOCR2_SHIFT	        3
-#define ODCR_ADR_X	        0x80000070	/* Output Driver Control register */
-#define ODCR_SHIFT              3
-#define PMCR2_ADR	        0x80000072	/* Power Mgmnt Cfg 2 register */
-#define PMCR2_ADR_X	        0x80000070
-#define PMCR2_SHIFT             3
-#define PMCR1_ADR	        0x80000070	/* Power Mgmnt Cfg 1 reister */
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-#define PICR1_CF_DPARK		0x00000200
-#define PICR1_MCP_EN		0x00000800
-#define PICR1_FLASH_WR_EN	0x00001000
-#ifdef CONFIG_MPC8240
-#define PICR1_ADDRESS_MAP	0x00010000
-#define PIRC1_MSK		0xff000000
-#endif
-#define PICR1_PROC_TYPE_MSK	0x00060000
-#define PICR1_PROC_TYPE_603E	0x00040000
-#define PICR1_RCS0		0x00100000
-
-#define PICR2_CF_SNOOP_WS_MASK	0x000c0000
-#define PICR2_CF_SNOOP_WS_0WS	0x00000000
-#define PICR2_CF_SNOOP_WS_1WS	0x00040000
-#define PICR2_CF_SNOOP_WS_2WS	0x00080000
-#define PICR2_CF_SNOOP_WS_3WS	0x000c0000
-#define PICR2_CF_APHASE_WS_MASK 0x0000000c
-#define PICR2_CF_APHASE_WS_0WS	0x00000000
-#define PICR2_CF_APHASE_WS_1WS	0x00000004
-#define PICR2_CF_APHASE_WS_2WS	0x00000008
-#define PICR2_CF_APHASE_WS_3WS	0x0000000c
-
-#define MCCR1_ROMNAL_SHIFT	28
-#define MCCR1_ROMNAL_MSK	0xf0000000
-#define MCCR1_ROMFAL_SHIFT	23
-#define MCCR1_ROMFAL_MSK	0x0f800000
-#define MCCR1_DBUS_SIZE0        0x00400000
-#define MCCR1_BURST		0x00100000
-#define MCCR1_MEMGO		0x00080000
-#define MCCR1_SREN		0x00040000
-#if defined(CONFIG_MPC8240)
-#define MCCR1_RAM_TYPE		0x00020000
-#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
-#define MCCR1_SDRAM_EN		0x00020000
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-#define MCCR1_PCKEN		0x00010000
-#define MCCR1_BANK1ROW_SHIFT	2
-#define MCCR1_BANK2ROW_SHIFT	4
-#define MCCR1_BANK3ROW_SHIFT	6
-#define MCCR1_BANK4ROW_SHIFT	8
-#define MCCR1_BANK5ROW_SHIFT	10
-#define MCCR1_BANK6ROW_SHIFT	12
-#define MCCR1_BANK7ROW_SHIFT	14
-
-#define MCCR2_TS_WAIT_TIMER_MSK 0xe0000000
-#define MCCR2_TS_WAIT_TIMER_SHIFT 29
-#define MCCR2_ASRISE_MSK	0x1e000000
-#define MCCR2_ASRISE_SHIFT	25
-#define MCCR2_ASFALL_MSK	0x01e00000
-#define MCCR2_ASFALL_SHIFT	21
-
-#define MCCR2_INLINE_PAR_NOT_ECC    0x00100000
-#define MCCR2_WRITE_PARITY_CHK	0x00080000
-#define MCCR2_INLFRD_PARECC_CHK_EN  0x00040000
-#ifdef CONFIG_MPC8240
-#define MCCR2_ECC_EN		0x00020000
-#define MCCR2_EDO		0x00010000
-#endif
-#define MCCR2_REFINT_MSK	0x0000fffc
-#define MCCR2_REFINT_SHIFT	2
-#define MCCR2_RSV_PG		0x00000002
-#define MCCR2_PMW_PAR		0x00000001
-
-#define MCCR3_BSTOPRE2TO5_MSK	0xf0000000 /*BSTOPRE[2-5]*/
-#define MCCR3_BSTOPRE2TO5_SHIFT 28
-#define MCCR3_REFREC_MSK	0x0f000000
-#define MCCR3_REFREC_SHIFT	24
-#ifdef CONFIG_MPC8240
-#define MCCR3_RDLAT_MSK		0x00f00000
-#define MCCR3_RDLAT_SHIFT	20
-#define MCCR3_CPX		0x00010000
-#define MCCR3_RAS6P_MSK		0x00078000
-#define MCCR3_RAS6P_SHIFT	15
-#define MCCR3_CAS5_MSK		0x00007000
-#define MCCR3_CAS5_SHIFT	12
-#define MCCR3_CP4_MSK		0x00000e00
-#define MCCR3_CP4_SHIFT		9
-#define MCCR3_CAS3_MSK		0x000001c0
-#define MCCR3_CAS3_SHIFT	6
-#define MCCR3_RCD2_MSK		0x00000038
-#define MCCR3_RCD2_SHIFT	3
-#define MCCR3_RP1_MSK		0x00000007
-#define MCCR3_RP1_SHIFT		0
-#endif
-
-#define MCCR4_PRETOACT_MSK	0xf0000000
-#define MCCR4_PRETOACT_SHIFT	28
-#define MCCR4_ACTTOPRE_MSK	0x0f000000
-#define MCCR4_ACTTOPRE_SHIFT	24
-#define MCCR4_WMODE		0x00800000
-#define MCCR4_INLINE		0x00400000
-#if defined(CONFIG_MPC8240)
-#define MCCR4_BIT21		0x00200000 /* this include cos DINK code sets it- unknown function*/
-#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
-#define MCCR4_EXTROM		0x00200000 /* enables Extended ROM space */
-#else
-#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
-#endif
-#define MCCR4_REGISTERED	0x00100000
-#define MCCR4_BSTOPRE0TO1_MSK	0x000c0000 /*BSTOPRE[0-1]*/
-#define MCCR4_BSTOPRE0TO1_SHIFT 18
-#define MCCR4_REGDIMM		0x00008000
-#define MCCR4_SDMODE_MSK	0x00007f00
-#define MCCR4_SDMODE_SHIFT	8
-#define MCCR4_ACTTORW_MSK	0x000000f0
-#define MCCR4_ACTTORW_SHIFT	4
-#define MCCR4_BSTOPRE6TO9_MSK	0x0000000f /*BSTOPRE[6-9]*/
-#define MCCR4_BSTOPRE6TO9_SHIFT 0
-#define MCCR4_DBUS_SIZE2_SHIFT	17
-
-#define MICR_ADDR_MASK		0x0ff00000
-#define MICR_ADDR_SHIFT		20
-#define MICR_EADDR_MASK		0x30000000
-#define MICR_EADDR_SHIFT	28
-
-/*eumb and epic config*/
-
-#define EPIC_FPR		0x00041000
-#define EPIC_GCR		0x00041020
-#define EPIC_EICR		0x00041030
-#define EPIC_EVI		0x00041080
-#define EPIC_PI			0x00041090
-#define EPIC_SVR		0x000410E0
-#define EPIC_TFRR		0x000410F0
-
-/*
- * Note the information for these is rather mangled in the 8240 manual.
- * These are guesses.
- */
-
-#define EPIC_GTCCR0		0x00041100
-#define EPIC_GTCCR1		0x00041140
-#define EPIC_GTCCR2		0x00041180
-#define EPIC_GTCCR3		0x000411C0
-#define EPIC_GTBCR0		0x00041110
-#define EPIC_GTBCR1		0x00041150
-#define EPIC_GTBCR2		0x00041190
-#define EPIC_GTBCR3		0x000411D0
-#define EPIC_GTVPR0		0x00041120
-#define EPIC_GTVPR1		0x00041160
-#define EPIC_GTVPR2		0x000411a0
-#define EPIC_GTVPR3		0x000411e0
-#define EPIC_GTDR0		0x00041130
-#define EPIC_GTDR1		0x00041170
-#define EPIC_GTDR2		0x000411b0
-#define EPIC_GTDR3		0x000411f0
-
-#define EPIC_IVPR0		0x00050200
-#define EPIC_IVPR1		0x00050220
-#define EPIC_IVPR2		0x00050240
-#define EPIC_IVPR3		0x00050260
-#define EPIC_IVPR4		0x00050280
-
-#define EPIC_SVPR0		0x00050200
-#define EPIC_SVPR1		0x00050220
-#define EPIC_SVPR2		0x00050240
-#define EPIC_SVPR3		0x00050260
-#define EPIC_SVPR4		0x00050280
-#define EPIC_SVPR5		0x000502A0
-#define EPIC_SVPR6		0x000502C0
-#define EPIC_SVPR7		0x000502E0
-#define EPIC_SVPR8		0x00050300
-#define EPIC_SVPR9		0x00050320
-#define EPIC_SVPRa		0x00050340
-#define EPIC_SVPRb		0x00050360
-#define EPIC_SVPRc		0x00050380
-#define EPIC_SVPRd		0x000503A0
-#define EPIC_SVPRe		0x000503C0
-#define EPIC_SVPRf		0x000503E0
-
-/* MPC8240 Byte Swap/PCI Support Macros */
-#define BYTE_SWAP_16_BIT(x)    ( (((x) & 0x00ff) << 8) | ( (x) >> 8) )
-#define LONGSWAP(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
-		     (((x) & 0x00ff0000) >>  8) | (((x) & 0xff000000) >> 24) )
-#define PCISWAP(x)   LONGSWAP(x)
-
-#ifndef __ASSEMBLY__
-
-/*
- * MPC107 Support
- *
- */
-unsigned int mpc824x_mpc107_getreg(unsigned int regNum);
-void mpc824x_mpc107_setreg(unsigned int regNum, unsigned int regVal);
-void mpc824x_mpc107_write8(unsigned int address, unsigned char data);
-void mpc824x_mpc107_write16(unsigned int address, unsigned short data);
-void mpc824x_mpc107_write32(unsigned int address, unsigned int data);
-unsigned char mpc824x_mpc107_read8(unsigned int address);
-unsigned short mpc824x_mpc107_read16(unsigned int address);
-unsigned int mpc824x_mpc107_read32(unsigned int address);
-unsigned int mpc824x_eummbar_read(unsigned int regNum);
-void mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal);
-
-#ifdef CONFIG_PCI
-struct pci_controller;
-void pci_cpm824x_init(struct pci_controller* hose);
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __MPC824X_H__ */
diff --git a/include/pci.h b/include/pci.h
index 216f4489e5..7f67ca6542 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -670,10 +670,6 @@ extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
 const char * pci_class_str(u8 class);
 int pci_last_busno(void);
 
-#ifdef CONFIG_MPC824X
-extern void pci_mpc824x_init (struct pci_controller *hose);
-#endif
-
 #ifdef CONFIG_MPC85xx
 extern void pci_mpc85xx_init (struct pci_controller *hose);
 #endif
diff --git a/include/pcmcia/cirrus.h b/include/pcmcia/cirrus.h
deleted file mode 100644
index cd34dd8560..0000000000
--- a/include/pcmcia/cirrus.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * cirrus.h 1.4 1999/10/25 20:03:34
- *
- * The contents of this file are subject to the Mozilla Public License
- * Version 1.1 (the "License"); you may not use this file except in
- * compliance with the License. You may obtain a copy of the License
- * at http://www.mozilla.org/MPL/
- *
- * Software distributed under the License is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
- * the License for the specific language governing rights and
- * limitations under the License.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in which
- * case the provisions of the GPL are applicable instead of the
- * above.  If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use
- * your version of this file under the MPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL.  If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the MPL or the GPL.
- */
-
-#ifndef _LINUX_CIRRUS_H
-#define _LINUX_CIRRUS_H
-
-#ifndef PCI_VENDOR_ID_CIRRUS
-#define PCI_VENDOR_ID_CIRRUS		0x1013
-#endif
-#ifndef PCI_DEVICE_ID_CIRRUS_6729
-#define PCI_DEVICE_ID_CIRRUS_6729	0x1100
-#endif
-#ifndef PCI_DEVICE_ID_CIRRUS_6832
-#define PCI_DEVICE_ID_CIRRUS_6832	0x1110
-#endif
-
-#define PD67_MISC_CTL_1		0x16	/* Misc control 1 */
-#define PD67_FIFO_CTL		0x17	/* FIFO control */
-#define PD67_MISC_CTL_2		0x1E	/* Misc control 2 */
-#define PD67_CHIP_INFO		0x1f	/* Chip information */
-#define PD67_ATA_CTL		0x026	/* 6730: ATA control */
-#define PD67_EXT_INDEX		0x2e	/* Extension index */
-#define PD67_EXT_DATA		0x2f	/* Extension data */
-
-/* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
-#define PD67_DATA_MASK0		0x01	/* Data mask 0 */
-#define PD67_DATA_MASK1		0x02	/* Data mask 1 */
-#define PD67_DMA_CTL		0x03	/* DMA control */
-
-/* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
-#define PD67_EXT_CTL_1		0x03	/* Extension control 1 */
-#define PD67_MEM_PAGE(n)	((n)+5)	/* PCI window bits 31:24 */
-#define PD67_EXTERN_DATA	0x0a
-#define PD67_MISC_CTL_3		0x25
-#define PD67_SMB_PWR_CTL	0x26
-
-/* I/O window address offset */
-#define PD67_IO_OFF(w)		(0x36+((w)<<1))
-
-/* Timing register sets */
-#define PD67_TIME_SETUP(n)	(0x3a + 3*(n))
-#define PD67_TIME_CMD(n)	(0x3b + 3*(n))
-#define PD67_TIME_RECOV(n)	(0x3c + 3*(n))
-
-/* Flags for PD67_MISC_CTL_1 */
-#define PD67_MC1_5V_DET		0x01	/* 5v detect */
-#define PD67_MC1_MEDIA_ENA	0x01	/* 6730: Multimedia enable */
-#define PD67_MC1_VCC_3V		0x02	/* 3.3v Vcc */
-#define PD67_MC1_PULSE_MGMT	0x04
-#define PD67_MC1_PULSE_IRQ	0x08
-#define PD67_MC1_SPKR_ENA	0x10
-#define PD67_MC1_INPACK_ENA	0x80
-
-/* Flags for PD67_FIFO_CTL */
-#define PD67_FIFO_EMPTY		0x80
-
-/* Flags for PD67_MISC_CTL_2 */
-#define PD67_MC2_FREQ_BYPASS	0x01
-#define PD67_MC2_DYNAMIC_MODE	0x02
-#define PD67_MC2_SUSPEND	0x04
-#define PD67_MC2_5V_CORE	0x08
-#define PD67_MC2_LED_ENA	0x10	/* IRQ 12 is LED enable */
-#define PD67_MC2_FAST_PCI	0x10	/* 6729: PCI bus > 25 MHz */
-#define PD67_MC2_3STATE_BIT7	0x20	/* Floppy change bit */
-#define PD67_MC2_DMA_MODE	0x40
-#define PD67_MC2_IRQ15_RI	0x80	/* IRQ 15 is ring enable */
-
-/* Flags for PD67_CHIP_INFO */
-#define PD67_INFO_SLOTS		0x20	/* 0 = 1 slot, 1 = 2 slots */
-#define PD67_INFO_CHIP_ID	0xc0
-#define PD67_INFO_REV		0x1c
-
-/* Fields in PD67_TIME_* registers */
-#define PD67_TIME_SCALE		0xc0
-#define PD67_TIME_SCALE_1	0x00
-#define PD67_TIME_SCALE_16	0x40
-#define PD67_TIME_SCALE_256	0x80
-#define PD67_TIME_SCALE_4096	0xc0
-#define PD67_TIME_MULT		0x3f
-
-/* Fields in PD67_DMA_CTL */
-#define PD67_DMA_MODE		0xc0
-#define PD67_DMA_OFF		0x00
-#define PD67_DMA_DREQ_INPACK	0x40
-#define PD67_DMA_DREQ_WP	0x80
-#define PD67_DMA_DREQ_BVD2	0xc0
-#define PD67_DMA_PULLUP		0x20	/* Disable socket pullups? */
-
-/* Fields in PD67_EXT_CTL_1 */
-#define PD67_EC1_VCC_PWR_LOCK	0x01
-#define PD67_EC1_AUTO_PWR_CLEAR	0x02
-#define PD67_EC1_LED_ENA	0x04
-#define PD67_EC1_INV_CARD_IRQ	0x08
-#define PD67_EC1_INV_MGMT_IRQ	0x10
-#define PD67_EC1_PULLUP_CTL	0x20
-
-/* Fields in PD67_MISC_CTL_3 */
-#define PD67_MC3_IRQ_MASK	0x03
-#define PD67_MC3_IRQ_PCPCI	0x00
-#define PD67_MC3_IRQ_EXTERN	0x01
-#define PD67_MC3_IRQ_PCIWAY	0x02
-#define PD67_MC3_IRQ_PCI	0x03
-#define PD67_MC3_PWR_MASK	0x0c
-#define PD67_MC3_PWR_SERIAL	0x00
-#define PD67_MC3_PWR_TI2202	0x08
-#define PD67_MC3_PWR_SMB	0x0c
-
-/* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */
-
-/* PD6832 extension registers -- indexed in PD67_EXT_INDEX */
-#define PD68_EXT_CTL_2			0x0b
-#define PD68_PCI_SPACE			0x22
-#define PD68_PCCARD_SPACE		0x23
-#define PD68_WINDOW_TYPE		0x24
-#define PD68_EXT_CSC			0x2e
-#define PD68_MISC_CTL_4			0x2f
-#define PD68_MISC_CTL_5			0x30
-#define PD68_MISC_CTL_6			0x31
-
-/* Extra flags in PD67_MISC_CTL_3 */
-#define PD68_MC3_HW_SUSP		0x10
-#define PD68_MC3_MM_EXPAND		0x40
-#define PD68_MC3_MM_ARM			0x80
-
-/* Bridge Control Register */
-#define  PD6832_BCR_MGMT_IRQ_ENA	0x0800
-
-/* Socket Number Register */
-#define PD6832_SOCKET_NUMBER		0x004c	/* 8 bit */
-
-
-typedef struct cirrus_state_t {
-    u_char		misc1, misc2;
-    u_char		timer[6];
-} cirrus_state_t;
-
-/* Cirrus options */
-static int has_dma = -1;
-static int has_led = -1;
-static int has_ring = -1;
-static int dynamic_mode = 0;
-static int freq_bypass = -1;
-#ifdef CONFIG_CPC45
-static int setup_time = 2;
-static int cmd_time = 6;
-static int recov_time = 1;
-#else
-static int setup_time = -1;
-static int cmd_time = -1;
-static int recov_time = -1;
-#endif
-
-
-#endif /* _LINUX_CIRRUS_H */
diff --git a/include/pcmcia/i82365.h b/include/pcmcia/i82365.h
deleted file mode 100644
index 0b432a80ba..0000000000
--- a/include/pcmcia/i82365.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * i82365.h 1.21 2001/08/24 12:15:33
- *
- * The contents of this file are subject to the Mozilla Public License
- * Version 1.1 (the "License"); you may not use this file except in
- * compliance with the License. You may obtain a copy of the License
- * at http://www.mozilla.org/MPL/
- *
- * Software distributed under the License is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
- * the License for the specific language governing rights and
- * limitations under the License.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in
- * which case the provisions of the GPL are applicable instead of the
- * above.  If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use
- * your version of this file under the MPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL.  If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the MPL or the GPL.
- */
-
-#ifndef _LINUX_I82365_H
-#define _LINUX_I82365_H
-
-/* register definitions for the Intel 82365SL PCMCIA controller */
-
-/* Offsets for PCIC registers */
-#define I365_IDENT	0x00	/* Identification and revision */
-#define I365_STATUS	0x01	/* Interface status */
-#define I365_POWER	0x02	/* Power and RESETDRV control */
-#define I365_INTCTL	0x03	/* Interrupt and general control */
-#define I365_CSC	0x04	/* Card status change */
-#define I365_CSCINT	0x05	/* Card status change interrupt control */
-#define I365_ADDRWIN	0x06	/* Address window enable */
-#define I365_IOCTL	0x07	/* I/O control */
-#define I365_GENCTL	0x16	/* Card detect and general control */
-#define I365_GBLCTL	0x1E	/* Global control register */
-
-/* Offsets for I/O and memory window registers */
-#define I365_IO(map)	(0x08+((map)<<2))
-#define I365_MEM(map)	(0x10+((map)<<3))
-#define I365_W_START	0
-#define I365_W_STOP	2
-#define I365_W_OFF	4
-
-/* Flags for I365_STATUS */
-#define I365_CS_BVD1	0x01
-#define I365_CS_STSCHG	0x01
-#define I365_CS_BVD2	0x02
-#define I365_CS_SPKR	0x02
-#define I365_CS_DETECT	0x0C
-#define I365_CS_WRPROT	0x10
-#define I365_CS_READY	0x20	/* Inverted */
-#define I365_CS_POWERON	0x40
-#define I365_CS_GPI	0x80
-
-/* Flags for I365_POWER */
-#define I365_PWR_OFF	0x00	/* Turn off the socket */
-#define I365_PWR_OUT	0x80	/* Output enable */
-#define I365_PWR_NORESET 0x40	/* Disable RESETDRV on resume */
-#define I365_PWR_AUTO	0x20	/* Auto pwr switch enable */
-#define I365_VCC_MASK	0x18	/* Mask for turning off Vcc */
-/* There are different layouts for B-step and DF-step chips: the B
-   step has independent Vpp1/Vpp2 control, and the DF step has only
-   Vpp1 control, plus 3V control */
-#define I365_VCC_5V	0x10	/* Vcc = 5.0v */
-#define I365_VCC_3V	0x18	/* Vcc = 3.3v */
-#define I365_VPP2_MASK	0x0c	/* Mask for turning off Vpp2 */
-#define I365_VPP2_5V	0x04	/* Vpp2 = 5.0v */
-#define I365_VPP2_12V	0x08	/* Vpp2 = 12.0v */
-#define I365_VPP1_MASK	0x03	/* Mask for turning off Vpp1 */
-#define I365_VPP1_5V	0x01	/* Vpp2 = 5.0v */
-#define I365_VPP1_12V	0x02	/* Vpp2 = 12.0v */
-
-/* Flags for I365_INTCTL */
-#define I365_RING_ENA	0x80
-#define I365_PC_RESET	0x40
-#define I365_PC_IOCARD	0x20
-#define I365_INTR_ENA	0x10
-#define I365_IRQ_MASK	0x0F
-
-/* Flags for I365_CSC and I365_CSCINT*/
-#define I365_CSC_BVD1	0x01
-#define I365_CSC_STSCHG	0x01
-#define I365_CSC_BVD2	0x02
-#define I365_CSC_READY	0x04
-#define I365_CSC_DETECT	0x08
-#define I365_CSC_ANY	0x0F
-#define I365_CSC_GPI	0x10
-
-/* Flags for I365_ADDRWIN */
-#define I365_ADDR_MEMCS16	0x20
-#define I365_ENA_IO(map)	(0x40 << (map))
-#define I365_ENA_MEM(map)	(0x01 << (map))
-
-/* Flags for I365_IOCTL */
-#define I365_IOCTL_MASK(map)	(0x0F << (map<<2))
-#define I365_IOCTL_WAIT(map)	(0x08 << (map<<2))
-#define I365_IOCTL_0WS(map)	(0x04 << (map<<2))
-#define I365_IOCTL_IOCS16(map)	(0x02 << (map<<2))
-#define I365_IOCTL_16BIT(map)	(0x01 << (map<<2))
-
-/* Flags for I365_GENCTL */
-#define I365_CTL_16DELAY	0x01
-#define I365_CTL_RESET		0x02
-#define I365_CTL_GPI_ENA	0x04
-#define I365_CTL_GPI_CTL	0x08
-#define I365_CTL_RESUME		0x10
-#define I365_CTL_SW_IRQ		0x20
-
-/* Flags for I365_GBLCTL */
-#define I365_GBL_PWRDOWN	0x01
-#define I365_GBL_CSC_LEV	0x02
-#define I365_GBL_WRBACK		0x04
-#define I365_GBL_IRQ_0_LEV	0x08
-#define I365_GBL_IRQ_1_LEV	0x10
-
-/* Flags for memory window registers */
-#define I365_MEM_16BIT	0x8000	/* In memory start high byte */
-#define I365_MEM_0WS	0x4000
-#define I365_MEM_WS1	0x8000	/* In memory stop high byte */
-#define I365_MEM_WS0	0x4000
-#define I365_MEM_WRPROT	0x8000	/* In offset high byte */
-#define I365_MEM_REG	0x4000
-
-#define I365_REG(slot, reg)	(((slot) << 6) | (reg))
-
-/* Default ISA interrupt mask */
-#define I365_ISA_IRQ_MASK	0xdeb8	/* irq's 3-5,7,9-12,14,15 */
-
-/* Device ID's for PCI-to-PCMCIA bridges */
-
-#ifndef PCI_VENDOR_ID_INTEL
-#define PCI_VENDOR_ID_INTEL		0x8086
-#endif
-#ifndef PCI_DEVICE_ID_INTEL_82092AA_0
-#define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
-#endif
-#ifndef PCI_VENDOR_ID_OMEGA
-#define PCI_VENDOR_ID_OMEGA		0x119b
-#endif
-#ifndef PCI_DEVICE_ID_OMEGA_82C092G
-#define PCI_DEVICE_ID_OMEGA_82C092G	0x1221
-#endif
-
-#endif /* _LINUX_I82365_H */
diff --git a/include/pcmcia/ss.h b/include/pcmcia/ss.h
deleted file mode 100644
index aafae8a547..0000000000
--- a/include/pcmcia/ss.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * ss.h 1.31 2001/08/24 12:16:13
- *
- * The contents of this file are subject to the Mozilla Public License
- * Version 1.1 (the "License"); you may not use this file except in
- * compliance with the License. You may obtain a copy of the License
- * at http://www.mozilla.org/MPL/
- *
- * Software distributed under the License is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
- * the License for the specific language governing rights and
- * limitations under the License.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in
- * which case the provisions of the GPL are applicable instead of the
- * above.  If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use
- * your version of this file under the MPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL.  If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the MPL or the GPL.
- */
-
-#ifndef _LINUX_SS_H
-#define _LINUX_SS_H
-
-/* For RegisterCallback */
-typedef struct ss_callback_t {
-    void	(*handler)(void *info, u_int events);
-    void	*info;
-} ss_callback_t;
-
-/* Definitions for card status flags for GetStatus */
-#define SS_WRPROT	0x0001
-#define SS_CARDLOCK	0x0002
-#define SS_EJECTION	0x0004
-#define SS_INSERTION	0x0008
-#define SS_BATDEAD	0x0010
-#define SS_BATWARN	0x0020
-#define SS_READY	0x0040
-#define SS_DETECT	0x0080
-#define SS_POWERON	0x0100
-#define SS_GPI		0x0200
-#define SS_STSCHG	0x0400
-#define SS_CARDBUS	0x0800
-#define SS_3VCARD	0x1000
-#define SS_XVCARD	0x2000
-#define SS_PENDING	0x4000
-
-/* for InquireSocket */
-typedef struct socket_cap_t {
-    u_int	features;
-    u_int	irq_mask;
-    u_int	map_size;
-    u_char	pci_irq;
-    u_char	cardbus;
-    struct pci_bus *cb_bus;
-    struct bus_operations *bus;
-} socket_cap_t;
-
-/* InquireSocket capabilities */
-#define SS_CAP_PAGE_REGS	0x0001
-#define SS_CAP_VIRTUAL_BUS	0x0002
-#define SS_CAP_MEM_ALIGN	0x0004
-#define SS_CAP_STATIC_MAP	0x0008
-#define SS_CAP_PCCARD		0x4000
-#define SS_CAP_CARDBUS		0x8000
-
-/* for GetSocket, SetSocket */
-typedef struct socket_state_t {
-    u_int	flags;
-    u_int	csc_mask;
-    u_char	Vcc, Vpp;
-    u_char	io_irq;
-} socket_state_t;
-
-/* Socket configuration flags */
-#define SS_PWR_AUTO	0x0010
-#define SS_IOCARD	0x0020
-#define SS_RESET	0x0040
-#define SS_DMA_MODE	0x0080
-#define SS_SPKR_ENA	0x0100
-#define SS_OUTPUT_ENA	0x0200
-#define SS_ZVCARD	0x0400
-
-/* Flags for I/O port and memory windows */
-#define MAP_ACTIVE	0x01
-#define MAP_16BIT	0x02
-#define MAP_AUTOSZ	0x04
-#define MAP_0WS		0x08
-#define MAP_WRPROT	0x10
-#define MAP_ATTRIB	0x20
-#define MAP_USE_WAIT	0x40
-#define MAP_PREFETCH	0x80
-
-/* Use this just for bridge windows */
-#define MAP_IOSPACE	0x20
-
-typedef struct pccard_io_map {
-    u_char	map;
-    u_char	flags;
-    u_short	speed;
-    u_short	start, stop;
-} pccard_io_map;
-
-typedef struct pccard_mem_map {
-    u_char	map;
-    u_char	flags;
-    u_short	speed;
-    u_long	sys_start, sys_stop;
-    u_int	card_start;
-} pccard_mem_map;
-
-typedef struct cb_bridge_map {
-    u_char	map;
-    u_char	flags;
-    u_int	start, stop;
-} cb_bridge_map;
-
-enum ss_service {
-    SS_RegisterCallback, SS_InquireSocket,
-    SS_GetStatus, SS_GetSocket, SS_SetSocket,
-    SS_GetIOMap, SS_SetIOMap, SS_GetMemMap, SS_SetMemMap,
-    SS_GetBridge, SS_SetBridge, SS_ProcSetup
-};
-
-#endif /* _LINUX_SS_H */
diff --git a/include/pcmcia/ti113x.h b/include/pcmcia/ti113x.h
deleted file mode 100644
index 5453588d0c..0000000000
--- a/include/pcmcia/ti113x.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * ti113x.h 1.31 2002/05/12 18:19:47
- *
- * The contents of this file are subject to the Mozilla Public License
- * Version 1.1 (the "License"); you may not use this file except in
- * compliance with the License. You may obtain a copy of the License
- * at http://www.mozilla.org/MPL/
- *
- * Software distributed under the License is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
- * the License for the specific language governing rights and
- * limitations under the License.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in
- * which case the provisions of the GPL are applicable instead of the
- * above.  If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use
- * your version of this file under the MPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL.  If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the MPL or the GPL.
- */
-
-#ifndef _LINUX_TI113X_H
-#define _LINUX_TI113X_H
-
-#ifndef PCI_VENDOR_ID_TI
-#define PCI_VENDOR_ID_TI		0x104c
-#endif
-
-#ifndef PCI_DEVICE_ID_TI_1130
-#define PCI_DEVICE_ID_TI_1130		0xac12
-#endif
-#ifndef PCI_DEVICE_ID_TI_1031
-#define PCI_DEVICE_ID_TI_1031		0xac13
-#endif
-#ifndef PCI_DEVICE_ID_TI_1131
-#define PCI_DEVICE_ID_TI_1131		0xac15
-#endif
-#ifndef PCI_DEVICE_ID_TI_1210
-#define PCI_DEVICE_ID_TI_1210		0xac1a
-#endif
-#ifndef PCI_DEVICE_ID_TI_1211
-#define PCI_DEVICE_ID_TI_1211		0xac1e
-#endif
-#ifndef PCI_DEVICE_ID_TI_1220
-#define PCI_DEVICE_ID_TI_1220		0xac17
-#endif
-#ifndef PCI_DEVICE_ID_TI_1221
-#define PCI_DEVICE_ID_TI_1221		0xac19
-#endif
-#ifndef PCI_DEVICE_ID_TI_1250A
-#define PCI_DEVICE_ID_TI_1250A		0xac16
-#endif
-#ifndef PCI_DEVICE_ID_TI_1225
-#define PCI_DEVICE_ID_TI_1225		0xac1c
-#endif
-#ifndef PCI_DEVICE_ID_TI_1251A
-#define PCI_DEVICE_ID_TI_1251A		0xac1d
-#endif
-#ifndef PCI_DEVICE_ID_TI_1251B
-#define PCI_DEVICE_ID_TI_1251B		0xac1f
-#endif
-#ifndef PCI_DEVICE_ID_TI_1410
-#define PCI_DEVICE_ID_TI_1410		0xac50
-#endif
-#ifndef PCI_DEVICE_ID_TI_1420
-#define PCI_DEVICE_ID_TI_1420		0xac51
-#endif
-#ifndef PCI_DEVICE_ID_TI_1450
-#define PCI_DEVICE_ID_TI_1450		0xac1b
-#endif
-#ifndef PCI_DEVICE_ID_TI_1451
-#define PCI_DEVICE_ID_TI_1451		0xac52
-#endif
-#ifndef PCI_DEVICE_ID_TI_1510
-#define PCI_DEVICE_ID_TI_1510		0xac56
-#endif
-#ifndef PCI_DEVICE_ID_TI_4410
-#define PCI_DEVICE_ID_TI_4410		0xac41
-#endif
-#ifndef PCI_DEVICE_ID_TI_4450
-#define PCI_DEVICE_ID_TI_4450		0xac40
-#endif
-#ifndef PCI_DEVICE_ID_TI_4451
-#define PCI_DEVICE_ID_TI_4451		0xac42
-#endif
-
-/* Register definitions for TI 113X PCI-to-CardBus bridges */
-
-/* System Control Register */
-#define TI113X_SYSTEM_CONTROL		0x80	/* 32 bit */
-#define  TI113X_SCR_SMIROUTE		0x04000000
-#define  TI113X_SCR_SMISTATUS		0x02000000
-#define  TI113X_SCR_SMIENB		0x01000000
-#define  TI113X_SCR_VCCPROT		0x00200000
-#define  TI113X_SCR_REDUCEZV		0x00100000
-#define  TI113X_SCR_CDREQEN		0x00080000
-#define  TI113X_SCR_CDMACHAN		0x00070000
-#define  TI113X_SCR_SOCACTIVE		0x00002000
-#define  TI113X_SCR_PWRSTREAM		0x00000800
-#define  TI113X_SCR_DELAYUP		0x00000400
-#define  TI113X_SCR_DELAYDOWN		0x00000200
-#define  TI113X_SCR_INTERROGATE		0x00000100
-#define  TI113X_SCR_CLKRUN_SEL		0x00000080
-#define  TI113X_SCR_PWRSAVINGS		0x00000040
-#define  TI113X_SCR_SUBSYSRW		0x00000020
-#define  TI113X_SCR_CB_DPAR		0x00000010
-#define  TI113X_SCR_CDMA_EN		0x00000008
-#define  TI113X_SCR_ASYNC_IRQ		0x00000004
-#define  TI113X_SCR_KEEPCLK		0x00000002
-#define  TI113X_SCR_CLKRUN_ENA		0x00000001
-
-#define  TI122X_SCR_SER_STEP		0xc0000000
-#define  TI122X_SCR_INTRTIE		0x20000000
-#define  TI122X_SCR_P2CCLK		0x08000000
-#define  TI122X_SCR_CBRSVD		0x00400000
-#define  TI122X_SCR_MRBURSTDN		0x00008000
-#define  TI122X_SCR_MRBURSTUP		0x00004000
-#define  TI122X_SCR_RIMUX		0x00000001
-
-/* Multimedia Control Register */
-#define TI1250_MULTIMEDIA_CTL		0x84	/* 8 bit */
-#define  TI1250_MMC_ZVOUTEN		0x80
-#define  TI1250_MMC_PORTSEL		0x40
-#define  TI1250_MMC_ZVEN1		0x02
-#define  TI1250_MMC_ZVEN0		0x01
-
-#define TI1250_GENERAL_STATUS		0x85	/* 8 bit */
-#define TI1250_GPIO0_CONTROL		0x88	/* 8 bit */
-#define TI1250_GPIO1_CONTROL		0x89	/* 8 bit */
-#define TI1250_GPIO2_CONTROL		0x8a	/* 8 bit */
-#define TI1250_GPIO3_CONTROL		0x8b	/* 8 bit */
-#define TI12XX_IRQMUX			0x8c	/* 32 bit */
-
-/* Retry Status Register */
-#define TI113X_RETRY_STATUS		0x90	/* 8 bit */
-#define  TI113X_RSR_PCIRETRY		0x80
-#define  TI113X_RSR_CBRETRY		0x40
-#define  TI113X_RSR_TEXP_CBB		0x20
-#define  TI113X_RSR_MEXP_CBB		0x10
-#define  TI113X_RSR_TEXP_CBA		0x08
-#define  TI113X_RSR_MEXP_CBA		0x04
-#define  TI113X_RSR_TEXP_PCI		0x02
-#define  TI113X_RSR_MEXP_PCI		0x01
-
-/* Card Control Register */
-#define TI113X_CARD_CONTROL		0x91	/* 8 bit */
-#define  TI113X_CCR_RIENB		0x80
-#define  TI113X_CCR_ZVENABLE		0x40
-#define  TI113X_CCR_PCI_IRQ_ENA		0x20
-#define  TI113X_CCR_PCI_IREQ		0x10
-#define  TI113X_CCR_PCI_CSC		0x08
-#define  TI113X_CCR_SPKROUTEN		0x02
-#define  TI113X_CCR_IFG			0x01
-
-#define  TI1220_CCR_PORT_SEL		0x20
-#define  TI122X_CCR_AUD2MUX		0x04
-
-/* Device Control Register */
-#define TI113X_DEVICE_CONTROL		0x92	/* 8 bit */
-#define  TI113X_DCR_5V_FORCE		0x40
-#define  TI113X_DCR_3V_FORCE		0x20
-#define  TI113X_DCR_IMODE_MASK		0x06
-#define  TI113X_DCR_IMODE_ISA		0x02
-#define  TI113X_DCR_IMODE_SERIAL	0x04
-
-#define  TI12XX_DCR_IMODE_PCI_ONLY	0x00
-#define  TI12XX_DCR_IMODE_ALL_SERIAL	0x06
-
-/* Buffer Control Register */
-#define TI113X_BUFFER_CONTROL		0x93	/* 8 bit */
-#define  TI113X_BCR_CB_READ_DEPTH	0x08
-#define  TI113X_BCR_CB_WRITE_DEPTH	0x04
-#define  TI113X_BCR_PCI_READ_DEPTH	0x02
-#define  TI113X_BCR_PCI_WRITE_DEPTH	0x01
-
-/* Diagnostic Register */
-#define TI1250_DIAGNOSTIC		0x93	/* 8 bit */
-#define  TI1250_DIAG_TRUE_VALUE		0x80
-#define  TI1250_DIAG_PCI_IREQ		0x40
-#define  TI1250_DIAG_PCI_CSC		0x20
-#define  TI1250_DIAG_ASYNC_CSC		0x01
-
-/* DMA Registers */
-#define TI113X_DMA_0			0x94	/* 32 bit */
-#define TI113X_DMA_1			0x98	/* 32 bit */
-
-/* ExCA IO offset registers */
-#define TI113X_IO_OFFSET(map)		(0x36+((map)<<1))
-
-/* Data structure for tracking vendor-specific state */
-typedef struct ti113x_state_t {
-    u32			sysctl;		/* TI113X_SYSTEM_CONTROL */
-    u8			cardctl;	/* TI113X_CARD_CONTROL */
-    u8			devctl;		/* TI113X_DEVICE_CONTROL */
-    u8			diag;		/* TI1250_DIAGNOSTIC */
-    u32			irqmux;		/* TI12XX_IRQMUX */
-} ti113x_state_t;
-
-#define TI_PCIC_ID \
-    IS_TI1130, IS_TI1131, IS_TI1031, IS_TI1210, IS_TI1211,	\
-    IS_TI1220, IS_TI1221, IS_TI1225, IS_TI1250A, IS_TI1251A,	\
-    IS_TI1251B, IS_TI1410, IS_TI1420, IS_TI1450, IS_TI1451,	\
-    IS_TI1510, IS_TI4410, IS_TI4450, IS_TI4451
-
-#define TI_PCIC_INFO \
-    { "TI 1130",  IS_TI|IS_CARDBUS, ID(TI, 1130) }, \
-    { "TI 1131",  IS_TI|IS_CARDBUS, ID(TI, 1131) }, \
-    { "TI 1031",  IS_TI|IS_CARDBUS, ID(TI, 1031) }, \
-    { "TI 1210",  IS_TI|IS_CARDBUS, ID(TI, 1210) }, \
-    { "TI 1211",  IS_TI|IS_CARDBUS, ID(TI, 1211) }, \
-    { "TI 1220",  IS_TI|IS_CARDBUS, ID(TI, 1220) }, \
-    { "TI 1221",  IS_TI|IS_CARDBUS, ID(TI, 1221) }, \
-    { "TI 1225",  IS_TI|IS_CARDBUS, ID(TI, 1225) }, \
-    { "TI 1250A", IS_TI|IS_CARDBUS, ID(TI, 1250A) }, \
-    { "TI 1251A", IS_TI|IS_CARDBUS, ID(TI, 1251A) }, \
-    { "TI 1251B", IS_TI|IS_CARDBUS, ID(TI, 1251B) }, \
-    { "TI 1410",  IS_TI|IS_CARDBUS, ID(TI, 1410) }, \
-    { "TI 1420",  IS_TI|IS_CARDBUS, ID(TI, 1420) }, \
-    { "TI 1450",  IS_TI|IS_CARDBUS, ID(TI, 1450) }, \
-    { "TI 1451",  IS_TI|IS_CARDBUS, ID(TI, 1451) }, \
-    { "TI 1510",  IS_TI|IS_CARDBUS, ID(TI, 1510) }, \
-    { "TI 4410",  IS_TI|IS_CARDBUS, ID(TI, 4410) }, \
-    { "TI 4450",  IS_TI|IS_CARDBUS, ID(TI, 4450) }, \
-    { "TI 4451",  IS_TI|IS_CARDBUS, ID(TI, 4451) }
-
-#endif /* _LINUX_TI113X_H */
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 5fcef9cebb..36d5975584 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -80,7 +80,7 @@
 #define	r31	31
 
 
-#if defined(CONFIG_8xx) || defined(CONFIG_MPC824X)
+#if defined(CONFIG_8xx)
 
 /* Some special registers */
 
@@ -92,7 +92,7 @@
 #define LCTRL2	157	/* Load/Store Support	    (37-41) */
 #define ICTRL	158
 
-#endif	/* CONFIG_8xx, CONFIG_MPC824X */
+#endif	/* CONFIG_8xx */
 
 
 #if  defined(CONFIG_5xx)