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| author | Anatolij Gustschin <agust@denx.de> | 2008-12-02 10:31:04 +0100 |
|---|---|---|
| committer | Ben Warren <biggerbadderben@gmail.com> | 2008-12-04 22:51:54 -0800 |
| commit | 23afaba65ec5206757e589ef334a8b38168c045f (patch) | |
| tree | 3c16f0e84b9cdcccac14644f05cdff7f9a150ba3 /include/tsec.h | |
| parent | 2e4970d8109d690adcf615d9e3cac7b5b2e8eaed (diff) | |
| download | u-boot-23afaba65ec5206757e589ef334a8b38168c045f.tar.gz u-boot-23afaba65ec5206757e589ef334a8b38168c045f.tar.bz2 u-boot-23afaba65ec5206757e589ef334a8b38168c045f.zip | |
net: tsec: Fix Marvell 88E1121R phy init
This patch tries to ensure that phy interrupt pin
won't be asserted after booting. We experienced
following issues with current 88E1121R phy init:
Marvell 88E1121R phy can be hardware-configured
to share MDC/MDIO and interrupt pins for both ports
P0 and P1 (e.g. as configured on socrates board).
Port 0 interrupt pin will be shared by both ports
in such configuration. After booting Linux and
configuring eth0 interface, port 0 phy interrupts
are enabled. After rebooting without proper eth0
interface shutdown port 0 phy interrupts remain
enabled so any change on port 0 (link status, etc.)
cause assertion of the interrupt. Now booting Linux
and configuring eth1 interface will cause permanent
phy interrupt storm as the registered phy 1 interrupt
handler doesn't acknowledge phy 0 interrupts. This
of course should be fixed in Linux driver too.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Diffstat (limited to 'include/tsec.h')
| -rw-r--r-- | include/tsec.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/tsec.h b/include/tsec.h index d2951f6d33..7b52e06ab0 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -226,6 +226,10 @@ #define MIIM_88E1121_PHY_LED_PAGE 3 #define MIIM_88E1121_PHY_LED_DEF 0x0030 +/* 88E1121 PHY IRQ Enable/Status Register */ +#define MIIM_88E1121_PHY_IRQ_EN 18 +#define MIIM_88E1121_PHY_IRQ_STATUS 19 + #define MIIM_88E1121_PHY_PAGE 22 /* 88E1145 Extended PHY Specific Control Register */ |