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authorMarek Vasut <marek.vasut+renesas@mailbox.org>2024-07-23 01:28:34 +0200
committerTom Rini <trini@konsulko.com>2024-07-29 15:01:04 -0600
commit6627fbba203f89a316299d35f6a2ff3f33dd15c8 (patch)
treecce8ae95fef0efc70c6ee256b3f007951aaec56f /include/mpc8xx.h
parenta1af57b70ad14fc490b5227d11c0edd954a81978 (diff)
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include: Remove duplicate newlines
Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Diffstat (limited to 'include/mpc8xx.h')
-rw-r--r--include/mpc8xx.h5
1 files changed, 0 insertions, 5 deletions
diff --git a/include/mpc8xx.h b/include/mpc8xx.h
index 0e0e0cb70d..53e0be3de4 100644
--- a/include/mpc8xx.h
+++ b/include/mpc8xx.h
@@ -13,7 +13,6 @@
#ifndef __MPCXX_H__
#define __MPCXX_H__
-
/*-----------------------------------------------------------------------
* Exception offsets (PowerPC standard)
*/
@@ -200,7 +199,6 @@
#define SCCR_DFALCD10 0x00000002 /* Division by 5 */
#define SCCR_DFALCD11 0x00000003 /* Division by 7 (maximum) */
-
/*-----------------------------------------------------------------------
* BR - Memory Controler: Base Register 16-9
*/
@@ -253,7 +251,6 @@
#define OR_TRLX 0x00000004 /* Timing Relaxed */
#define OR_EHTR 0x00000002 /* Extended Hold Time on Read */
-
/*-----------------------------------------------------------------------
* MPTPR - Memory Periodic Timer Prescaler Register 16-17
*/
@@ -464,7 +461,6 @@
#define TGCR_STP1 0x0002 /* Stop timer 1 */
#define TGCR_RST1 0x0001 /* Reset timer 1 */
-
/*-----------------------------------------------------------------------
* Timer Mode Register 18-9
*/
@@ -485,7 +481,6 @@
#define TMR_ICLK_TIN_PIN 0x0006 /* TINx pin */
#define TMR_GE 0x0001 /* Gate Enable */
-
/*-----------------------------------------------------------------------
* I2C Controller Registers
*/