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| author | Gaurav Jain <gaurav.jain@nxp.com> | 2022-04-15 16:40:49 +0530 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-05-19 21:39:36 +0200 |
| commit | 0c45c77b8aeac0c3c5a0b5ea13a44ee478b51fdb (patch) | |
| tree | 6df39d78304f7eed572a0d148fd37741a94cd763 /include/fsl_sec.h | |
| parent | 9fd406de522ef1fb5863837eee1dd9bd99cd4b07 (diff) | |
| download | u-boot-0c45c77b8aeac0c3c5a0b5ea13a44ee478b51fdb.tar.gz u-boot-0c45c77b8aeac0c3c5a0b5ea13a44ee478b51fdb.tar.bz2 u-boot-0c45c77b8aeac0c3c5a0b5ea13a44ee478b51fdb.zip | |
i.MX6SX: crypto/fsl: fix entropy delay value
RNG Hardware error is reported due to incorrect entropy delay
rng self test are run to determine the correct ent_dly.
test is executed with different voltage and temperature to identify the
worst case value for ent_dly. after adding a margin value(1000),
ent_dly should be at least 12000.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Diffstat (limited to 'include/fsl_sec.h')
| -rw-r--r-- | include/fsl_sec.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 7b6e3e2c20..d57c4ca820 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -48,7 +48,11 @@ struct rng4tst { u32 rtmctl; /* misc. control register */ u32 rtscmisc; /* statistical check misc. register */ u32 rtpkrrng; /* poker range register */ -#define RTSDCTL_ENT_DLY_MIN 3200 +#ifdef CONFIG_MX6SX +#define RTSDCTL_ENT_DLY 12000 +#else +#define RTSDCTL_ENT_DLY 3200 +#endif #define RTSDCTL_ENT_DLY_MAX 12800 union { u32 rtpkrmax; /* PRGM=1: poker max. limit register */ |