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| author | Tom Rini <trini@konsulko.com> | 2024-07-04 16:11:08 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-07-04 16:11:08 -0600 |
| commit | 7c9c5c0562347dccb8ac89148784a34de402ea9e (patch) | |
| tree | 5fdbb111881c14649932cf9e58dbbec6cb9b8e1a /include/configs | |
| parent | 26c56f1c58f6cdbbfb3428526136749ff8372c53 (diff) | |
| parent | 51aabf50e57f5139de31a4850347edbad8bb338b (diff) | |
| download | u-boot-7c9c5c0562347dccb8ac89148784a34de402ea9e.tar.gz u-boot-7c9c5c0562347dccb8ac89148784a34de402ea9e.tar.bz2 u-boot-7c9c5c0562347dccb8ac89148784a34de402ea9e.zip | |
Merge patch series "xtensa: Enable qemu-xtensa board"
Jiaxun Yang <jiaxun.yang@flygoat.com> says:
Hi all,
This series enabled qemu-xtensa board.
For dc232b CPU it needs to be built with toolchain[1].
This is a side product of me investigating architectures
physical address != virtual address in U-Boot. Now we can
get it covered under CI and regular tests.
VirtIO devices are not working as expected, due to U-Boot's
assumption on VA == PA everywhere, I'm going to get this fixed
later.
My Xtensa knowledge is pretty limited, Xtensa people please
feel free to point out if I got anything wrong.
Thanks
[1]: https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc232b-elf.tar.gz
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/qemu-xtensa.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/include/configs/qemu-xtensa.h b/include/configs/qemu-xtensa.h new file mode 100644 index 0000000000..505aa0646b --- /dev/null +++ b/include/configs/qemu-xtensa.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2007-2013 Tensilica, Inc. + * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. + * Copyright (C) 2024 Jiaxun Yang <jiaxun.yang@flygoat.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/core.h> +#include <asm/addrspace.h> +#include <asm/config.h> + +#if XCHAL_HAVE_PTP_MMU +#define CFG_SYS_MEMORY_BASE \ + (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) +#define CFG_SYS_IO_BASE 0xf0000000 +#define CFG_SYS_SDRAM_SIZE 0x80000000 /* xtensa.sysram0 */ +#else +#define CFG_SYS_MEMORY_BASE 0x60000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* xtensa.sysram0 */ +#endif + +#define CFG_SYS_SDRAM_BASE MEMADDR(0x00000000) + +#if defined(CFG_MAX_MEM_MAPPED) && \ + CFG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE +#define XTENSA_SYS_TEXT_ADDR \ + (MEMADDR(CFG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN) +#else +#define XTENSA_SYS_TEXT_ADDR \ + (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN) +#endif + +#endif /* __CONFIG_H */ |