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authorTom Rini <trini@konsulko.com>2022-11-16 13:10:33 -0500
committerTom Rini <trini@konsulko.com>2022-12-05 16:06:07 -0500
commitecc8d425fd50d894dd0a06796c17030ef4a7942f (patch)
tree6fade563d93ccb2dc3c774bdcc3d2f5cf5b6403c /include/configs
parent789bb9537a4427798e3e28ff0c6be2c27454315f (diff)
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global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/MPC837XERDB.h18
-rw-r--r--include/configs/MPC8548CDS.h24
-rw-r--r--include/configs/P1010RDB.h24
-rw-r--r--include/configs/P2041RDB.h20
-rw-r--r--include/configs/T102xRDB.h20
-rw-r--r--include/configs/T104xRDB.h24
-rw-r--r--include/configs/T208xQDS.h24
-rw-r--r--include/configs/T208xRDB.h24
-rw-r--r--include/configs/T4240RDB.h24
-rw-r--r--include/configs/kmcent2.h8
-rw-r--r--include/configs/p1_p2_rdb_pc.h24
-rw-r--r--include/configs/socrates.h4
12 files changed, 119 insertions, 119 deletions
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 059885ecb5..0e70b2853b 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -177,15 +177,15 @@
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
-
-#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
+#define CFG_SYS_PCIE1_CFG_BASE 0xA0000000
+#define CFG_SYS_PCIE1_CFG_SIZE 0x08000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0xA8000000
+#define CFG_SYS_PCIE1_IO_PHYS 0xB8000000
+
+#define CFG_SYS_PCIE2_CFG_BASE 0xC0000000
+#define CFG_SYS_PCIE2_CFG_SIZE 0x08000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xC8000000
+#define CFG_SYS_PCIE2_IO_PHYS 0xD8000000
/*
* TSEC
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index c29e63c54e..c59a37646f 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -254,31 +254,31 @@
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
+#define CFG_SYS_PCI1_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
+#define CFG_SYS_PCI1_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
+#define CFG_SYS_PCI1_MEM_PHYS 0x80000000
#endif
-#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
+#define CFG_SYS_PCI1_IO_VIRT 0xe2000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
+#define CFG_SYS_PCI1_IO_PHYS 0xfe2000000ull
#else
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
+#define CFG_SYS_PCI1_IO_PHYS 0xe2000000
#endif
#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
+#define CFG_SYS_PCIE1_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0xa0000000
#endif
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
+#define CFG_SYS_PCIE1_IO_VIRT 0xe3000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
+#define CFG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
+#define CFG_SYS_PCIE1_IO_PHYS 0xe3000000
#endif
#endif
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 05c097759f..f87e7597ad 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -68,31 +68,31 @@
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0x80000000
#endif
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
+#define CFG_SYS_PCIE1_IO_VIRT 0xffc00000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
+#define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
+#define CFG_SYS_PCIE1_IO_PHYS 0xffc00000
#endif
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
+#define CFG_SYS_PCIE2_IO_VIRT 0xffc10000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
+#define CFG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
+#define CFG_SYS_PCIE2_IO_PHYS 0xffc10000
#endif
#endif
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index c832981078..e996dbaa4d 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -234,20 +234,20 @@
*/
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
+#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000
+#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
/* Qman/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index e21639a695..6d6e334bf0 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -331,24 +331,24 @@
#ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
#endif
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#ifdef CONFIG_PCIE2
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
+#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
#endif
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#ifdef CONFIG_PCIE3
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000
+#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
#endif
#endif /* CONFIG_PCI */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index a3d04882f0..423ba81617 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -307,30 +307,30 @@
#ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
#endif
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#ifdef CONFIG_PCIE2
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
+#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
#endif
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#ifdef CONFIG_PCIE3
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000
+#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
#endif
/* controller 4, Base address 203000 */
#ifdef CONFIG_PCIE4
-#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
+#define CFG_SYS_PCIE4_MEM_VIRT 0xb0000000
+#define CFG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
#endif
#endif /* CONFIG_PCI */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 72052be78a..2efc2eb95c 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -345,24 +345,24 @@
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
+#define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000
+#define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
+#define CFG_SYS_PCIE4_MEM_VIRT 0xc0000000
+#define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index c798e4487a..ca8bfac0c6 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -299,24 +299,24 @@
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
+#define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000
+#define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
+#define CFG_SYS_PCIE4_MEM_VIRT 0xc0000000
+#define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 5777df8e50..091920dccf 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -107,24 +107,24 @@
*/
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
+#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000
+#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
+#define CFG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CFG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
/*
* Miscellaneous configurable options
diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index 7af65737ff..1df90def67 100644
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h
@@ -346,10 +346,10 @@ int get_scl(void);
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* controller 1 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 44e608536f..6e8ac1b98d 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -343,31 +343,31 @@
*/
/* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
+#define CFG_SYS_PCIE2_IO_VIRT 0xffc10000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
+#define CFG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
+#define CFG_SYS_PCIE2_IO_PHYS 0xffc10000
#endif
/* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0x80000000
#endif
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
+#define CFG_SYS_PCIE1_IO_VIRT 0xffc00000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
+#define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
+#define CFG_SYS_PCIE1_IO_PHYS 0xffc00000
#endif
#endif /* CONFIG_PCI */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 9b106fc1c9..a60ac6d1a3 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -109,8 +109,8 @@
* Memory space is mapped 1-1.
*/
-#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CFG_SYS_PCI1_MEM_PHYS 0x80000000
+#define CFG_SYS_PCI1_IO_PHYS 0xE2000000
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 01:48:36 +0000