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| author | Tom Warren <twarren@nvidia.com> | 2012-09-04 17:00:24 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2012-09-10 13:01:24 -0700 |
| commit | 29f3e3f24832fccdd7ce5fa961bc4d4005b07381 (patch) | |
| tree | 28c89e24dca02035354f888fb83311217f54d20f /include/configs/tegra20-common.h | |
| parent | 22e73940216ef971c71c49e959519db8babc876a (diff) | |
| download | u-boot-29f3e3f24832fccdd7ce5fa961bc4d4005b07381.tar.gz u-boot-29f3e3f24832fccdd7ce5fa961bc4d4005b07381.tar.bz2 u-boot-29f3e3f24832fccdd7ce5fa961bc4d4005b07381.zip | |
Tegra: Change Tegra20 to Tegra in common code, prep for T30
Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.
Upcoming Tegra30 port will use common code/defines/names where possible.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'include/configs/tegra20-common.h')
| -rw-r--r-- | include/configs/tegra20-common.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 02cf0cdc14..098cdb4460 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -54,7 +54,7 @@ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ -#ifdef CONFIG_TEGRA20_LP0 +#ifdef CONFIG_TEGRA_LP0 #define TEGRA_LP0_ADDR 0x1C406000 #define TEGRA_LP0_SIZE 0x2000 #define TEGRA_LP0_VEC \ @@ -132,9 +132,9 @@ /* Environment information, boards can override if required */ #define CONFIG_CONSOLE_MUX #define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define TEGRA20_DEVICE_SETTINGS "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" +#define TEGRA_DEVICE_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" #define CONFIG_LOADADDR 0x408000 /* def. location for kernel */ #define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ @@ -157,7 +157,7 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) -#define CONFIG_SYS_MEMTEST_START (TEGRA20_SDRC_CS0 + 0x600000) +#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) #define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */ @@ -169,7 +169,7 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 TEGRA20_SDRC_CS0 +#define PHYS_SDRAM_1 NV_PA_SDRC_CS0 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_TEXT_BASE 0x0010c000 |