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| author | Mario Six <mario.six@gdsys.cc> | 2019-01-21 09:18:17 +0100 |
|---|---|---|
| committer | Mario Six <mario.six@gdsys.cc> | 2019-05-21 07:52:33 +0200 |
| commit | 42c9a494f1659db6043f980d5f4fdee86fdf9dfb (patch) | |
| tree | f4a50f87cb3901f0a26b09caa843b48795419c74 /include/configs/MPC8349ITX.h | |
| parent | 133ec602846d28a7915a7b3149d05d1c8a270873 (diff) | |
| download | u-boot-42c9a494f1659db6043f980d5f4fdee86fdf9dfb.tar.gz u-boot-42c9a494f1659db6043f980d5f4fdee86fdf9dfb.tar.bz2 u-boot-42c9a494f1659db6043f980d5f4fdee86fdf9dfb.zip | |
mpc83xx: Get rid of CONFIG_SYS_LBC_*
Except for one counter example, CONFIG_SYS_LBC_LBCR always has a value
of either 0x00040000 or 0x00000000.
CONFIG_SYS_LBC_MRTPR always has the value 0x20000000.
CONFIG_SYS_LBC_LSDMR_{1,2,4,5} are not set for any mpc83xx board.
CONFIG_SYS_LBC_LSRT is set by one board (to 0x32000000).
To simplify the configuration files, hardcode the setting of these
values for mpc83xx.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'include/configs/MPC8349ITX.h')
| -rw-r--r-- | include/configs/MPC8349ITX.h | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 388910ac38..a3f704c73b 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -251,19 +251,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - - /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 - /* LB refresh timer prescal, 266MHz/32*/ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -/* * Serial Port */ #define CONFIG_SYS_NS16550_SERIAL |