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| author | York Sun <yorksun@freescale.com> | 2014-03-27 17:54:47 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:48 -0700 |
| commit | 34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85 (patch) | |
| tree | f155ebdbac95a5ef637e7796ad22935029a56ce6 /include/common_timing_params.h | |
| parent | 8d451a7129ee6820cc126c77f0f0a175a2cb2e8d (diff) | |
| download | u-boot-34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85.tar.gz u-boot-34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85.tar.bz2 u-boot-34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85.zip | |
driver/ddr/fsl: Add DDR4 support to Freescale DDR driver
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/common_timing_params.h')
| -rw-r--r-- | include/common_timing_params.h | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/include/common_timing_params.h b/include/common_timing_params.h index 76338d4e6c..821de21de7 100644 --- a/include/common_timing_params.h +++ b/include/common_timing_params.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -14,32 +14,45 @@ typedef struct { unsigned int tckmin_x_ps; unsigned int tckmax_ps; - unsigned int tckmax_max_ps; unsigned int trcd_ps; unsigned int trp_ps; unsigned int tras_ps; +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + unsigned int taamin_ps; +#endif - unsigned int twr_ps; /* maximum = 63750 ps */ +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int trfc1_ps; + unsigned int trfc2_ps; + unsigned int trfc4_ps; + unsigned int trrds_ps; + unsigned int trrdl_ps; + unsigned int tccdl_ps; +#else unsigned int twtr_ps; /* maximum = 63750 ps */ unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns = 511750 ps */ unsigned int trrd_ps; /* maximum = 63750 ps */ + unsigned int trtp_ps; /* byte 38, spd->trtp */ +#endif + unsigned int twr_ps; /* maximum = 63750 ps */ unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ unsigned int refresh_rate_ps; unsigned int extended_op_srt; +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) unsigned int tis_ps; /* byte 32, spd->ca_setup */ unsigned int tih_ps; /* byte 33, spd->ca_hold */ unsigned int tds_ps; /* byte 34, spd->data_setup */ unsigned int tdh_ps; /* byte 35, spd->data_hold */ - unsigned int trtp_ps; /* byte 38, spd->trtp */ unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ unsigned int tqhs_ps; /* byte 45, spd->tqhs */ +#endif unsigned int ndimms_present; - unsigned int lowest_common_SPD_caslat; + unsigned int lowest_common_spd_caslat; unsigned int highest_common_derated_caslat; unsigned int additive_latency; unsigned int all_dimms_burst_lengths_bitmask; |