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| author | Weijie Gao <weijie.gao@mediatek.com> | 2019-09-25 17:45:17 +0800 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2019-10-25 17:20:43 +0200 |
| commit | 99ced5331baf1254232e3f73e113fb7ecedebad2 (patch) | |
| tree | 2309bc02d52aa649f6d7898ad9be04c37f1f1fd8 /drivers | |
| parent | e365de90517ba4686d7a88417b1a729f5891d376 (diff) | |
| download | u-boot-99ced5331baf1254232e3f73e113fb7ecedebad2.tar.gz u-boot-99ced5331baf1254232e3f73e113fb7ecedebad2.tar.bz2 u-boot-99ced5331baf1254232e3f73e113fb7ecedebad2.zip | |
serial: serial_mtk: enable FIFO and disable flow control
This patch adds codes to enable FIFO and disable flow control taken from
ns16550 driver.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/serial/serial_mtk.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c index bce1be8227..11892a8740 100644 --- a/drivers/serial/serial_mtk.c +++ b/drivers/serial/serial_mtk.c @@ -46,6 +46,22 @@ struct mtk_serial_regs { #define UART_LSR_DR 0x01 /* Data ready */ #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define UART_LSR_TEMT 0x40 /* Xmitter empty */ + +#define UART_MCR_DTR 0x01 /* DTR */ +#define UART_MCR_RTS 0x02 /* RTS */ + +#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ + +#define UART_MCRVAL (UART_MCR_DTR | \ + UART_MCR_RTS) + +/* Clear & enable FIFOs */ +#define UART_FCRVAL (UART_FCR_FIFO_EN | \ + UART_FCR_RXSR | \ + UART_FCR_TXSR) /* the data is correct if the real baud is within 3%. */ #define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100) @@ -175,6 +191,9 @@ static int mtk_serial_probe(struct udevice *dev) /* Disable interrupt */ writel(0, &priv->regs->ier); + writel(UART_MCRVAL, &priv->regs->mcr); + writel(UART_FCRVAL, &priv->regs->fcr); + return 0; } @@ -248,6 +267,8 @@ static inline void _debug_uart_init(void) priv.clock = CONFIG_DEBUG_UART_CLOCK; writel(0, &priv.regs->ier); + writel(UART_MCRVAL, &priv.regs->mcr); + writel(UART_FCRVAL, &priv.regs->fcr); _mtk_serial_setbrg(&priv, CONFIG_BAUDRATE); } |