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| author | Simon Glass <sjg@chromium.org> | 2015-06-07 08:50:40 -0600 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-07-14 18:03:17 -0600 |
| commit | aec241dfb45e7763716c1cbc98942cb01a3a77fd (patch) | |
| tree | 1dccf1997219cdcd4bc565751ac5142113d235d3 /drivers/pci | |
| parent | cdb6babec6422ad4b89e447b1b468f625deaea79 (diff) | |
| download | u-boot-aec241dfb45e7763716c1cbc98942cb01a3a77fd.tar.gz u-boot-aec241dfb45e7763716c1cbc98942cb01a3a77fd.tar.bz2 u-boot-aec241dfb45e7763716c1cbc98942cb01a3a77fd.zip | |
dm: pci: Use the correct hose when configuring devices
Only the PCI controller has access to the PCI region information. Make sure
to use the controller (rather than any attached bridges) when configuring
devices.
This corrects a failure to scan and configure devices when driver model is
enabled for PCI.
Also add a comment to explain the problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/pci-uclass.c | 6 | ||||
| -rw-r--r-- | drivers/pci/pci_common.c | 6 |
2 files changed, 11 insertions, 1 deletions
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index de87505466..41d19cb37a 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -296,6 +296,7 @@ int pci_auto_config_devices(struct udevice *bus) !ret && dev; ret = device_find_next_child(&dev)) { struct pci_child_platdata *pplat; + struct pci_controller *ctlr_hose; pplat = dev_get_parent_platdata(dev); unsigned int max_bus; @@ -303,7 +304,10 @@ int pci_auto_config_devices(struct udevice *bus) bdf = PCI_ADD_BUS(bus->seq, pplat->devfn); debug("%s: device %s\n", __func__, dev->name); - max_bus = pciauto_config_device(hose, bdf); + + /* The root controller has the region information */ + ctlr_hose = hose->ctlr->uclass_priv; + max_bus = pciauto_config_device(ctlr_hose, bdf); sub_bus = max(sub_bus, max_bus); } debug("%s: done\n", __func__); diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c index b9ff23f35b..f67c9c7b2f 100644 --- a/drivers/pci/pci_common.c +++ b/drivers/pci/pci_common.c @@ -11,6 +11,7 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <pci.h> #include <asm/io.h> @@ -221,6 +222,11 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose, return phys_addr; } +#ifdef CONFIG_DM_PCI + /* The root controller has the region information */ + hose = hose->ctlr->uclass_priv; +#endif + /* * if PCI_REGION_MEM is set we do a two pass search with preference * on matches that don't have PCI_REGION_SYS_MEMORY set |