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| author | Bin Meng <bmeng.cn@gmail.com> | 2017-08-22 08:15:10 -0700 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-08-28 07:17:11 -0400 |
| commit | b65c6921433c8fcf306b4671f9f9f7c68c36cefc (patch) | |
| tree | 4970188c3a7f3fb7710bb4c166636c7319ac12d7 /drivers/nvme/nvme.c | |
| parent | 3e18562961933c7772b7e91ba6fc1e908b453d93 (diff) | |
| download | u-boot-b65c6921433c8fcf306b4671f9f9f7c68c36cefc.tar.gz u-boot-b65c6921433c8fcf306b4671f9f9f7c68c36cefc.tar.bz2 u-boot-b65c6921433c8fcf306b4671f9f9f7c68c36cefc.zip | |
nvme: Cache controller's capabilities
Capabilities register is RO and accessed at various places in the
driver. Let's cache it in the controller driver's priv struct.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'drivers/nvme/nvme.c')
| -rw-r--r-- | drivers/nvme/nvme.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index 2ae947c672..d92273e67f 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -318,7 +318,7 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) { int result; u32 aqa; - u64 cap = nvme_readq(&dev->bar->cap); + u64 cap = dev->cap; struct nvme_queue *nvmeq; /* most architectures use 4KB as the page size */ unsigned page_shift = 12; @@ -549,7 +549,7 @@ static int nvme_get_info_from_identify(struct nvme_dev *dev) { struct nvme_id_ctrl buf, *ctrl = &buf; int ret; - int shift = NVME_CAP_MPSMIN(nvme_readq(&dev->bar->cap)) + 12; + int shift = NVME_CAP_MPSMIN(dev->cap) + 12; ret = nvme_identify(dev, 0, 1, (dma_addr_t)ctrl); if (ret) @@ -772,7 +772,6 @@ static int nvme_probe(struct udevice *udev) { int ret; struct nvme_dev *ndev = dev_get_priv(udev); - u64 cap; ndev->instance = trailing_strtol(udev->name); @@ -801,9 +800,9 @@ static int nvme_probe(struct udevice *udev) } ndev->prp_entry_num = MAX_PRP_POOL >> 3; - cap = nvme_readq(&ndev->bar->cap); - ndev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); - ndev->db_stride = 1 << NVME_CAP_STRIDE(cap); + ndev->cap = nvme_readq(&ndev->bar->cap); + ndev->q_depth = min_t(int, NVME_CAP_MQES(ndev->cap) + 1, NVME_Q_DEPTH); + ndev->db_stride = 1 << NVME_CAP_STRIDE(ndev->cap); ndev->dbs = ((void __iomem *)ndev->bar) + 4096; ret = nvme_configure_admin_queue(ndev); |