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| author | Caleb Connolly <caleb.connolly@linaro.org> | 2024-02-26 17:26:14 +0000 |
|---|---|---|
| committer | Caleb Connolly <caleb.connolly@linaro.org> | 2024-03-01 14:44:36 +0000 |
| commit | 19f000b72b2fa7e4540f7cdb91287aff594239bd (patch) | |
| tree | eab3e8c40d0ff5d70f9fa7d84553045bfdd38ea4 /drivers/gpio | |
| parent | a2ce3aac46121e7ffa244540b62b439ddeed7a9c (diff) | |
| download | u-boot-19f000b72b2fa7e4540f7cdb91287aff594239bd.tar.gz u-boot-19f000b72b2fa7e4540f7cdb91287aff594239bd.tar.bz2 u-boot-19f000b72b2fa7e4540f7cdb91287aff594239bd.zip | |
gpio: qcom_pmic: add a quirk to skip GPIO configuration
Some platforms hard reset when attempting to configure PMIC GPIOs. Add
support for quirks specified in match data with a single quirk to skip
this configuration. We rely on the GPIO already be configured correctly,
which is always the case for volume up (the only current user of these
GPIOs).
This is not expected behaviour but appears to be due to a U-Boot
specific bug. This quirk at least allows for the volume buttons to be
used on platforms where this bug is apparent.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Diffstat (limited to 'drivers/gpio')
| -rw-r--r-- | drivers/gpio/qcom_pmic_gpio.c | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 2a4fef8d28..63b512725a 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -64,6 +64,17 @@ #define REG_EN_CTL 0x46 #define REG_EN_CTL_ENABLE (1 << 7) +/** + * pmic_gpio_match_data - platform specific configuration + * + * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them. + * This is a workaround for an unknown bug on some platforms where trying to write the + * GPIO configuration registers causes the board to hang. + */ +enum pmic_gpio_quirks { + QCOM_PMIC_QUIRK_READONLY = (1 << 0), +}; + struct qcom_gpio_bank { uint32_t pid; /* Peripheral ID on SPMI bus */ bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */ @@ -75,7 +86,12 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset, struct qcom_gpio_bank *priv = dev_get_priv(dev); uint32_t gpio_base = priv->pid + REG_OFFSET(offset); uint32_t reg_ctl_val; - int ret; + ulong quirks = dev_get_driver_data(dev); + int ret = 0; + + /* Some PMICs don't like their GPIOs being configured */ + if (quirks & QCOM_PMIC_QUIRK_READONLY) + return 0; /* Disable the GPIO */ ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, @@ -304,7 +320,7 @@ static int qcom_gpio_of_to_plat(struct udevice *dev) static const struct udevice_id qcom_gpio_ids[] = { { .compatible = "qcom,pm8916-gpio" }, { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ - { .compatible = "qcom,pm8998-gpio" }, + { .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, { .compatible = "qcom,pms405-gpio" }, { } }; |