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| author | Sean Anderson <sean.anderson@seco.com> | 2022-08-30 17:01:07 -0400 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2022-09-06 09:28:46 +0800 |
| commit | 6f6fbb334cc72cd5183cfe9a5b9fd31bc5d404d7 (patch) | |
| tree | 3ee398ca5bfa10319f6e493f4ba415d92edcf9af /drivers/ddr | |
| parent | 96624d7b47530bb3e0009c01aa64d8e5279f95bd (diff) | |
| download | u-boot-6f6fbb334cc72cd5183cfe9a5b9fd31bc5d404d7.tar.gz u-boot-6f6fbb334cc72cd5183cfe9a5b9fd31bc5d404d7.tar.bz2 u-boot-6f6fbb334cc72cd5183cfe9a5b9fd31bc5d404d7.zip | |
ddr: fsl: Make bank_addr_bits reflect actual bits
In both the Freescale DDR controller and the SPD spec, bank address bits
are stored as the number of bank address bits minus 2. For example, if a
chip had 8 banks (3 total bank address bits), the value of
bank_addr_bits would be 1. This is rather surprising for users
configuring their memory manually, since they can't set bank_addr_bits
to the actual number of bank address bits. Rectify this.
There is at least one example of this kind of mistake already, in
board/freescale/t102xrdb/ddr.c. The documented MT40A512M8HX has two bank
address bits, but bank_addr_bits was set to 2, implying 4 bank address
bits. Such a value is reserved in BA_BITS_CS, but I suspect the
controller simply ignores the top bit, making this kind of mistake
harmless, if misleading.
Fixes: e8a7f1c32b5 ("powerpc/t1023rdb: Add T1023 RDB board support")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/fsl/ctrl_regs.c | 2 | ||||
| -rw-r--r-- | drivers/ddr/fsl/ddr4_dimm_params.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index b5122d1a1c..0b0b4e5cb7 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -214,7 +214,7 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; #ifdef CONFIG_SYS_FSL_DDR4 - ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits; + ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits - 2; bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits; #else n_banks_per_sdram_device diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c index e2bdc12ef2..ea79162262 100644 --- a/drivers/ddr/fsl/ddr4_dimm_params.c +++ b/drivers/ddr/fsl/ddr4_dimm_params.c @@ -246,7 +246,7 @@ unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, /* SDRAM device parameters */ pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12; pdimm->n_col_addr = (spd->addressing & 0x7) + 9; - pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3; + pdimm->bank_addr_bits = ((spd->density_banks >> 4) & 0x3) + 2; pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3; /* |