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author | Tony Dinh <mibodhi@gmail.com> | 2023-04-02 21:42:33 -0700 |
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committer | Stefan Roese <sr@denx.de> | 2023-04-13 11:34:47 +0200 |
commit | 6add83991b2887619d0b25e4068b4c0082a4596a (patch) | |
tree | 15c3bc3a53853419b21597d337447f457c85f69a /drivers/ddr | |
parent | c62af15393b34dff4350d37e678707ad70e288a7 (diff) | |
download | u-boot-6add83991b2887619d0b25e4068b4c0082a4596a.tar.gz u-boot-6add83991b2887619d0b25e4068b4c0082a4596a.tar.bz2 u-boot-6add83991b2887619d0b25e4068b4c0082a4596a.zip |
ddr: marvell: a38x: Perform DDR training sequence again for 2nd boot
- DDR Training sequence happens very fast. The speedup in boot time is
negligible by skipping the training sequence during 2nd boot or after.
So remove the check and skip.
- This change improves the robustness of DDR training. If u-boot crashed
during DDR training, the training could be left in a limbo state, where
the BootROM has recorded that it is already in a 2nd boot. The training
must be repeated in this scenario to get out of this limbo state, but due
to the check it cannot be performed.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/ddr')
-rw-r--r-- | drivers/ddr/marvell/a38x/mv_ddr_plat.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c index 6e7949ac72..8ec9fb0874 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c @@ -1363,13 +1363,6 @@ int mv_ddr_pre_training_soc_config(const char *ddr_type) DRAM_RESET_MASK_MASKED << DRAM_RESET_MASK_OFFS); } - /* Check if DRAM is already initialized */ - if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & - (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) { - printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type); - return MV_OK; - } - /* Fix read ready phases for all SOC in reg 0x15c8 */ reg_val = reg_read(TRAINING_DBG_3_REG); |