Merge branch 'u-boot/master' into 'u-boot-arm/master'

Conflicts:
	arch/arm/cpu/armv7/rmobile/Makefile
	doc/README.scrapyard

Needed manual fix:
	arch/arm/cpu/armv7/omap-common/Makefile
	board/compulab/cm_t335/u-boot.lds

5 files changed, 82 insertions, 200 deletions

diff --git a/doc/README.malta b/doc/README.malta
new file mode 100644
index 0000000000..a495d02455
--- /dev/null
+++ b/doc/README.malta
@@ -0,0 +1,16 @@
+MIPS Malta board
+
+How to flash using a MIPS Navigator Probe:
+
+  - Ensure that your Malta has jumper JP1 fitted. Without this jumper you will
+    be unable to flash your Malta using a Navigator Probe.
+
+  - Connect Navigator Console to your probe and Malta as usual.
+
+  - Within Navigator Console run the following commands:
+
+      source /path/to/u-boot/board/malta/flash-malta-boot.tcl
+      reset
+      flash-boot /path/to/u-boot/u-boot.bin
+
+  - You should now be able to reboot your Malta to a U-boot shell.
diff --git a/doc/README.nand b/doc/README.nand
index 913e9b50b8..b91f1985d1 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -104,6 +104,16 @@ Configuration Options:
    CONFIG_SYS_MAX_NAND_DEVICE
       The maximum number of NAND devices you want to support.
 
+   CONFIG_SYS_NAND_MAX_ECCPOS
+      If specified, overrides the maximum number of ECC bytes
+      supported.  Useful for reducing image size, especially with SPL.
+      This must be at least 48 if nand_base.c is used.
+
+   CONFIG_SYS_NAND_MAX_OOBFREE
+      If specified, overrides the maximum number of free OOB regions
+      supported.  Useful for reducing image size, especially with SPL.
+      This must be at least 2 if nand_base.c is used.
+
    CONFIG_SYS_NAND_MAX_CHIPS
       The maximum number of NAND chips per device to be supported.
 
@@ -169,6 +179,59 @@ Configuration Options:
       Please convert your driver even if you don't need the extra
       flexibility, so that one day we can eliminate the old mechanism.
 
+
+   CONFIG_SYS_NAND_ONFI_DETECTION
+	Enables detection of ONFI compliant devices during probe.
+	And fetching device parameters flashed on device, by parsing
+	ONFI parameter page.
+
+   CONFIG_BCH
+	Enables software based BCH ECC algorithm present in lib/bch.c
+	This is used by SoC platforms which do not have built-in ELM
+	hardware engine required for BCH ECC correction.
+
+
+Platform specific options
+=========================
+   CONFIG_NAND_OMAP_GPMC
+	Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
+	GPMC controller is used for parallel NAND flash devices, and can
+	do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
+	and BCH16 ECC algorithms.
+
+   CONFIG_NAND_OMAP_ELM
+	Enables omap_elm.c driver for OMAPx and AMxxxx platforms.
+	ELM controller is used for ECC error detection (not ECC calculation)
+	of BCH4, BCH8 and BCH16 ECC algorithms.
+	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
+	thus such SoC platforms need to depend on software library for ECC error
+	detection. However ECC calculation on such plaforms would still be
+	done by GPMC controller.
+
+   CONFIG_NAND_OMAP_ECCSCHEME
+	On OMAP platforms, this CONFIG specifies NAND ECC scheme.
+	It can take following values:
+	OMAP_ECC_HAM1_CODE_SW
+		1-bit Hamming code using software lib.
+		(for legacy devices only)
+	OMAP_ECC_HAM1_CODE_HW
+		1-bit Hamming code using GPMC hardware.
+		(for legacy devices only)
+	OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
+		4-bit BCH code (unsupported)
+	OMAP_ECC_BCH4_CODE_HW
+		4-bit BCH code (unsupported)
+	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+		8-bit BCH code with
+		- ecc calculation using GPMC hardware engine,
+		- error detection using software library.
+		- requires CONFIG_BCH to enable software BCH library
+		(For legacy device which do not have ELM h/w engine)
+	OMAP_ECC_BCH8_CODE_HW
+		8-bit BCH code with
+		- ecc calculation using GPMC hardware engine,
+		- error detection using ELM hardware engine.
+
 NOTE:
 =====
 
diff --git a/doc/README.omap3 b/doc/README.omap3
index 1fbe79db37..a62c357405 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -161,8 +161,7 @@ BCH8
 
 To enable hardware assisted BCH8 (8-bit BCH [Bose, Chaudhuri, Hocquenghem]) on
 OMAP3 devices we can use the BCH library in lib/bch.c. To do so add CONFIG_BCH
-to enable the library and CONFIG_NAND_OMAP_BCH8 to to enable hardware assisted
-syndrom generation to your board config.
+and set CONFIG_NAND_OMAP_ECCSCHEME=5 (refer README.nand) for selecting BCH8_SW.
 The NAND OOB layout is the same as in linux kernel, if the linux kernel BCH8
 implementation for OMAP3 works for you so the u-boot version should also.
 When you require the SPL to read with BCH8 there are two more configs to
diff --git a/doc/README.p1010rdb b/doc/README.p1010rdb
deleted file mode 100644
index 6b2b5ff3fb..0000000000
--- a/doc/README.p1010rdb
+++ /dev/null
@@ -1,198 +0,0 @@
-Overview
-=========
-The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
-
-The P1010 is a cost-effective, low-power, highly integrated host processor
-based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
-that addresses the requirements of several routing, gateways, storage, consumer,
-and industrial applications. Applications of interest include the main CPUs and
-I/O processors in network attached storage (NAS), the voice over IP (VoIP)
-router/gateway, and wireless LAN (WLAN) and industrial controllers.
-
-The P1010RDB board features are as follows:
-Memory subsystem:
-	- 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
-	- 32 Mbyte NOR flash single-chip memory
-	- 32 Mbyte NAND flash memory
-	- 256 Kbit M24256 I2C EEPROM
-	- 16 Mbyte SPI memory
-	- I2C Board EEPROM 128x8 bit memory
-	- SD/MMC connector to interface with the SD memory card
-Interfaces:
-	- PCIe:
-		- Lane0: x1 mini-PCIe slot
-		- Lane1: x1 PCIe standard slot
-	- SATA:
-		- 1 internal SATA connector to 2.5" 160G SATA2 HDD
-		- 1 eSATA connector to rear panel
-	- 10/100/1000 BaseT Ethernet ports:
-		- eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
-		- eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
-		- eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
-	- USB 2.0 port:
-		- x1 USB2.0 port: via an ULPI PHY to micro-AB connector
-		- x1 USB2.0 poort via an internal PHY to micro-AB connector
-	- FlexCAN ports:
-		- x2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
-		   interface;
-	- DUART interface:
-		- DUART interface: supports two UARTs up to 115200 bps for
-		  console display
-		- J45 connectors are used for these 2 UART ports.
-	- TDM
-		- 2 FXS ports connected via an external SLIC to the TDM
-		   interface. SLIC is controllled via SPI.
-		- 1 FXO port connected via a relay to FXS for switchover to
-		   POTS
-Board connectors:
-	- Mini-ITX power supply connector
-	- JTAG/COP for debugging
-IEEE Std. 1588 signals for test and measurement
-Real-time clock on I2C bus
-POR
-	- support critical POR setting changed via switch on board
-PCB
-	- 6-layer routing (4-layer signals, 2-layer power and ground)
-
-
-Serial Port Configuration on P1010RDB
-=====================================
-Configure the serial port of the attached computer with the following values:
-	-Data rate: 115200 bps
-	-Number of data bits: 8
-	-Parity: None
-	-Number of Stop bits: 1
-	-Flow Control: Hardware/None
-
-
-Settings of DIP-switch
-======================
-  SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
-  SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
-  SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
-Note: 1 stands for 'on', 0 stands for 'off'
-
-
-Setting of hwconfig
-===================
-If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
-"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
-setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
-By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
-is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
-instead of to CAN/UART1.
-
-
-Build and burn u-boot to NOR flash
-==================================
-1. Build u-boot.bin image
-	export ARCH=powerpc
-	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
-	make P1010RDB_NOR
-
-2. Burn u-boot.bin into NOR flash
-	=> tftp $loadaddr $uboot
-	=> protect off eff80000 +$filesize
-	=> erase eff80000 +$filesize
-	=> cp.b $loadaddr eff80000 $filesize
-
-3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
-
-
-Alternate NOR bank
-============================
-1. Burn u-boot.bin into alternate NOR bank
-	=> tftp $loadaddr $uboot
-	=> protect off eef80000 +$filesize
-	=> erase eef80000 +$filesize
-	=> cp.b $loadaddr eef80000 $filesize
-
-2. Switch to alternate NOR bank
-	=> mw.b ffb00009 1
-	=> reset
-	or set SW1[8]= ON
-
-SW1[8]= OFF: Upper bank used for booting start
-SW1[8]= ON:  Lower bank used for booting start
-CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
-0 - boot from upper 4 sectors
-1 - boot from lower 4 sectors
-
-
-Build and burn u-boot to NAND flash
-===================================
-1. Build u-boot.bin image
-	export ARCH=powerpc
-	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
-	make P1010RDB_NAND
-
-2. Burn u-boot-nand.bin into NAND flash
-	=> tftp $loadaddr $uboot-nand
-	=> nand erase 0 $filesize
-	=> nand write $loadaddr 0 $filesize
-
-3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
-
-
-
-Build and burn u-boot to SPI flash
-==================================
-1. Build u-boot-spi.bin image
-	make P1010RDB_SPIFLASH_config; make
-	Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
-	Download u-boot.bin to linux and you can find some config files
-	under /usr/share such as config_xx.dat. Do below command:
-	boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
-			u-boot-spi.bin
-	to generate u-boot-spi.bin.
-
-2. Burn u-boot-spi.bin into SPI flash
-	=> tftp $loadaddr $uboot-spi
-	=> sf erase 0 100000
-	=> sf write $loadaddr 0 $filesize
-
-3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
-
-
-
-CPLD POR setting registers
-==========================
-1. Set POR switch selection register (addr 0xFFB00011) to 0.
-2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
-   proper values.
-   If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
-   switch command by I2C.
-3. Send reset command.
-   After reset, the new POR setting will be implemented.
-
-Two examples are given in below:
-Switch from NOR to NAND boot with default frequency:
-	=> i2c dev 0
-	=> i2c mw 18 1 f9
-	=> i2c mw 18 3 f0
-	=> mw.b ffb00011 0
-	=> mw.b ffb00017 1
-	=> reset
-Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
-	=> i2c dev 0
-	=> i2c mw 18 1 f1
-	=> i2c mw 18 3 f0
-	=> mw.b ffb00011 0
-	=> mw.b ffb00014 2
-	=> mw.b ffb00015 5
-	=> mw.b ffb00016 3
-	=> mw.b ffb00017 f
-	=> reset
-
-
-Boot Linux from network using TFTP on P1010RDB
-==============================================
-Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
-	=> tftp 1000000 uImage
-	=> tftp 2000000 p1010rdb.dtb
-	=> tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
-	=> bootm 1000000 3000000 2000000
-
-
-Please contact your local field applications engineer or sales representative
-to obtain related documents, such as P1010-RDB User Guide for details.
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index a48ce7c866..604de0c8a7 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ easily if here is something they might want to dig for...
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
 omap730p2        arm         arm926ejs      -           2013-11-11
+pn62             powerpc     mpc824x        -           2013-11-11  Wolfgang Grandegger <wg@grandegger.com>
 pdnb3            arm         ixp            304db0b     2013-09-24  Stefan Roese <sr@denx.de>
 scpu             arm         ixp            304db0b     2013-09-24  Stefan Roese <sr@denx.de>
 omap1510inn      arm         arm925t        0610a16     2013-09-23  Kshitij Gupta <kshitij@ti.com>
@@ -103,3 +104,4 @@ CPCI440          powerpc     440GP          b568fd2     2007-12-27  Matthias Fuc
 PCIPPC2          powerpc     MPC740/MPC750  7c9e89b     2013-02-07  Wolfgang Denk <wd@denx.de>
 PCIPPC6          powerpc     MPC740/MPC750  -           -           Wolfgang Denk <wd@denx.de>
 omap2420h4       arm         omap24xx       -           2013-06-04  Richard Woodruff <r-woodruff2@ti.com>
+eNET             x86         x86            7e8c53d     2013-02-14  Graeme Russ <graeme.russ@gmail.com>