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authorTom Rini <trini@konsulko.com>2018-10-11 15:28:32 -0400
committerTom Rini <trini@konsulko.com>2018-10-11 15:28:32 -0400
commit0223462b373b975d970fa86e5e1a7eadd1d41820 (patch)
tree65f798468bfb9cdf3c4c2a99bd88df9108ccd4df /doc
parent3d5ced9e22d32112a20f9dc0f5fb1f22ef088079 (diff)
parent1a048cd65645338069d591108031fa4ebe96d53f (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-net
Diffstat (limited to 'doc')
-rw-r--r--doc/device-tree-bindings/net/ti,dp83867.txt8
1 files changed, 8 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt
index cb77fdf082..034146f5f8 100644
--- a/doc/device-tree-bindings/net/ti,dp83867.txt
+++ b/doc/device-tree-bindings/net/ti,dp83867.txt
@@ -8,6 +8,12 @@ Required properties:
for applicable values
- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
for applicable values
+ - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
+ compensate for the board being designed with the lanes swapped.
+ - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
+ TX/RX lanes.
+ - ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h
+ for applicable values
Default child nodes are standard Ethernet PHY device
nodes as described in doc/devicetree/bindings/net/ethernet.txt
@@ -19,6 +25,8 @@ Example:
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ enet-phy-lane-no-swap;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
};
Datasheet can be found: