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authorPeter Robinson <pbrobinson@gmail.com>2021-12-21 12:32:47 +0000
committerTom Rini <trini@konsulko.com>2022-01-07 09:30:44 -0500
commit2bbe1ba0c712c3eb1670952efa3351f501959eb3 (patch)
treef48f935ae34326aac2fa59716b2ce7df899d0a04 /board/udoo
parent4be9947edf68650db0c68d7c212f98a7cd1dfbdd (diff)
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udoo_neo: Fixes for booting from the mSD card
This fixes booting from the mSD card from both SPL and when using it for the OS booting. It also cleans up a few mmc booting bits that are no longer needed. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Diffstat (limited to 'board/udoo')
-rw-r--r--board/udoo/neo/neo.c40
1 files changed, 40 insertions, 0 deletions
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
index 61195be744..8b0d13b1ca 100644
--- a/board/udoo/neo/neo.c
+++ b/board/udoo/neo/neo.c
@@ -19,6 +19,8 @@
#include <asm/mach-imx/iomux-v3.h>
#include <dm.h>
#include <env.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/mach-imx/mxc_i2c.h>
@@ -214,6 +216,19 @@ static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* CD pin */
+ MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* Power */
+ MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
static iomux_v3_cfg_t const phy_control_pads[] = {
/* 25MHz Ethernet PHY Clock */
MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
@@ -327,6 +342,31 @@ int board_early_init_f(void)
return 0;
}
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC2_BASE_ADDR},
+};
+
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
+#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return !gpio_get_value(USDHC2_CD_GPIO);
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+ SETUP_IOMUX_PADS(usdhc2_pads);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ gpio_request(IMX_GPIO_NR(6, 1), "usdhc2_pwr");
+ gpio_request(IMX_GPIO_NR(6, 2), "usdhc2_cd");
+ gpio_direction_input(USDHC2_CD_GPIO);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
static char *board_string(void)
{
switch (get_board_value()) {