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| author | Baruch Siach <baruch@tkos.co.il> | 2020-01-20 14:20:07 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2020-01-21 08:31:49 +0100 |
| commit | 66646fa89365594999af710a9885a6d5d7a0f7e8 (patch) | |
| tree | b9c64d1b3e2957b0522ed1ba5fbaa6a8f2cf1e3e /board/solidrun | |
| parent | d67b98ed4790a30da9bdd337cfb76b03aac993e3 (diff) | |
| download | u-boot-66646fa89365594999af710a9885a6d5d7a0f7e8.tar.gz u-boot-66646fa89365594999af710a9885a6d5d7a0f7e8.tar.bz2 u-boot-66646fa89365594999af710a9885a6d5d7a0f7e8.zip | |
arm: mvebu: clearfog: enable both DDR clocks
Enabled both DDR clock signals to support Clearfog variants (currently,
Clearfog GTR) that need both clocks.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Diffstat (limited to 'board/solidrun')
| -rw-r--r-- | board/solidrun/clearfog/clearfog.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 03724fee10..8b63811946 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -68,7 +68,10 @@ static struct mv_ddr_topology_map board_topology_map = { BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ - {0} /* timing parameters */ + {0}, /* timing parameters */ + { {0} }, /* electrical configuration */ + {0,}, /* electrical parameters */ + 0x3, /* clock enable mask */ }; struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) |