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authorOleh Kravchenko <oleg@kaa.org.ua>2021-05-15 00:18:33 +0300
committerStefano Babic <sbabic@denx.de>2021-06-09 13:32:49 +0200
commit1180baec98147e05a8b3b36199ae22010a4d4fe7 (patch)
tree13bc623d4e06f708d3ec30d142bb137d0588e086 /board/out4
parent3675ac081ad5129cbcb22b06fb6d8e3264a30d20 (diff)
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Add EV-iMX280-NANO-X-MB board
A simple prototyping board with one microSD port, one Ethernet port, 2 USB ports, I2C, SPI, GPIO, and UART interfaces. Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua> Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/out4')
-rw-r--r--board/out4/o4-imx6ull-nano/Kconfig7
-rw-r--r--board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c22
2 files changed, 19 insertions, 10 deletions
diff --git a/board/out4/o4-imx6ull-nano/Kconfig b/board/out4/o4-imx6ull-nano/Kconfig
index c2497d521f..e2ab80b6d4 100644
--- a/board/out4/o4-imx6ull-nano/Kconfig
+++ b/board/out4/o4-imx6ull-nano/Kconfig
@@ -45,6 +45,12 @@ config O4_IMX_NANO
A baseboard for EV-iMX280-NANO module:
https://out4.ru/products/board/18-o4-imx-nano.html
+config EV_IMX280_NANO_X_MB
+ bool "EV-IMX280-NANO-X-MB"
+ help
+ A simple baseboard for EV-iMX280-NANO module:
+ http://evodbg.net/products/mx28-eval-kits/14-ev-imx280-nano-x-mb.html
+
endchoice
config IMX_CONFIG
@@ -53,5 +59,6 @@ config IMX_CONFIG
config DEFAULT_DEVICE_TREE
default "o4-imx-nano" if O4_IMX_NANO
+ default "ev-imx280-nano-x-mb" if EV_IMX280_NANO_X_MB
endif
diff --git a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c
index fec1755c32..edb200e9e5 100644
--- a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c
+++ b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c
@@ -39,16 +39,18 @@ static int setup_fec_clock(void)
if (ret)
return ret;
- /*
- * Use 50M anatop loopback REF_CLK2 for ENET2,
- * clear gpr1[14], set gpr1[18].
- */
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
- IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
-
- ret = enable_fec_anatop_clock(1, ENET_50MHZ);
- if (ret)
- return ret;
+ if (!IS_ENABLED(CONFIG_EV_IMX280_NANO_X_MB)) {
+ /*
+ * Use 50M anatop loopback REF_CLK2 for ENET2,
+ * clear gpr1[14], set gpr1[18].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+ IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+ ret = enable_fec_anatop_clock(1, ENET_50MHZ);
+ if (ret)
+ return ret;
+ }
enable_enet_clk(1);
}