ppc: Remove gdsys strider boards

These boards have not been converted to CONFIG_DM_MMC, along with other
DM conversions, by the deadline.  Remove them.

Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Tom Rini <trini@konsulko.com>

9 files changed, 1 insertions, 861 deletions

diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index 7dfe104561..fa4c65c634 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -7,10 +7,6 @@ obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
 obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
 obj-$(CONFIG_CONTROLCENTERD) += dp501.o
 obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
-obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
-obj-$(CONFIG_TARGET_STRIDER) += fanctrl.o
-obj-$(CONFIG_STRIDER_CON) += osd.o
-obj-$(CONFIG_STRIDER_CON_DP) += osd.o
 obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o
 
 ifdef CONFIG_OSD
diff --git a/board/gdsys/common/adv7611.c b/board/gdsys/common/adv7611.c
deleted file mode 100644
index 06cdc05825..0000000000
--- a/board/gdsys/common/adv7611.c
+++ /dev/null
@@ -1,180 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2014
- * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
- */
-
-#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
-
-#include <common.h>
-#include <i2c.h>
-
-#define ADV7611_I2C_ADDR 0x4c
-#define ADV7611_RDINFO 0x2051
-
-/*
- * ADV7611 I2C Addresses in u-boot notation
- */
-enum {
-	CP_I2C_ADDR = 0x22,
-	DPLL_I2C_ADDR = 0x26,
-	KSV_I2C_ADDR = 0x32,
-	HDMI_I2C_ADDR = 0x34,
-	EDID_I2C_ADDR = 0x36,
-	INFOFRAME_I2C_ADDR = 0x3e,
-	CEC_I2C_ADDR = 0x40,
-	IO_I2C_ADDR = ADV7611_I2C_ADDR,
-};
-
-/*
- * Global Control Registers
- */
-enum {
-	IO_RD_INFO_MSB = 0xea,
-	IO_RD_INFO_LSB = 0xeb,
-	IO_CEC_ADDR = 0xf4,
-	IO_INFOFRAME_ADDR = 0xf5,
-	IO_DPLL_ADDR = 0xf8,
-	IO_KSV_ADDR = 0xf9,
-	IO_EDID_ADDR = 0xfa,
-	IO_HDMI_ADDR = 0xfb,
-	IO_CP_ADDR = 0xfd,
-};
-
-int adv7611_i2c[] = CONFIG_SYS_ADV7611_I2C;
-
-int adv7611_probe(unsigned int screen)
-{
-	int old_bus = i2c_get_bus_num();
-	unsigned int rd_info;
-	int res = 0;
-
-	i2c_set_bus_num(adv7611_i2c[screen]);
-
-	rd_info = (i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_MSB) << 8)
-		  | i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_LSB);
-
-	if (rd_info != ADV7611_RDINFO) {
-		res = -1;
-		goto out;
-	}
-
-	/*
-	 * set I2C addresses to default values
-	 */
-	i2c_reg_write(IO_I2C_ADDR, IO_CEC_ADDR, CEC_I2C_ADDR << 1);
-	i2c_reg_write(IO_I2C_ADDR, IO_INFOFRAME_ADDR, INFOFRAME_I2C_ADDR << 1);
-	i2c_reg_write(IO_I2C_ADDR, IO_DPLL_ADDR, DPLL_I2C_ADDR << 1);
-	i2c_reg_write(IO_I2C_ADDR, IO_KSV_ADDR, KSV_I2C_ADDR << 1);
-	i2c_reg_write(IO_I2C_ADDR, IO_EDID_ADDR, EDID_I2C_ADDR << 1);
-	i2c_reg_write(IO_I2C_ADDR, IO_HDMI_ADDR, HDMI_I2C_ADDR << 1);
-	i2c_reg_write(IO_I2C_ADDR, IO_CP_ADDR, CP_I2C_ADDR << 1);
-
-	/*
-	 * do magic initialization sequence from
-	 * "ADV7611 Register Settings Recommendations Revision 1.5"
-	 * with most registers undocumented
-	 */
-	i2c_reg_write(CP_I2C_ADDR, 0x6c, 0x00);
-	i2c_reg_write(HDMI_I2C_ADDR, 0x9b, 0x03);
-	i2c_reg_write(HDMI_I2C_ADDR, 0x6f, 0x08);
-	i2c_reg_write(HDMI_I2C_ADDR, 0x85, 0x1f);
-	i2c_reg_write(HDMI_I2C_ADDR, 0x87, 0x70);
-	i2c_reg_write(HDMI_I2C_ADDR, 0x57, 0xda);
-	i2c_reg_write(HDMI_I2C_ADDR, 0x58, 0x01);
-	i2c_reg_write(HDMI_I2C_ADDR, 0x03, 0x98);
-	i2c_reg_write(HDMI_I2C_ADDR, 0x4c, 0x44);
-
-	/*
-	 * IO_REG_02, default 0xf0
-	 *
-	 * INP_COLOR_SPACE (IO, Address 0x02[7:4])
-	 * default: 0b1111 auto
-	 * set to : 0b0001 force RGB (range 0 to 255) input
-	 *
-	 * RGB_OUT (IO, Address 0x02[1])
-	 * default: 0 YPbPr color space output
-	 * set to : 1 RGB color space output
-	 */
-	i2c_reg_write(IO_I2C_ADDR, 0x02, 0x12);
-
-	/*
-	 * IO_REG_03, default 0x00
-	 *
-	 * OP_FORMAT_SEL (IO, Address 0x03[7:0])
-	 * default: 0x00 8-bit SDR ITU-656 mode
-	 * set to : 0x40 24-bit 4:4:4 SDR mode
-	 */
-	i2c_reg_write(IO_I2C_ADDR, 0x03, 0x40);
-
-	/*
-	 * IO_REG_05, default 0x2c
-	 *
-	 * AVCODE_INSERT_EN (IO, Address 0x05[2])
-	 * default: 1 insert AV codes into data stream
-	 * set to : 0 do not insert AV codes into data stream
-	 */
-	i2c_reg_write(IO_I2C_ADDR, 0x05, 0x28);
-
-	/*
-	 * IO_REG_0C, default 0x62
-	 *
-	 * POWER_DOWN (IO, Address 0x0C[5])
-	 * default: 1 chip is powered down
-	 * set to : 0 chip is operational
-	 */
-	i2c_reg_write(IO_I2C_ADDR, 0x0c, 0x42);
-
-	/*
-	 * IO_REG_15, default 0xbe
-	 *
-	 * TRI_SYNCS (IO, Address 0x15[3)
-	 * TRI_LLC (IO, Address 0x15[2])
-	 * TRI_PIX (IO, Address 0x15[1])
-	 * default: 1 video output pins are tristate
-	 * set to : 0 video output pins are active
-	 */
-	i2c_reg_write(IO_I2C_ADDR, 0x15, 0xb0);
-
-	/*
-	 * HDMI_REGISTER_02H, default 0xff
-	 *
-	 * CLOCK_TERMA_DISABLE (HDMI, Address 0x83[0])
-	 * default: 1 disable termination
-	 * set to : 0 enable termination
-	 * Future options are:
-	 * - use the chips automatic termination control
-	 * - set this manually on cable detect
-	 * but at the moment this seems a safe default.
-	 */
-	i2c_reg_write(HDMI_I2C_ADDR, 0x83, 0xfe);
-
-	/*
-	 * HDMI_CP_CNTRL_1, default 0x01
-	 *
-	 * HDMI_FRUN_EN (CP, Address 0xBA[0])
-	 * default: 1 Enable the free run feature in HDMI mode
-	 * set to : 0 Disable the free run feature in HDMI mode
-	 */
-	i2c_reg_write(CP_I2C_ADDR, 0xba, 0x00);
-
-	/*
-	 * INT1_CONFIGURATION, default 0x20
-	 *
-	 * INTRQ_DUR_SEL[1:0] (IO, Address 0x40[7:6])
-	 * default: 00 Interrupt signal is active for 4 Xtal periods
-	 * set to : 11 Active until cleared
-	 *
-	 * INTRQ_OP_SEL[1:0] (IO, Address 0x40[1:0])
-	 * default: 00 Open drain
-	 * set to : 10 Drives high when active
-	 */
-	i2c_reg_write(IO_I2C_ADDR, 0x40, 0xc2);
-
-out:
-	i2c_set_bus_num(old_bus);
-
-	return res;
-}
-
-#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/board/gdsys/common/adv7611.h b/board/gdsys/common/adv7611.h
deleted file mode 100644
index 7b4e27c6bc..0000000000
--- a/board/gdsys/common/adv7611.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2014
- * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
- */
-
-#ifndef _ADV7611_H_
-#define _ADV7611_H_
-
-int adv7611_probe(unsigned int screen);
-
-#endif
diff --git a/board/gdsys/common/ch7301.c b/board/gdsys/common/ch7301.c
deleted file mode 100644
index 5e42467651..0000000000
--- a/board/gdsys/common/ch7301.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2014
- * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
- */
-
-/* Chrontel CH7301C DVI Transmitter */
-
-#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
-
-#include <common.h>
-#include <asm/io.h>
-#include <errno.h>
-#include <i2c.h>
-
-#define CH7301_I2C_ADDR 0x75
-
-enum {
-	CH7301_CM = 0x1c,		/* Clock Mode Register */
-	CH7301_IC = 0x1d,		/* Input Clock Register */
-	CH7301_GPIO = 0x1e,		/* GPIO Control Register */
-	CH7301_IDF = 0x1f,		/* Input Data Format Register */
-	CH7301_CD = 0x20,		/* Connection Detect Register */
-	CH7301_DC = 0x21,		/* DAC Control Register */
-	CH7301_HPD = 0x23,		/* Hot Plug Detection Register */
-	CH7301_TCTL = 0x31,		/* DVI Control Input Register */
-	CH7301_TPCP = 0x33,		/* DVI PLL Charge Pump Ctrl Register */
-	CH7301_TPD = 0x34,		/* DVI PLL Divide Register */
-	CH7301_TPVT = 0x35,		/* DVI PLL Supply Control Register */
-	CH7301_TPF = 0x36,		/* DVI PLL Filter Register */
-	CH7301_TCT = 0x37,		/* DVI Clock Test Register */
-	CH7301_TSTP = 0x48,		/* Test Pattern Register */
-	CH7301_PM = 0x49,		/* Power Management register */
-	CH7301_VID = 0x4a,		/* Version ID Register */
-	CH7301_DID = 0x4b,		/* Device ID Register */
-	CH7301_DSP = 0x56,		/* DVI Sync polarity Register */
-};
-
-int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
-
-int ch7301_probe(unsigned screen, bool power)
-{
-	u8 value;
-
-	i2c_set_bus_num(ch7301_i2c[screen]);
-	if (i2c_probe(CH7301_I2C_ADDR))
-		return -1;
-
-	value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
-	if (value != 0x17)
-		return -1;
-
-	if (power) {
-		i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
-		i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
-		i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
-		i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
-		i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
-	} else {
-		i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x00);
-		i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0x01);
-	}
-
-	return 0;
-}
-
-#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/board/gdsys/common/ch7301.h b/board/gdsys/common/ch7301.h
deleted file mode 100644
index e0e8a9e9d4..0000000000
--- a/board/gdsys/common/ch7301.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2014
- * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
- */
-
-#ifndef _CH7301_H_
-#define _CH7301_H_
-
-int ch7301_probe(unsigned screen, bool power);
-
-#endif
diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig
index 30811889fb..1c33f0c982 100644
--- a/board/gdsys/mpc8308/Kconfig
+++ b/board/gdsys/mpc8308/Kconfig
@@ -52,25 +52,6 @@ config GDSYS_LEGACY_DRIVERS
 
 endif
 
-if TARGET_STRIDER
-
-config SYS_BOARD
-	default "mpc8308"
-
-config SYS_VENDOR
-	default "gdsys"
-
-config SYS_CONFIG_NAME
-	default "strider"
-
-config GDSYS_LEGACY_OSD_CMDS
-	default y
-
-config GDSYS_LEGACY_DRIVERS
-	default y
-
-endif
-
 if TARGET_GAZERBEAM
 
 config SYS_BOARD
@@ -92,7 +73,7 @@ config GDSYS_LEGACY_OSD_CMDS
 	default y
 endif
 
-if TARGET_HRCON || TARGET_STRIDER || TARGET_GAZERBEAM
+if TARGET_HRCON || TARGET_GAZERBEAM
 
 choice
 	prompt "FPGA flavor selection"
diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS
index ed1b6fa106..cc0fbebccd 100644
--- a/board/gdsys/mpc8308/MAINTAINERS
+++ b/board/gdsys/mpc8308/MAINTAINERS
@@ -5,10 +5,4 @@ F:	board/gdsys/mpc8308/
 F:	include/configs/hrcon.h
 F:	configs/hrcon_defconfig
 F:	configs/hrcon_dh_defconfig
-F:	include/configs/strider.h
-F:	configs/strider_defconfig
-F:	configs/strider_cpu_defconfig
-F:	configs/strider_cpu_dp_defconfig
-F:	configs/strider_con_defconfig
-F:	configs/strider_con_dp_defconfig
 F:	configs/gazerbeam_defconfig
diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile
index 9af5fe04d1..578b36653d 100644
--- a/board/gdsys/mpc8308/Makefile
+++ b/board/gdsys/mpc8308/Makefile
@@ -5,5 +5,4 @@
 
 obj-y := mpc8308.o sdram.o
 obj-$(CONFIG_TARGET_HRCON) += hrcon.o
-obj-$(CONFIG_TARGET_STRIDER) += strider.o
 obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o
diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c
deleted file mode 100644
index 91fec74fb0..0000000000
--- a/board/gdsys/mpc8308/strider.c
+++ /dev/null
@@ -1,559 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2014
- * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
- */
-
-#include <common.h>
-#include <env.h>
-#include <flash.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <init.h>
-#include <spi.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <fsl_esdhc.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-
-#include "mpc8308.h"
-
-#include <gdsys_fpga.h>
-
-#include "../common/adv7611.h"
-#include "../common/ch7301.h"
-#include "../common/dp501.h"
-#include "../common/ioep-fpga.h"
-#include "../common/mclink.h"
-#include "../common/osd.h"
-#include "../common/phy.h"
-#include "../common/fanctrl.h"
-
-#include <pca953x.h>
-#include <pca9698.h>
-
-#include <miiphy.h>
-
-#define MAX_MUX_CHANNELS 2
-
-enum {
-	MCFPGA_DONE = 1 << 0,
-	MCFPGA_INIT_N = 1 << 1,
-	MCFPGA_PROGRAM_N = 1 << 2,
-	MCFPGA_UPDATE_ENABLE_N = 1 << 3,
-	MCFPGA_RESET_N = 1 << 4,
-};
-
-enum {
-	GPIO_MDC = 1 << 14,
-	GPIO_MDIO = 1 << 15,
-};
-
-uint mclink_fpgacount;
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-struct {
-	u8 bus;
-	u8 addr;
-} strider_fans[] = CONFIG_STRIDER_FANS;
-
-int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
-{
-	int res;
-
-	switch (fpga) {
-	case 0:
-		out_le16(reg, data);
-		break;
-	default:
-		res = mclink_send(fpga - 1, regoff, data);
-		if (res < 0) {
-			printf("mclink_send reg %02lx data %04x returned %d\n",
-			       regoff, data, res);
-			return res;
-		}
-		break;
-	}
-
-	return 0;
-}
-
-int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
-{
-	int res;
-
-	switch (fpga) {
-	case 0:
-		*data = in_le16(reg);
-		break;
-	default:
-		if (fpga > mclink_fpgacount)
-			return -EINVAL;
-		res = mclink_receive(fpga - 1, regoff, data);
-		if (res < 0) {
-			printf("mclink_receive reg %02lx returned %d\n",
-			       regoff, res);
-			return res;
-		}
-	}
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char *s = env_get("serial#");
-	bool hw_type_cat = pca9698_get_value(0x20, 18);
-
-	puts("Board: ");
-
-	printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
-
-	if (s) {
-		puts(", serial# ");
-		puts(s);
-	}
-
-	puts("\n");
-
-	return 0;
-}
-
-int last_stage_init(void)
-{
-	int slaves;
-	uint k;
-	uint mux_ch;
-	uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
-#ifdef CONFIG_STRIDER_CPU
-	uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
-#endif
-	bool hw_type_cat = pca9698_get_value(0x20, 18);
-#ifdef CONFIG_STRIDER_CON_DP
-	bool is_dh = pca9698_get_value(0x20, 25);
-#endif
-	bool ch0_sgmii2_present;
-
-	/* Turn on Analog Devices ADV7611 */
-	pca9698_direction_output(0x20, 8, 0);
-
-	/* Turn on Parade DP501 */
-	pca9698_direction_output(0x20, 10, 1);
-	pca9698_direction_output(0x20, 11, 1);
-
-	ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
-
-	/* wait for FPGA done, then reset FPGA */
-	for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
-		uint ctr = 0;
-		uchar *mclink_controllers = mclink_controllers_dvi;
-
-#ifdef CONFIG_STRIDER_CPU
-		if (i2c_probe(mclink_controllers[k])) {
-			mclink_controllers = mclink_controllers_dp;
-			if (i2c_probe(mclink_controllers[k]))
-				continue;
-		}
-#else
-		if (i2c_probe(mclink_controllers[k]))
-			continue;
-#endif
-		while (!(pca953x_get_val(mclink_controllers[k])
-		       & MCFPGA_DONE)) {
-			mdelay(100);
-			if (ctr++ > 5) {
-				printf("no done for mclink_controller %d\n", k);
-				break;
-			}
-		}
-
-		pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
-		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
-		udelay(10);
-		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
-				MCFPGA_RESET_N);
-	}
-
-	if (hw_type_cat) {
-		int retval;
-		struct mii_dev *mdiodev = mdio_alloc();
-
-		if (!mdiodev)
-			return -ENOMEM;
-		strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
-		mdiodev->read = bb_miiphy_read;
-		mdiodev->write = bb_miiphy_write;
-
-		retval = mdio_register(mdiodev);
-		if (retval < 0)
-			return retval;
-		for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
-			if ((mux_ch == 1) && !ch0_sgmii2_present)
-				continue;
-
-			setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
-		}
-	}
-
-	/* give slave-PLLs and Parade DP501 some time to be up and running */
-	mdelay(500);
-
-	mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
-	slaves = mclink_probe();
-	mclink_fpgacount = 0;
-
-	ioep_fpga_print_info(0);
-
-	if (!adv7611_probe(0))
-		printf("       Advantiv ADV7611 HDMI Receiver\n");
-
-#ifdef CONFIG_STRIDER_CON
-	if (ioep_fpga_has_osd(0))
-		osd_probe(0);
-#endif
-
-#ifdef CONFIG_STRIDER_CON_DP
-	if (ioep_fpga_has_osd(0)) {
-		osd_probe(0);
-		if (is_dh)
-			osd_probe(4);
-	}
-#endif
-
-#ifdef CONFIG_STRIDER_CPU
-	ch7301_probe(0, false);
-	dp501_probe(0, false);
-#endif
-
-	if (slaves <= 0)
-		return 0;
-
-	mclink_fpgacount = slaves;
-
-#ifdef CONFIG_STRIDER_CPU
-	/* get ADV7611 out of reset, power up DP501, give some time to wakeup */
-	for (k = 1; k <= slaves; ++k)
-		FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
-
-	mdelay(500);
-#endif
-
-	for (k = 1; k <= slaves; ++k) {
-		ioep_fpga_print_info(k);
-#ifdef CONFIG_STRIDER_CON
-		if (ioep_fpga_has_osd(k))
-			osd_probe(k);
-#endif
-#ifdef CONFIG_STRIDER_CON_DP
-		if (ioep_fpga_has_osd(k)) {
-			osd_probe(k);
-			if (is_dh)
-				osd_probe(k + 4);
-		}
-#endif
-#ifdef CONFIG_STRIDER_CPU
-		if (!adv7611_probe(k))
-			printf("       Advantiv ADV7611 HDMI Receiver\n");
-		ch7301_probe(k, false);
-		dp501_probe(k, false);
-#endif
-		if (hw_type_cat) {
-			int retval;
-			struct mii_dev *mdiodev = mdio_alloc();
-
-			if (!mdiodev)
-				return -ENOMEM;
-			strncpy(mdiodev->name, bb_miiphy_buses[k].name,
-				MDIO_NAME_LEN);
-			mdiodev->read = bb_miiphy_read;
-			mdiodev->write = bb_miiphy_write;
-
-			retval = mdio_register(mdiodev);
-			if (retval < 0)
-				return retval;
-			setup_88e1514(bb_miiphy_buses[k].name, 0);
-		}
-	}
-
-	for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
-		i2c_set_bus_num(strider_fans[k].bus);
-		init_fan_controller(strider_fans[k].addr);
-	}
-
-	return 0;
-}
-
-/*
- * provide access to fpga gpios (for I2C bitbang)
- * (these may look all too simple but make iocon.h much more readable)
- */
-void fpga_gpio_set(uint bus, int pin)
-{
-	FPGA_SET_REG(bus, gpio.set, pin);
-}
-
-void fpga_gpio_clear(uint bus, int pin)
-{
-	FPGA_SET_REG(bus, gpio.clear, pin);
-}
-
-int fpga_gpio_get(uint bus, int pin)
-{
-	u16 val;
-
-	FPGA_GET_REG(bus, gpio.read, &val);
-
-	return val & pin;
-}
-
-#ifdef CONFIG_STRIDER_CON_DP
-void fpga_control_set(uint bus, int pin)
-{
-	u16 val;
-
-	FPGA_GET_REG(bus, control, &val);
-	FPGA_SET_REG(bus, control, val | pin);
-}
-
-void fpga_control_clear(uint bus, int pin)
-{
-	u16 val;
-
-	FPGA_GET_REG(bus, control, &val);
-	FPGA_SET_REG(bus, control, val & ~pin);
-}
-#endif
-
-void mpc8308_init(void)
-{
-	pca9698_direction_output(0x20, 26, 1);
-}
-
-void mpc8308_set_fpga_reset(uint state)
-{
-	pca9698_set_value(0x20, 26, state ? 0 : 1);
-}
-
-void mpc8308_setup_hw(void)
-{
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
-	/*
-	 * set "startup-finished"-gpios
-	 */
-	setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
-	setbits_gpio0_out(BIT(31 - 12));
-}
-
-int mpc8308_get_fpga_done(uint fpga)
-{
-	return pca9698_get_value(0x20, 20);
-}
-
-#ifdef CONFIG_FSL_ESDHC
-int board_mmc_init(struct bd_info *bd)
-{
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	sysconf83xx_t *sysconf = &immr->sysconf;
-
-	/* Enable cache snooping in eSDHC system configuration register */
-	out_be32(&sysconf->sdhccr, 0x02000000);
-
-	return fsl_esdhc_mmc_init(bd);
-}
-#endif
-
-static struct pci_region pcie_regions_0[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
-		.size = CONFIG_SYS_PCIE1_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-void pci_init_board(void)
-{
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	sysconf83xx_t *sysconf = &immr->sysconf;
-	law83xx_t *pcie_law = sysconf->pcielaw;
-	struct pci_region *pcie_reg[] = { pcie_regions_0 };
-
-	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
-			 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-
-	/* Deassert the resets in the control register */
-	out_be32(&sysconf->pecr1, 0xE0008000);
-	udelay(2000);
-
-	/* Configure PCI Express Local Access Windows */
-	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	mpc83xx_pcie_init(1, pcie_reg);
-}
-
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
-	info->portwidth = FLASH_CFI_16BIT;
-	info->chipwidth = FLASH_CFI_BY16;
-	info->interface = FLASH_CFI_X16;
-	return 1;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-	fsl_fdt_fixup_dr_usb(blob, bd);
-	fdt_fixup_esdhc(blob, bd);
-
-	return 0;
-}
-#endif
-
-/*
- * FPGA MII bitbang implementation
- */
-
-struct fpga_mii {
-	uint fpga;
-	int mdio;
-} fpga_mii[] = {
-	{ 0, 1},
-	{ 1, 1},
-	{ 2, 1},
-	{ 3, 1},
-};
-
-static int mii_dummy_init(struct bb_miiphy_bus *bus)
-{
-	return 0;
-}
-
-static int mii_mdio_active(struct bb_miiphy_bus *bus)
-{
-	struct fpga_mii *fpga_mii = bus->priv;
-
-	if (fpga_mii->mdio)
-		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
-	else
-		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
-
-	return 0;
-}
-
-static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
-{
-	struct fpga_mii *fpga_mii = bus->priv;
-
-	FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
-
-	return 0;
-}
-
-static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
-{
-	struct fpga_mii *fpga_mii = bus->priv;
-
-	if (v)
-		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
-	else
-		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
-
-	fpga_mii->mdio = v;
-
-	return 0;
-}
-
-static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
-{
-	u16 gpio;
-	struct fpga_mii *fpga_mii = bus->priv;
-
-	FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
-
-	*v = ((gpio & GPIO_MDIO) != 0);
-
-	return 0;
-}
-
-static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
-{
-	struct fpga_mii *fpga_mii = bus->priv;
-
-	if (v)
-		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
-	else
-		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
-
-	return 0;
-}
-
-static int mii_delay(struct bb_miiphy_bus *bus)
-{
-	udelay(1);
-
-	return 0;
-}
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
-	{
-		.name = "board0",
-		.init = mii_dummy_init,
-		.mdio_active = mii_mdio_active,
-		.mdio_tristate = mii_mdio_tristate,
-		.set_mdio = mii_set_mdio,
-		.get_mdio = mii_get_mdio,
-		.set_mdc = mii_set_mdc,
-		.delay = mii_delay,
-		.priv = &fpga_mii[0],
-	},
-	{
-		.name = "board1",
-		.init = mii_dummy_init,
-		.mdio_active = mii_mdio_active,
-		.mdio_tristate = mii_mdio_tristate,
-		.set_mdio = mii_set_mdio,
-		.get_mdio = mii_get_mdio,
-		.set_mdc = mii_set_mdc,
-		.delay = mii_delay,
-		.priv = &fpga_mii[1],
-	},
-	{
-		.name = "board2",
-		.init = mii_dummy_init,
-		.mdio_active = mii_mdio_active,
-		.mdio_tristate = mii_mdio_tristate,
-		.set_mdio = mii_set_mdio,
-		.get_mdio = mii_get_mdio,
-		.set_mdc = mii_set_mdc,
-		.delay = mii_delay,
-		.priv = &fpga_mii[2],
-	},
-	{
-		.name = "board3",
-		.init = mii_dummy_init,
-		.mdio_active = mii_mdio_active,
-		.mdio_tristate = mii_mdio_tristate,
-		.set_mdio = mii_set_mdio,
-		.get_mdio = mii_get_mdio,
-		.set_mdc = mii_set_mdc,
-		.delay = mii_delay,
-		.priv = &fpga_mii[3],
-	},
-};
-
-int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);