diff options
| author | Matthias Fuchs <matthias.fuchs@esd-electronics.com> | 2008-12-10 15:12:56 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-12-10 17:20:03 +0100 |
| commit | 5b67a1439a73ba6c34007d9ff60a2c6aa90265df (patch) | |
| tree | cd49517797f918b0ae7628ce6e5b083eac80ed01 /board/esd/pmc440 | |
| parent | 1951f847f0a851853871b613ad7cf21a5242226c (diff) | |
| download | u-boot-5b67a1439a73ba6c34007d9ff60a2c6aa90265df.tar.gz u-boot-5b67a1439a73ba6c34007d9ff60a2c6aa90265df.tar.bz2 u-boot-5b67a1439a73ba6c34007d9ff60a2c6aa90265df.zip | |
ppc4xx: Fix Ethernet PHY LED configuration on PMC440 boards
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Diffstat (limited to 'board/esd/pmc440')
| -rw-r--r-- | board/esd/pmc440/pmc440.c | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 8563d7d5f2..4d81c33a82 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -755,17 +755,31 @@ int post_hotkeys_pressed(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { + char *s; + unsigned short val_method, val_behavior; + + /* special LED setup for NGCC/CANDES */ + if ((s = getenv("bd_type")) && + ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) { + val_method = 0x0e0a; + val_behavior = 0x0cf2; + } else { + /* PMC440 standard type */ + val_method = 0x0e10; + val_behavior = 0x0cf0; + } + if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) { miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010); - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0); - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method); miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000); } if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) { miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010); - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0); - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10); + miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior); + miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method); miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000); } } |