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authorChristophe Leroy <christophe.leroy@csgroup.eu>2024-04-14 16:47:06 +0200
committerChristophe Leroy <christophe.leroy@csgroup.eu>2024-04-18 15:47:46 +0200
commit741e30e8c2b837dc92ee2eedec5478afdd83a316 (patch)
tree64f766d513a8cc88be675e66e695fc5b95511c78 /board/cssi
parent313ffe2746b6d89a34aab9a844a1753538564ffa (diff)
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board: cssi: Read and display MCR board address
MCR boards are plugged in racks. The position in the rack can be read in a register. For MCR3000, that's provided by the FPGA so check it is loaded before reading the address. For the other boards, the FPGA is loaded by hardware so it can be read inconditionnaly. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Diffstat (limited to 'board/cssi')
-rw-r--r--board/cssi/common/common.c6
-rw-r--r--board/cssi/mcr3000/mcr3000.c7
2 files changed, 11 insertions, 2 deletions
diff --git a/board/cssi/common/common.c b/board/cssi/common/common.c
index 6848efd43b..0292a9016e 100644
--- a/board/cssi/common/common.c
+++ b/board/cssi/common/common.c
@@ -164,7 +164,7 @@ int checkboard_common(void)
void misc_init_r_common(void)
{
- u8 tmp, far_id;
+ u8 tmp, far_id, addr;
int count = 3;
switch (in_8(ADDR_FPGA_R_BASE)) {
@@ -173,6 +173,10 @@ void misc_init_r_common(void)
if ((in_8(ADDR_FPGA_R_BASE + 0x31) & FPGA_R_ACQ_AL_FAV) == 0)
env_set("bootdelay", "60");
+ addr = in_8(ADDR_FPGA_R_BASE + 0x43);
+ printf("Board address: 0x%2.2x (System %d Rack %d Slot %d)\n",
+ addr, addr >> 7, (addr >> 4) & 7, addr & 15);
+
env_set("config", CFG_BOARD_MCR3000_2G);
env_set("hostname", CFG_BOARD_MCR3000_2G);
break;
diff --git a/board/cssi/mcr3000/mcr3000.c b/board/cssi/mcr3000/mcr3000.c
index 15a2d0d946..48e82a902d 100644
--- a/board/cssi/mcr3000/mcr3000.c
+++ b/board/cssi/mcr3000/mcr3000.c
@@ -167,7 +167,12 @@ int misc_init_r(void)
setbits_be32(&immr->im_cpm.cp_pbdir, 0xf);
clrbits_be32(&immr->im_cpm.cp_pbdat, 0x1);
- load_fpga();
+ if (!load_fpga()) {
+ u8 addr = in_be16((void *)0x1400009c);
+
+ printf("Board address: 0x%2.2x (System %d Rack %d Slot %d)\n",
+ addr, addr >> 7, (addr >> 4) & 7, addr & 15);
+ }
/* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)