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authorRick Chen <rick@andestech.com>2023-01-04 10:37:48 +0800
committerLeo Yu-Chi Liang <ycliang@andestech.com>2023-02-01 16:17:53 +0800
commitc5740bc1b2f069a58fae28bee28dbda0e5c6f5dc (patch)
treed582a87302ddf3790def2954006b13d9011b8810 /board/AndesTech
parent3c60e59a4f540ae28dc51a4044f9733169cd7081 (diff)
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riscv: ae350: support OpenSBI 1.0+ which enable FW_PIC
Original OpenSBI (without FW_PIC) will relocate itself from 0x1000000 to 0x0. After OpenSBI added FW_PIC codes, it will not relocate any more and always run at 0x1000000. Hence, it may overlap with Kernel memory region. So it is necessary to change OpenSBI address from 0x1000000 to 0x0. More details can refer to commit cb052d771200 ("riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+") Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bin Meng <bmeng@tinylab.org>
Diffstat (limited to 'board/AndesTech')
-rw-r--r--board/AndesTech/ax25-ae350/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
index 36b67f0b52..4bb33b0793 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -25,7 +25,7 @@ config SPL_TEXT_BASE
default 0x800000
config SPL_OPENSBI_LOAD_ADDR
- default 0x01000000
+ default 0x00000000
config SYS_FDT_BASE
hex