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authorBaruch Siach <baruch@tkos.co.il>2019-02-03 15:15:38 +0200
committerStefan Roese <sr@denx.de>2019-02-11 09:39:12 +0100
commitf301ba55c877707e15378401247cc828740ba00e (patch)
tree01181f148f4619b4c2268c025a4935c0b8e497d4 /arch
parentdbe70c7d4e3d5c705a98d82952e05a591efd0683 (diff)
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arm: mvebu: mcbin: dts: fix PCIe reset polarity
The PCIe slot PERST signal is active low. Fix the gpio signal description in the dts. This happened to work because the pcie_dw_mvebu driver sets the reset gpio level to 1 (high) to release the reset. The following commit will fix that. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/armada-8040-mcbin.dts2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
index 7e8e2f707c..5a046d9de4 100644
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -132,7 +132,7 @@
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_pcie_reset_pins>;
- marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */
+ marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
status = "okay";
};