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| author | Paul Burton <paul.burton@imgtec.com> | 2016-09-21 11:18:49 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-09-21 15:04:04 +0200 |
| commit | 33b5c9b2092e10fa3b8b325823c846368f25bba9 (patch) | |
| tree | 82545fc3c03572f244679cdfcd4c7387d0a24c41 /arch | |
| parent | 8cb4817d0f076605c5126f0925f6c7fdb0461bf6 (diff) | |
| download | u-boot-33b5c9b2092e10fa3b8b325823c846368f25bba9.tar.gz u-boot-33b5c9b2092e10fa3b8b325823c846368f25bba9.tar.bz2 u-boot-33b5c9b2092e10fa3b8b325823c846368f25bba9.zip | |
MIPS: Enable use of the instruction cache earlier
Enable use of the instruction cache immediately after it has been
initialised. This will only take effect if U-Boot was linked to run from
kseg0 rather than kseg1, but when this is the case the data cache
initialisation code will run cached & thus significantly faster.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/cpu/start.S | 8 | ||||
| -rw-r--r-- | arch/mips/lib/cache_init.S | 13 |
2 files changed, 13 insertions, 8 deletions
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index fc6dd66aa6..827a544987 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -12,10 +12,6 @@ #include <asm/regdef.h> #include <asm/mipsregs.h> -#ifndef CONFIG_SYS_MIPS_CACHE_MODE -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT -#endif - #ifndef CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_INIT_SP_OFFSET) @@ -154,10 +150,6 @@ reset: PTR_LA t9, mips_cache_reset jalr t9 nop - - /* ... and enable them */ - li t0, CONFIG_SYS_MIPS_CACHE_MODE - mtc0 t0, CP0_CONFIG #endif /* Set up temporary stack */ diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index bc8ab27b58..974dfe9cea 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -172,6 +172,19 @@ LEAF(mips_cache_reset) cache_loop t0, t1, t8, INDEX_STORE_TAG_I #endif + /* Enable use of the I-cache by setting Config.K0 */ + sync + mfc0 t0, CP0_CONFIG + li t1, CONFIG_SYS_MIPS_CACHE_MODE +#if __mips_isa_rev >= 2 + ins t0, t1, 0, 3 +#else + ori t0, t0, CONF_CM_CMASK + xori t0, t0, CONF_CM_CMASK + or t0, t0, t1 +#endif + mtc0 t0, CP0_CONFIG + /* * then initialize D-cache. */ |