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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-26 14:21:44 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-29 03:50:16 +0900 |
| commit | 82e5950802137d8bb5ee389e16c6a9f3b0361faf (patch) | |
| tree | 78cc9024565ba7a09423b6e40a0101de64ffac94 /arch | |
| parent | 6257a0b0e9b84fca5853e225e1de8023de5f1668 (diff) | |
| download | u-boot-82e5950802137d8bb5ee389e16c6a9f3b0361faf.tar.gz u-boot-82e5950802137d8bb5ee389e16c6a9f3b0361faf.tar.bz2 u-boot-82e5950802137d8bb5ee389e16c6a9f3b0361faf.zip | |
ARM: uniphier: refactor UMC init code for PH1-sLD8
Move frequency-dependent register settings to arrays for clean-up.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 37 |
1 files changed, 29 insertions, 8 deletions
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index 73ad934cff..5e333e0c96 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -13,6 +13,14 @@ #include "ddrphy-regs.h" #include "umc-regs.h" +enum dram_size { + DRAM_SZ_128M, + DRAM_SZ_256M, + DRAM_SZ_NR, +}; + +static u32 umc_spcctla[DRAM_SZ_NR] = {0x00240512, 0x00350512}; + static void umc_start_ssif(void __iomem *ssif_base) { writel(0x00000000, ssif_base + 0x0000b004); @@ -47,17 +55,28 @@ static void umc_start_ssif(void __iomem *ssif_base) writel(0x00000001, ssif_base + UMC_DMDRST); } -static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq, bool ddr3plus) +static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq, bool ddr3plus) { + enum dram_size size_e; + + switch (size) { + case 0: + return 0; + case 1: + size_e = DRAM_SZ_128M; + break; + case 2: + size_e = DRAM_SZ_256M; + break; + default: + pr_err("unsupported DRAM size\n"); + return -EINVAL; + } + writel(ddr3plus ? 0x45990b11 : 0x55990b11, dramcont + UMC_CMDCTLA); writel(ddr3plus ? 0x16958924 : 0x16958944, dramcont + UMC_CMDCTLB); - - if (size == 1) - writel(0x00240512, dramcont + UMC_SPCCTLA); - else if (size == 2) - writel(0x00350512, dramcont + UMC_SPCCTLA); - + writel(umc_spcctla[size_e], dramcont + UMC_SPCCTLA); writel(0x00ff0006, dramcont + UMC_SPCCTLB); writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); writel(0x04060806, dramcont + UMC_WDATACTL_D0); @@ -78,6 +97,8 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, writel(0x200a0a00, dramcont + UMC_SPCSETB); writel(0x00000000, dramcont + UMC_SPCSETD); writel(0x00000520, dramcont + UMC_DFICUPDCTLA); + + return 0; } static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus) |