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authorTom Rini <trini@konsulko.com>2018-10-12 11:54:30 -0400
committerTom Rini <trini@konsulko.com>2018-10-12 15:21:24 -0400
commit19ca29f3ff5811e058360aa275208d219b3078c2 (patch)
tree0e6bb5ef2ee94e829c793337cbf2f74b3bce4fe2 /arch
parente6cd05e5025bbab9723bbb09c506cbb5aa63bc53 (diff)
parent90de3969be48924114f2d725923e12f32bf7796e (diff)
downloadu-boot-19ca29f3ff5811e058360aa275208d219b3078c2.tar.gz
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Merge git://git.denx.de/u-boot-sunxi
[trini: Convert da850evm_nand defconfig now to to SPL_DM] Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-sunxi/dram_sun50i_h6.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index 6b94cf38c5..5da90a2835 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -299,6 +299,8 @@ static void mctl_sys_init(struct dram_para *para)
/* Put all DRAM-related blocks to reset state */
clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET);
+ clrbits_le32(&ccm->dram_gate_reset, BIT(0));
+ udelay(5);
writel(0, &ccm->dram_gate_reset);
clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
@@ -313,7 +315,9 @@ static void mctl_sys_init(struct dram_para *para)
/* Configure DRAM mod clock */
writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);
setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE);
- writel(BIT(0) | BIT(RESET_SHIFT), &ccm->dram_gate_reset);
+ writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset);
+ udelay(5);
+ setbits_le32(&ccm->dram_gate_reset, BIT(0));
/* Disable all channels */
writel(0, &mctl_com->maer0);