summaryrefslogtreecommitdiff
path: root/arch/x86
diff options
context:
space:
mode:
authorBin Meng <bmeng.cn@gmail.com>2021-07-28 12:00:23 +0800
committerBin Meng <bmeng.cn@gmail.com>2021-08-02 15:11:40 +0800
commitc79cbb5952068d9f05e4bcc7bdbbc8957fe35c68 (patch)
tree3a15b63c5a64bbc754b58eb7be0b9d2ebc842023 /arch/x86
parent5824bc6d6fe5f63aa1fb9acbe5ad5aa28d77380f (diff)
downloadu-boot-c79cbb5952068d9f05e4bcc7bdbbc8957fe35c68.tar.gz
u-boot-c79cbb5952068d9f05e4bcc7bdbbc8957fe35c68.tar.bz2
u-boot-c79cbb5952068d9f05e4bcc7bdbbc8957fe35c68.zip
x86: dts: Define a default TSC timer frequency
If for some reason, TSC timer frequency cannot be determined from hardware, nor is it specified in the device tree, U-Boot will panic resulting in endless reset during boot. Let's define a default TSC timer frequency using the Kconfig value CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of /include/ otherwise the macro is not pre-processed). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/dts/bayleybay.dts2
-rw-r--r--arch/x86/dts/baytrail_som-db5800-som-6867.dts2
-rw-r--r--arch/x86/dts/cherryhill.dts2
-rw-r--r--arch/x86/dts/chromebook_coral.dts3
-rw-r--r--arch/x86/dts/chromebook_link.dts2
-rw-r--r--arch/x86/dts/chromebook_samus.dts2
-rw-r--r--arch/x86/dts/chromebox_panther.dts2
-rw-r--r--arch/x86/dts/conga-qeval20-qa3-e3845.dts2
-rw-r--r--arch/x86/dts/coreboot.dts7
-rw-r--r--arch/x86/dts/cougarcanyon2.dts2
-rw-r--r--arch/x86/dts/crownbay.dts2
-rw-r--r--arch/x86/dts/edison.dts2
-rw-r--r--arch/x86/dts/efi-x86_app.dts7
-rw-r--r--arch/x86/dts/efi-x86_payload.dts7
-rw-r--r--arch/x86/dts/galileo.dts7
-rw-r--r--arch/x86/dts/minnowmax.dts2
-rw-r--r--arch/x86/dts/qemu-x86_i440fx.dts6
-rw-r--r--arch/x86/dts/qemu-x86_q35.dts6
-rw-r--r--arch/x86/dts/slimbootloader.dts2
-rw-r--r--arch/x86/dts/tsc_timer.dtsi1
20 files changed, 25 insertions, 43 deletions
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index b487bc6655..b92729dd0b 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -14,8 +14,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
index 9c9b5735d7..e9b56de792 100644
--- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts
+++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
@@ -14,8 +14,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts
index 54a9e566d1..7a273670bd 100644
--- a/arch/x86/dts/cherryhill.dts
+++ b/arch/x86/dts/cherryhill.dts
@@ -12,8 +12,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index 8e98e2d5e0..f0caaacfee 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -8,7 +8,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+
+#include "tsc_timer.dtsi"
#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE)
#include "chromeos-x86.dtsi"
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 4f8c65974b..11ff520ac2 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -9,8 +9,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index e624264424..930ec1ace0 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -7,8 +7,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE)
diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index 71519ca2cd..b25f759c79 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -4,8 +4,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 43fea11eb1..705157ceaa 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -14,8 +14,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
index 38ddaafa19..d21978d6e0 100644
--- a/arch/x86/dts/coreboot.dts
+++ b/arch/x86/dts/coreboot.dts
@@ -12,7 +12,8 @@
/include/ "pcspkr.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+
+#include "tsc_timer.dtsi"
/ {
model = "coreboot x86 payload";
@@ -30,10 +31,6 @@
stdout-path = "/serial";
};
- tsc-timer {
- clock-frequency = <1000000000>;
- };
-
pci {
compatible = "pci-x86";
u-boot,dm-pre-reloc;
diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts
index 94ec111db2..58395b5eb6 100644
--- a/arch/x86/dts/cougarcanyon2.dts
+++ b/arch/x86/dts/cougarcanyon2.dts
@@ -12,8 +12,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index a7166a9749..5768352531 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -13,8 +13,8 @@
/include/ "pcspkr.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts
index 8d245bffc2..64b6228363 100644
--- a/arch/x86/dts/edison.dts
+++ b/arch/x86/dts/edison.dts
@@ -10,8 +10,8 @@
/include/ "skeleton.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/efi-x86_app.dts b/arch/x86/dts/efi-x86_app.dts
index 20150f6ede..04e044a07a 100644
--- a/arch/x86/dts/efi-x86_app.dts
+++ b/arch/x86/dts/efi-x86_app.dts
@@ -6,7 +6,8 @@
/dts-v1/;
/include/ "skeleton.dtsi"
-/include/ "tsc_timer.dtsi"
+
+#include "tsc_timer.dtsi"
/ {
model = "EFI x86 Application";
@@ -16,10 +17,6 @@
stdout-path = &serial;
};
- tsc-timer {
- clock-frequency = <1000000000>;
- };
-
serial: serial {
compatible = "efi,uart";
};
diff --git a/arch/x86/dts/efi-x86_payload.dts b/arch/x86/dts/efi-x86_payload.dts
index 5ccb986774..087865f225 100644
--- a/arch/x86/dts/efi-x86_payload.dts
+++ b/arch/x86/dts/efi-x86_payload.dts
@@ -12,7 +12,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+
+#include "tsc_timer.dtsi"
/ {
model = "EFI x86 Payload";
@@ -30,10 +31,6 @@
stdout-path = "/serial";
};
- tsc-timer {
- clock-frequency = <1000000000>;
- };
-
pci {
compatible = "pci-x86";
u-boot,dm-pre-reloc;
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index b5ba1181dd..4120e8f5c4 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -11,7 +11,8 @@
/include/ "skeleton.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+
+#include "tsc_timer.dtsi"
/ {
model = "Intel Galileo";
@@ -41,10 +42,6 @@
};
};
- tsc-timer {
- clock-frequency = <CONFIG_X86_TSC_TIMER_FREQ>;
- };
-
mrc {
compatible = "intel,quark-mrc";
flags = <MRC_FLAG_SCRAMBLE_EN>;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index aa7718f31c..68e0510c68 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -13,8 +13,8 @@
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index c33a11d593..6556e9ebcd 100644
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -12,8 +12,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@@ -42,10 +42,6 @@
};
};
- tsc-timer {
- clock-frequency = <1000000000>;
- };
-
pci {
compatible = "pci-x86";
#address-cells = <3>;
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 9faae7fb56..d0830892e8 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -22,8 +22,8 @@
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
#include "smbios.dtsi"
/ {
@@ -53,10 +53,6 @@
};
};
- tsc-timer {
- clock-frequency = <1000000000>;
- };
-
pci {
compatible = "pci-x86";
#address-cells = <3>;
diff --git a/arch/x86/dts/slimbootloader.dts b/arch/x86/dts/slimbootloader.dts
index d04095c4f8..9b581c8489 100644
--- a/arch/x86/dts/slimbootloader.dts
+++ b/arch/x86/dts/slimbootloader.dts
@@ -7,7 +7,7 @@
/include/ "skeleton.dtsi"
/include/ "reset.dtsi"
-/include/ "tsc_timer.dtsi"
+#include "tsc_timer.dtsi"
/ {
model = "slimbootloader x86 payload";
diff --git a/arch/x86/dts/tsc_timer.dtsi b/arch/x86/dts/tsc_timer.dtsi
index 4f5021d96f..4df8e9d7fc 100644
--- a/arch/x86/dts/tsc_timer.dtsi
+++ b/arch/x86/dts/tsc_timer.dtsi
@@ -1,6 +1,7 @@
/ {
tsc-timer {
compatible = "x86,tsc-timer";
+ clock-frequency = <CONFIG_X86_TSC_TIMER_FREQ>;
u-boot,dm-pre-reloc;
};
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 12:17:54 +0000