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| author | Sagar Shrikant Kadam <sagar.kadam@sifive.com> | 2020-06-28 07:45:00 -0700 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-07-01 15:01:27 +0800 |
| commit | eb75ee4bd63cbd3b9dd0a0696f1457fb38c22024 (patch) | |
| tree | 8b0a55753434e342c673bd3b9aaceb0c063aa4e8 /arch/riscv | |
| parent | a7c81fc8532669822b454f4a0c967d24bfd14f9d (diff) | |
| download | u-boot-eb75ee4bd63cbd3b9dd0a0696f1457fb38c22024.tar.gz u-boot-eb75ee4bd63cbd3b9dd0a0696f1457fb38c22024.tar.bz2 u-boot-eb75ee4bd63cbd3b9dd0a0696f1457fb38c22024.zip | |
riscv: dts: hifive-unleashed-a00: add cpu aliases
Add cpu aliases to U-Boot specific dtsi for hifive-unleashed.
Without aliases we see that the CPU device sequence numbers are set
randomly and the cpu list/detail command will show it as follows:
=> cpu list
1: cpu@1 rv64imafdc
2: cpu@2 rv64imafdc
3: cpu@3 rv64imafdc
0: cpu@4 rv64imafdc
Seems like CPU probing with dm-model also relies on aliases as observed
in case spi. The fu540-c000-u-boot.dtsi has cpu nodes and so adding
corresponding aliases we can ensure that cpu devices are assigned
proper sequence as follows:
=> cpu list
1: cpu@1 rv64imafdc
2: cpu@2 rv64imafdc
3: cpu@3 rv64imafdc
4: cpu@4 rv64imafdc
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi index 303806454b..e037150520 100644 --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -8,6 +8,10 @@ / { aliases { + cpu1 = &cpu1; + cpu2 = &cpu2; + cpu3 = &cpu3; + cpu4 = &cpu4; spi0 = &qspi0; spi2 = &qspi2; }; |