diff options
| author | T Karthik Reddy <t.karthik.reddy@xilinx.com> | 2022-05-12 04:05:33 -0600 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2022-06-29 16:00:31 +0200 |
| commit | bf8dae5fcf400a593d56d5847d8ee62bc4c27855 (patch) | |
| tree | 5638bf0a8e5697d93b8076af87edb195fada3bc5 /arch/arm/mach-versal | |
| parent | cf553bf20e51951110f88501577c7fe8bbf68386 (diff) | |
| download | u-boot-bf8dae5fcf400a593d56d5847d8ee62bc4c27855.tar.gz u-boot-bf8dae5fcf400a593d56d5847d8ee62bc4c27855.tar.bz2 u-boot-bf8dae5fcf400a593d56d5847d8ee62bc4c27855.zip | |
spi: cadence-qspi: reset qspi flash for versal platform
When flash operated at non default mode like DDR, flash need to be reset
to operate in SDR mode to read flash ids by spi-nor framework. Reset the
flash to the default state before using the flash. This reset is handled
by a gpio driver, in case of mini U-Boot as gpio driver is disabled, we
do raw read and write access by the registers.
Versal platform utilizes spi calibration for read delay programming, so
incase by default read delay property is set in DT. We make sure not to
use read delay from DT by overwriting read_delay with -1.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-4-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'arch/arm/mach-versal')
| -rw-r--r-- | arch/arm/mach-versal/include/mach/hardware.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h index 7b728ac110..c52c9d9792 100644 --- a/arch/arm/mach-versal/include/mach/hardware.h +++ b/arch/arm/mach-versal/include/mach/hardware.h @@ -82,3 +82,14 @@ struct crp_regs { #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 #define BOOT_MODE_ALT_SHIFT 12 + +#define FLASH_RESET_GPIO 0xc +#define WPROT_CRP 0xF126001C +#define RST_GPIO 0xF1260318 +#define WPROT_LPD_MIO 0xFF080728 +#define WPROT_PMC_MIO 0xF1060828 +#define BOOT_MODE_DIR 0xF1020204 +#define BOOT_MODE_OUT 0xF1020208 +#define MIO_PIN_12 0xF1060030 +#define BANK0_OUTPUT 0xF1020040 +#define BANK0_TRI 0xF1060200 |