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authorSam Protsenko <semen.protsenko@linaro.org>2024-01-10 21:09:07 -0600
committerMinkyu Kang <mk7.kang@samsung.com>2024-01-24 11:23:20 +0900
commite6e300d5efa65d67a5cd5fcd5749f94f8ad1cda4 (patch)
treebf0bc5bb90a2e04209771ad7cade2dc796b2aabd /arch/arm/mach-exynos
parentc2e8b97c608eb27b82e3a7330b26c2be6684fdae (diff)
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arm: exynos: Add Exynos850 SoC support
Samsung Exynos850 is ARMv8-based mobile-oriented SoC. It features Cortex-A55 CPU (8 cores) and it's built using 8nm process. Add Exynos850 support by enabling next features: * Import Exynos850 SoC dtsi files from Linux kernel * Add Exynos850 MMU memory map * Introduce ARCH_EXYNOS9 platform config option Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/Kconfig9
-rw-r--r--arch/arm/mach-exynos/mmu-arm64.c34
2 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 8f3aee052c..45fc6bb024 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -58,6 +58,15 @@ config ARCH_EXYNOS7
Cortex-A53 CPU (and some in a big.LITTLE configuration). There are
multiple SoCs in this family including Exynos7420.
+config ARCH_EXYNOS9
+ bool "Exynos9 SoC family"
+ select ARM64
+ select BLK
+ select DM_MMC
+ help
+ Samsung Exynos9 SoC family are based on ARMv8 Cortex CPU. There are
+ multiple SoCs in this family including Exynos850.
+
endchoice
if ARCH_EXYNOS4
diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c
index 8d8c64e8f8..30e522804f 100644
--- a/arch/arm/mach-exynos/mmu-arm64.c
+++ b/arch/arm/mach-exynos/mmu-arm64.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
#if IS_ENABLED(CONFIG_EXYNOS7420)
@@ -95,4 +96,37 @@ static struct mm_region exynos7880_mem_map[] = {
};
struct mm_region *mem_map = exynos7880_mem_map;
+
+#elif IS_ENABLED(CONFIG_EXYNOS850)
+
+static struct mm_region exynos850_mem_map[] = {
+ {
+ /* Peripheral block */
+ .virt = 0x10000000UL,
+ .phys = 0x10000000UL,
+ .size = SZ_256M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* DDR, 32-bit area */
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = SZ_2G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* DDR, 64-bit area */
+ .virt = 0x880000000UL,
+ .phys = 0x880000000UL,
+ .size = SZ_2G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ }
+};
+
+struct mm_region *mem_map = exynos850_mem_map;
+
#endif