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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2015-11-09 16:42:07 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-11-30 08:53:04 -0800 |
| commit | 449372148f6d9b5b8bded88ed8eee5c581a4bf81 (patch) | |
| tree | 9e15d0812f5aebf6808e98c8d41c7a225f36b6fb /README | |
| parent | 14480454c76d0f0bc4c5828cc1f054ba6278530e (diff) | |
| download | u-boot-449372148f6d9b5b8bded88ed8eee5c581a4bf81.tar.gz u-boot-449372148f6d9b5b8bded88ed8eee5c581a4bf81.tar.bz2 u-boot-449372148f6d9b5b8bded88ed8eee5c581a4bf81.zip | |
armv8: LS2080A: Rename LS2085A to reflect LS2080A
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -611,6 +611,9 @@ The following options need to be configured: CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS Number of controllers used for other than main memory. + CONFIG_SYS_FSL_HAS_DP_DDR + Defines the SoC has DP-DDR used for DPAA. + CONFIG_SYS_FSL_SEC_BE Defines the SEC controller register space as Big Endian |