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| author | Rafal Jaworowski <raj@semihalf.com> | 2006-08-18 10:39:11 +0200 |
|---|---|---|
| committer | Rafal Jaworowski <raj@pollux.denx.de> | 2006-08-18 10:39:11 +0200 |
| commit | 6fe16a8769a3c8923dea24a7ed9ff7f1f89c3bef (patch) | |
| tree | 37b4ee4d96b4b1db6304764aa60988454b95b97d | |
| parent | 0a0f3a46fb5cfa7105402bee9c52dd379325d156 (diff) | |
| download | u-boot-6fe16a8769a3c8923dea24a7ed9ff7f1f89c3bef.tar.gz u-boot-6fe16a8769a3c8923dea24a7ed9ff7f1f89c3bef.tar.bz2 u-boot-6fe16a8769a3c8923dea24a7ed9ff7f1f89c3bef.zip | |
Fix TQM834x hang.
| -rw-r--r-- | CHANGELOG | 2 | ||||
| -rw-r--r-- | include/configs/TQM834x.h | 19 |
2 files changed, 16 insertions, 5 deletions
@@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix TQM834x hang. + * Cleanup debug code for yucca board. * MCC200: restrict addressable flash space to 32 MB diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index cec7e3ece4..92c7016e6b 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -422,9 +422,9 @@ extern int tqm834x_num_flash_banks; #define CFG_SICRL SICRL_LDP_A /* i-cache and d-cache disabled */ -#define CFG_HID0_INIT 0x000000000 -#define CFG_HID0_FINAL CFG_HID0_INIT -#define CFG_HID2 0x000000000 +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT +#define CFG_HID2 HID2_HBE /* DDR 0 - 512M */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) @@ -437,12 +437,21 @@ extern int tqm834x_num_flash_banks; #define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) /* PCI */ -#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#ifdef CONFIG_PCI +#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) #define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT3L (0) +#define CFG_IBAT3U (0) +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) +#define CFG_IBAT5L (0) +#define CFG_IBAT5U (0) +#endif /* IMMRBAR */ #define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |