Merge branch 'next' of git://git.denx.de/u-boot-sh

This is part 1 of big network cleanup / DM conversion.
The dc2114x/rtl8139/pcnet/tulip PCI adapter drivers received checkpatch
cleanups in preparation for DM conversion. The smc911x is converted to
DM completely. The dwc_eth_qos cache fixes are applied.

13 files changed, 1447 insertions, 1179 deletions

diff --git a/README b/README
index 0834850676..2e8ad3bc0c 100644
--- a/README
+++ b/README
@@ -896,8 +896,6 @@ The following options need to be configured:
 
 		CONFIG_TULIP
 		Support for Digital 2114x chips.
-		Optional CONFIG_TULIP_SELECT_MEDIA for board specific
-		modem chip initialisation (KS8761/QS6611).
 
 		CONFIG_NATSEMI
 		Support for National dp83815 chips.
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index bc518f218d..a2587a29e1 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -388,11 +388,13 @@ config SMC911X
 
 if SMC911X
 
+if !DM_ETH
 config SMC911X_BASE
 	hex "SMC911X Base Address"
 	help
 	  Define this to hold the physical address
 	  of the device (I/O space)
+endif #DM_ETH
 
 choice
 	prompt "SMC911X bus width"
diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c
index 43c2253f10..d008696b0f 100644
--- a/drivers/net/dc2114x.c
+++ b/drivers/net/dc2114x.c
@@ -7,24 +7,21 @@
 #include <netdev.h>
 #include <pci.h>
 
-#undef DEBUG_SROM
-#undef DEBUG_SROM2
+#define SROM_DLEVEL	0
 
 #undef UPDATE_SROM
 
-/* PCI Registers.
- */
-#define PCI_CFDA_PSM		0x43
+/* PCI Registers. */
+#define PCI_CFDA_PSM	0x43
 
 #define CFRV_RN		0x000000f0	/* Revision Number */
 
 #define WAKEUP		0x00		/* Power Saving Wakeup */
 #define SLEEP		0x80		/* Power Saving Sleep Mode */
 
-#define DC2114x_BRK	0x0020		/* CFRV break between DC21142 & DC21143 */
+#define DC2114x_BRK	0x0020	/* CFRV break between DC21142 & DC21143 */
 
-/* Ethernet chip registers.
- */
+/* Ethernet chip registers. */
 #define DE4X5_BMR	0x000		/* Bus Mode Register */
 #define DE4X5_TPD	0x008		/* Transmit Poll Demand Reg */
 #define DE4X5_RRBA	0x018		/* RX Ring Base Address Reg */
@@ -34,8 +31,7 @@
 #define DE4X5_SICR	0x068		/* SIA Connectivity Register */
 #define DE4X5_APROM	0x048		/* Ethernet Address PROM */
 
-/* Register bits.
- */
+/* Register bits. */
 #define BMR_SWR		0x00000001	/* Software Reset */
 #define STS_TS		0x00700000	/* Transmit Process State */
 #define STS_RS		0x000e0000	/* Receive Process State */
@@ -45,8 +41,7 @@
 #define OMR_SDP		0x02000000	/* SD Polarity - MUST BE ASSERTED */
 #define OMR_PM		0x00000080	/* Pass All Multicast */
 
-/* Descriptor bits.
- */
+/* Descriptor bits. */
 #define R_OWN		0x80000000	/* Own Bit */
 #define RD_RER		0x02000000	/* Receive End Of Ring */
 #define RD_LS		0x00000100	/* Last Descriptor */
@@ -63,12 +58,12 @@
 #define SROM_READ_CMD	6
 #define SROM_ERASE_CMD	7
 
-#define SROM_HWADD	    0x0014	/* Hardware Address offset in SROM */
+#define SROM_HWADD	0x0014		/* Hardware Address offset in SROM */
 #define SROM_RD		0x00004000	/* Read from Boot ROM */
-#define EE_DATA_WRITE	      0x04	/* EEPROM chip data in. */
-#define EE_WRITE_0	    0x4801
-#define EE_WRITE_1	    0x4805
-#define EE_DATA_READ	      0x08	/* EEPROM chip data out. */
+#define EE_DATA_WRITE	0x04		/* EEPROM chip data in. */
+#define EE_WRITE_0	0x4801
+#define EE_WRITE_1	0x4805
+#define EE_DATA_READ	0x08		/* EEPROM chip data out. */
 #define SROM_SR		0x00000800	/* Select Serial ROM when set */
 
 #define DT_IN		0x00000004	/* Serial Data In */
@@ -77,48 +72,14 @@
 
 #define POLL_DEMAND	1
 
-#ifdef CONFIG_TULIP_FIX_DAVICOM
-#define RESET_DM9102(dev) {\
-    unsigned long i;\
-    i=INL(dev, 0x0);\
-    udelay(1000);\
-    OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
-    udelay(1000);\
-}
+#if defined(CONFIG_E500)
+#define phys_to_bus(a) (a)
 #else
-#define RESET_DE4X5(dev) {\
-    int i;\
-    i=INL(dev, DE4X5_BMR);\
-    udelay(1000);\
-    OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
-    udelay(1000);\
-    OUTL(dev, i, DE4X5_BMR);\
-    udelay(1000);\
-    for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
-    udelay(1000);\
-}
+#define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
 #endif
 
-#define START_DE4X5(dev) {\
-    s32 omr; \
-    omr = INL(dev, DE4X5_OMR);\
-    omr |= OMR_ST | OMR_SR;\
-    OUTL(dev, omr, DE4X5_OMR);		/* Enable the TX and/or RX */\
-}
-
-#define STOP_DE4X5(dev) {\
-    s32 omr; \
-    omr = INL(dev, DE4X5_OMR);\
-    omr &= ~(OMR_ST|OMR_SR);\
-    OUTL(dev, omr, DE4X5_OMR);		/* Disable the TX and/or RX */ \
-}
-
 #define NUM_RX_DESC PKTBUFSRX
-#ifndef CONFIG_TULIP_FIX_DAVICOM
-	#define NUM_TX_DESC 1			/* Number of TX descriptors   */
-#else
-	#define NUM_TX_DESC 4
-#endif
+#define NUM_TX_DESC 1			/* Number of TX descriptors   */
 #define RX_BUFF_SZ  PKTSIZE_ALIGN
 
 #define TOUT_LOOP   1000000
@@ -132,455 +93,117 @@ struct de4x5_desc {
 	u32 next;
 };
 
-static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring         */
-static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring         */
-static int rx_new;                             /* RX descriptor ring pointer */
-static int tx_new;                             /* TX descriptor ring pointer */
+/* RX and TX descriptor ring */
+static struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
+static struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
+static int rx_new;	/* RX descriptor ring pointer */
+static int tx_new;	/* TX descriptor ring pointer */
 
-static char rxRingSize;
-static char txRingSize;
+static char rx_ring_size;
+static char tx_ring_size;
 
-#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
-static void  sendto_srom(struct eth_device* dev, u_int command, u_long addr);
-static int   getfrom_srom(struct eth_device* dev, u_long addr);
-static int   do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len);
-static int   do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len);
-#endif	/* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
-#ifdef UPDATE_SROM
-static int   write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
-static void  update_srom(struct eth_device *dev, bd_t *bis);
-#endif
-#ifndef CONFIG_TULIP_FIX_DAVICOM
-static int   read_srom(struct eth_device *dev, u_long ioaddr, int index);
-static void  read_hw_addr(struct eth_device* dev, bd_t * bis);
-#endif	/* CONFIG_TULIP_FIX_DAVICOM */
-static void  send_setup_frame(struct eth_device* dev, bd_t * bis);
-
-static int   dc21x4x_init(struct eth_device* dev, bd_t* bis);
-static int   dc21x4x_send(struct eth_device *dev, void *packet, int length);
-static int   dc21x4x_recv(struct eth_device* dev);
-static void  dc21x4x_halt(struct eth_device* dev);
-#ifdef CONFIG_TULIP_SELECT_MEDIA
-extern void  dc21x4x_select_media(struct eth_device* dev);
-#endif
-
-#if defined(CONFIG_E500)
-#define phys_to_bus(a) (a)
-#else
-#define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
-#endif
-
-static int INL(struct eth_device* dev, u_long addr)
+static u32 dc2114x_inl(struct eth_device *dev, u32 addr)
 {
-	return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
+	return le32_to_cpu(*(volatile u32 *)(addr + dev->iobase));
 }
 
-static void OUTL(struct eth_device* dev, int command, u_long addr)
+static void dc2114x_outl(struct eth_device *dev, u32 command, u32 addr)
 {
-	*(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
+	*(volatile u32 *)(addr + dev->iobase) = cpu_to_le32(command);
 }
 
-static struct pci_device_id supported[] = {
-	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
-	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
-#ifdef CONFIG_TULIP_FIX_DAVICOM
-	{ PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A },
-#endif
-	{ }
-};
-
-int dc21x4x_initialize(bd_t *bis)
+static void reset_de4x5(struct eth_device *dev)
 {
-	int			idx=0;
-	int			card_number = 0;
-	unsigned int		cfrv;
-	unsigned char		timer;
-	pci_dev_t		devbusfn;
-	unsigned int		iobase;
-	unsigned short		status;
-	struct eth_device*	dev;
-
-	while(1) {
-		devbusfn =  pci_find_devices(supported, idx++);
-		if (devbusfn == -1) {
-			break;
-		}
-
-		/* Get the chip configuration revision register. */
-		pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
-
-#ifndef CONFIG_TULIP_FIX_DAVICOM
-		if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
-			printf("Error: The chip is not DC21143.\n");
-			continue;
-		}
-#endif
-
-		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
-		status |=
-#ifdef CONFIG_TULIP_USE_IO
-		  PCI_COMMAND_IO |
-#else
-		  PCI_COMMAND_MEMORY |
-#endif
-		  PCI_COMMAND_MASTER;
-		pci_write_config_word(devbusfn, PCI_COMMAND, status);
-
-		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
-#ifdef CONFIG_TULIP_USE_IO
-		if (!(status & PCI_COMMAND_IO)) {
-			printf("Error: Can not enable I/O access.\n");
-			continue;
-		}
-#else
-		if (!(status & PCI_COMMAND_MEMORY)) {
-			printf("Error: Can not enable MEMORY access.\n");
-			continue;
-		}
-#endif
-
-		if (!(status & PCI_COMMAND_MASTER)) {
-			printf("Error: Can not enable Bus Mastering.\n");
-			continue;
-		}
-
-		/* Check the latency timer for values >= 0x60. */
-		pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
-
-		if (timer < 0x60) {
-			pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60);
-		}
-
-#ifdef CONFIG_TULIP_USE_IO
-		/* read BAR for memory space access */
-		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
-		iobase &= PCI_BASE_ADDRESS_IO_MASK;
-#else
-		/* read BAR for memory space access */
-		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
-		iobase &= PCI_BASE_ADDRESS_MEM_MASK;
-#endif
-		debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
-
-		dev = (struct eth_device*) malloc(sizeof *dev);
-
-		if (!dev) {
-			printf("Can not allocalte memory of dc21x4x\n");
-			break;
-		}
-		memset(dev, 0, sizeof(*dev));
-
-#ifdef CONFIG_TULIP_FIX_DAVICOM
-		sprintf(dev->name, "Davicom#%d", card_number);
-#else
-		sprintf(dev->name, "dc21x4x#%d", card_number);
-#endif
-
-#ifdef CONFIG_TULIP_USE_IO
-		dev->iobase = pci_io_to_phys(devbusfn, iobase);
-#else
-		dev->iobase = pci_mem_to_phys(devbusfn, iobase);
-#endif
-		dev->priv   = (void*) devbusfn;
-		dev->init   = dc21x4x_init;
-		dev->halt   = dc21x4x_halt;
-		dev->send   = dc21x4x_send;
-		dev->recv   = dc21x4x_recv;
-
-		/* Ensure we're not sleeping. */
-		pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
-
-		udelay(10 * 1000);
-
-#ifndef CONFIG_TULIP_FIX_DAVICOM
-		read_hw_addr(dev, bis);
-#endif
-		eth_register(dev);
-
-		card_number++;
+	u32 i;
+
+	i = dc2114x_inl(dev, DE4X5_BMR);
+	mdelay(1);
+	dc2114x_outl(dev, i | BMR_SWR, DE4X5_BMR);
+	mdelay(1);
+	dc2114x_outl(dev, i, DE4X5_BMR);
+	mdelay(1);
+
+	for (i = 0; i < 5; i++) {
+		dc2114x_inl(dev, DE4X5_BMR);
+		mdelay(10);
 	}
 
-	return card_number;
+	mdelay(1);
 }
 
-static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
+static void start_de4x5(struct eth_device *dev)
 {
-	int		i;
-	int		devbusfn = (int) dev->priv;
+	u32 omr;
 
-	/* Ensure we're not sleeping. */
-	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
-
-#ifdef CONFIG_TULIP_FIX_DAVICOM
-	RESET_DM9102(dev);
-#else
-	RESET_DE4X5(dev);
-#endif
-
-	if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
-		printf("Error: Cannot reset ethernet controller.\n");
-		return -1;
-	}
-
-#ifdef CONFIG_TULIP_SELECT_MEDIA
-	dc21x4x_select_media(dev);
-#else
-	OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
-#endif
-
-	for (i = 0; i < NUM_RX_DESC; i++) {
-		rx_ring[i].status = cpu_to_le32(R_OWN);
-		rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
-		rx_ring[i].buf = cpu_to_le32(
-			phys_to_bus((u32)net_rx_packets[i]));
-#ifdef CONFIG_TULIP_FIX_DAVICOM
-		rx_ring[i].next = cpu_to_le32(
-			phys_to_bus((u32)&rx_ring[(i + 1) % NUM_RX_DESC]));
-#else
-		rx_ring[i].next = 0;
-#endif
-	}
-
-	for (i=0; i < NUM_TX_DESC; i++) {
-		tx_ring[i].status = 0;
-		tx_ring[i].des1 = 0;
-		tx_ring[i].buf = 0;
-
-#ifdef CONFIG_TULIP_FIX_DAVICOM
-	tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC]));
-#else
-		tx_ring[i].next = 0;
-#endif
-	}
-
-	rxRingSize = NUM_RX_DESC;
-	txRingSize = NUM_TX_DESC;
-
-	/* Write the end of list marker to the descriptor lists. */
-	rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
-	tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
-
-	/* Tell the adapter where the TX/RX rings are located. */
-	OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA);
-	OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA);
-
-	START_DE4X5(dev);
-
-	tx_new = 0;
-	rx_new = 0;
-
-	send_setup_frame(dev, bis);
-
-	return 0;
+	omr = dc2114x_inl(dev, DE4X5_OMR);
+	omr |= OMR_ST | OMR_SR;
+	dc2114x_outl(dev, omr, DE4X5_OMR);	/* Enable the TX and/or RX */
 }
 
-static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
+static void stop_de4x5(struct eth_device *dev)
 {
-	int		status = -1;
-	int		i;
+	u32 omr;
 
-	if (length <= 0) {
-		printf("%s: bad packet size: %d\n", dev->name, length);
-		goto Done;
-	}
-
-	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
-		if (i >= TOUT_LOOP) {
-			printf("%s: tx error buffer not ready\n", dev->name);
-			goto Done;
-		}
-	}
-
-	tx_ring[tx_new].buf    = cpu_to_le32(phys_to_bus((u32) packet));
-	tx_ring[tx_new].des1   = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
-	tx_ring[tx_new].status = cpu_to_le32(T_OWN);
-
-	OUTL(dev, POLL_DEMAND, DE4X5_TPD);
-
-	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
-		if (i >= TOUT_LOOP) {
-			printf(".%s: tx buffer not ready\n", dev->name);
-			goto Done;
-		}
-	}
-
-	if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
-#if 0 /* test-only */
-		printf("TX error status = 0x%08X\n",
-			le32_to_cpu(tx_ring[tx_new].status));
-#endif
-		tx_ring[tx_new].status = 0x0;
-		goto Done;
-	}
-
-	status = length;
-
- Done:
-    tx_new = (tx_new+1) % NUM_TX_DESC;
-	return status;
+	omr = dc2114x_inl(dev, DE4X5_OMR);
+	omr &= ~(OMR_ST | OMR_SR);
+	dc2114x_outl(dev, omr, DE4X5_OMR);	/* Disable the TX and/or RX */
 }
 
-static int dc21x4x_recv(struct eth_device* dev)
+/* SROM Read and write routines. */
+static void sendto_srom(struct eth_device *dev, u_int command, u_long addr)
 {
-	s32		status;
-	int		length    = 0;
-
-	for ( ; ; ) {
-		status = (s32)le32_to_cpu(rx_ring[rx_new].status);
-
-		if (status & R_OWN) {
-			break;
-		}
-
-		if (status & RD_LS) {
-			/* Valid frame status.
-			 */
-			if (status & RD_ES) {
-
-				/* There was an error.
-				 */
-				printf("RX error status = 0x%08X\n", status);
-			} else {
-				/* A valid frame received.
-				 */
-				length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);
-
-				/* Pass the packet up to the protocol
-				 * layers.
-				 */
-				net_process_received_packet(
-					net_rx_packets[rx_new], length - 4);
-			}
-
-			/* Change buffer ownership for this frame, back
-			 * to the adapter.
-			 */
-			rx_ring[rx_new].status = cpu_to_le32(R_OWN);
-		}
-
-		/* Update entry information.
-		 */
-		rx_new = (rx_new + 1) % rxRingSize;
-	}
-
-	return length;
-}
-
-static void dc21x4x_halt(struct eth_device* dev)
-{
-	int		devbusfn = (int) dev->priv;
-
-	STOP_DE4X5(dev);
-	OUTL(dev, 0, DE4X5_SICR);
-
-	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
-}
-
-static void send_setup_frame(struct eth_device* dev, bd_t *bis)
-{
-	int		i;
-	char	setup_frame[SETUP_FRAME_LEN];
-	char	*pa = &setup_frame[0];
-
-	memset(pa, 0xff, SETUP_FRAME_LEN);
-
-	for (i = 0; i < ETH_ALEN; i++) {
-		*(pa + (i & 1)) = dev->enetaddr[i];
-		if (i & 0x01) {
-			pa += 4;
-		}
-	}
-
-	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
-		if (i >= TOUT_LOOP) {
-			printf("%s: tx error buffer not ready\n", dev->name);
-			goto Done;
-		}
-	}
-
-	tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
-	tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
-	tx_ring[tx_new].status = cpu_to_le32(T_OWN);
-
-	OUTL(dev, POLL_DEMAND, DE4X5_TPD);
-
-	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
-		if (i >= TOUT_LOOP) {
-			printf("%s: tx buffer not ready\n", dev->name);
-			goto Done;
-		}
-	}
-
-	if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
-		printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
-	}
-	tx_new = (tx_new+1) % NUM_TX_DESC;
-
-Done:
-	return;
-}
-
-#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
-/* SROM Read and write routines.
- */
-static void
-sendto_srom(struct eth_device* dev, u_int command, u_long addr)
-{
-	OUTL(dev, command, addr);
+	dc2114x_outl(dev, command, addr);
 	udelay(1);
 }
 
-static int
-getfrom_srom(struct eth_device* dev, u_long addr)
+static int getfrom_srom(struct eth_device *dev, u_long addr)
 {
-	s32 tmp;
+	u32 tmp = dc2114x_inl(dev, addr);
 
-	tmp = INL(dev, addr);
 	udelay(1);
-
 	return tmp;
 }
 
 /* Note: this routine returns extra data bits for size detection. */
-static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len)
+static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location,
+			  int addr_len)
 {
-	int i;
-	unsigned retval = 0;
 	int read_cmd = location | (SROM_READ_CMD << addr_len);
+	unsigned int retval = 0;
+	int i;
 
 	sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
 	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
 
-#ifdef DEBUG_SROM
-	printf(" EEPROM read at %d ", location);
-#endif
+	debug_cond(SROM_DLEVEL >= 1, " EEPROM read at %d ", location);
 
 	/* Shift the read command bits out. */
 	for (i = 4 + addr_len; i >= 0; i--) {
 		short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
-		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr);
+
+		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval,
+			    ioaddr);
 		udelay(10);
-		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr);
+		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK,
+			    ioaddr);
 		udelay(10);
-#ifdef DEBUG_SROM2
-		printf("%X", getfrom_srom(dev, ioaddr) & 15);
-#endif
-		retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
+		debug_cond(SROM_DLEVEL >= 2, "%X",
+			   getfrom_srom(dev, ioaddr) & 15);
+		retval = (retval << 1) |
+			 !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
 	}
 
 	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
 
-#ifdef DEBUG_SROM2
-	printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
-#endif
+	debug_cond(SROM_DLEVEL >= 2, " :%X:", getfrom_srom(dev, ioaddr) & 15);
 
 	for (i = 16; i > 0; i--) {
 		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
 		udelay(10);
-#ifdef DEBUG_SROM2
-		printf("%X", getfrom_srom(dev, ioaddr) & 15);
-#endif
-		retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
+		debug_cond(SROM_DLEVEL >= 2, "%X",
+			   getfrom_srom(dev, ioaddr) & 15);
+		retval = (retval << 1) |
+			 !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
 		sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
 		udelay(10);
 	}
@@ -588,145 +211,115 @@ static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, i
 	/* Terminate the EEPROM access. */
 	sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
 
-#ifdef DEBUG_SROM2
-	printf(" EEPROM value at %d is %5.5x.\n", location, retval);
-#endif
+	debug_cond(SROM_DLEVEL >= 2, " EEPROM value at %d is %5.5x.\n",
+		   location, retval);
 
 	return retval;
 }
-#endif	/* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
 
-/* This executes a generic EEPROM command, typically a write or write
+/*
+ * This executes a generic EEPROM command, typically a write or write
  * enable. It returns the data output from the EEPROM, and thus may
  * also be used for reads.
  */
-#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
-static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
+static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd,
+			 int cmd_len)
 {
-	unsigned retval = 0;
+	unsigned int retval = 0;
 
-#ifdef DEBUG_SROM
-	printf(" EEPROM op 0x%x: ", cmd);
-#endif
+	debug_cond(SROM_DLEVEL >= 1, " EEPROM op 0x%x: ", cmd);
 
-	sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
+	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
 
 	/* Shift the command bits out. */
 	do {
-		short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
-		sendto_srom(dev,dataval, ioaddr);
+		short dataval = (cmd & BIT(cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
+
+		sendto_srom(dev, dataval, ioaddr);
 		udelay(10);
 
-#ifdef DEBUG_SROM2
-		printf("%X", getfrom_srom(dev,ioaddr) & 15);
-#endif
+		debug_cond(SROM_DLEVEL >= 2, "%X",
+			   getfrom_srom(dev, ioaddr) & 15);
 
-		sendto_srom(dev,dataval | DT_CLK, ioaddr);
+		sendto_srom(dev, dataval | DT_CLK, ioaddr);
 		udelay(10);
-		retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0);
+		retval = (retval << 1) |
+			 !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
 	} while (--cmd_len >= 0);
-	sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr);
+
+	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
 
 	/* Terminate the EEPROM access. */
-	sendto_srom(dev,SROM_RD | SROM_SR, ioaddr);
+	sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
 
-#ifdef DEBUG_SROM
-	printf(" EEPROM result is 0x%5.5x.\n", retval);
-#endif
+	debug_cond(SROM_DLEVEL >= 1, " EEPROM result is 0x%5.5x.\n", retval);
 
 	return retval;
 }
-#endif	/* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
 
-#ifndef CONFIG_TULIP_FIX_DAVICOM
 static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
 {
-	int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
+	int ee_addr_size;
 
-	return do_eeprom_cmd(dev, ioaddr,
-			     (((SROM_READ_CMD << ee_addr_size) | index) << 16)
-			     | 0xffff, 3 + ee_addr_size + 16);
+	ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
+
+	return do_eeprom_cmd(dev, ioaddr, 0xffff |
+			     (((SROM_READ_CMD << ee_addr_size) | index) << 16),
+			     3 + ee_addr_size + 16);
 }
-#endif	/* CONFIG_TULIP_FIX_DAVICOM */
 
 #ifdef UPDATE_SROM
-static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
+static int write_srom(struct eth_device *dev, u_long ioaddr, int index,
+		      int new_value)
 {
-	int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
-	int i;
 	unsigned short newval;
+	int ee_addr_size;
+	int i;
 
-	udelay(10*1000); /* test-only */
+	ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
 
-#ifdef DEBUG_SROM
-	printf("ee_addr_size=%d.\n", ee_addr_size);
-	printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
-#endif
+	udelay(10 * 1000); /* test-only */
+
+	debug_cond(SROM_DLEVEL >= 1, "ee_addr_size=%d.\n", ee_addr_size);
+	debug_cond(SROM_DLEVEL >= 1,
+		   "Writing new entry 0x%4.4x to offset %d.\n",
+		   new_value, index);
 
 	/* Enable programming modes. */
-	do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size);
+	do_eeprom_cmd(dev, ioaddr, 0x4f << (ee_addr_size - 4),
+		      3 + ee_addr_size);
 
 	/* Do the actual write. */
-	do_eeprom_cmd(dev, ioaddr,
-		      (((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value,
+	do_eeprom_cmd(dev, ioaddr, new_value |
+		      (((SROM_WRITE_CMD << ee_addr_size) | index) << 16),
 		      3 + ee_addr_size + 16);
 
 	/* Poll for write finished. */
 	sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
-	for (i = 0; i < 10000; i++)			/* Typical 2000 ticks */
+	for (i = 0; i < 10000; i++) {	/* Typical 2000 ticks */
 		if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
 			break;
+	}
 
-#ifdef DEBUG_SROM
-	printf(" Write finished after %d ticks.\n", i);
-#endif
+	debug_cond(SROM_DLEVEL >= 1, " Write finished after %d ticks.\n", i);
 
 	/* Disable programming. */
-	do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size);
+	do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size - 4)),
+		      3 + ee_addr_size);
 
 	/* And read the result. */
 	newval = do_eeprom_cmd(dev, ioaddr,
-			       (((SROM_READ_CMD<<ee_addr_size)|index) << 16)
+			       (((SROM_READ_CMD << ee_addr_size) | index) << 16)
 			       | 0xffff, 3 + ee_addr_size + 16);
-#ifdef DEBUG_SROM
-	printf("  New value at offset %d is %4.4x.\n", index, newval);
-#endif
-	return 1;
-}
-#endif
-
-#ifndef CONFIG_TULIP_FIX_DAVICOM
-static void read_hw_addr(struct eth_device *dev, bd_t *bis)
-{
-	u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
-	int i, j = 0;
 
-	for (i = 0; i < (ETH_ALEN >> 1); i++) {
-		tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
-		*p = le16_to_cpu(tmp);
-		j += *p++;
-	}
+	debug_cond(SROM_DLEVEL >= 1, "  New value at offset %d is %4.4x.\n",
+		   index, newval);
 
-	if ((j == 0) || (j == 0x2fffd)) {
-		memset (dev->enetaddr, 0, ETH_ALEN);
-		debug ("Warning: can't read HW address from SROM.\n");
-		goto Done;
-	}
-
-	return;
-
-Done:
-#ifdef UPDATE_SROM
-	update_srom(dev, bis);
-#endif
-	return;
+	return 1;
 }
-#endif	/* CONFIG_TULIP_FIX_DAVICOM */
 
-#ifdef UPDATE_SROM
 static void update_srom(struct eth_device *dev, bd_t *bis)
 {
-	int i;
 	static unsigned short eeprom[0x40] = {
 		0x140b, 0x6610, 0x0000, 0x0000,	/* 00 */
 		0x0000, 0x0000, 0x0000, 0x0000,	/* 04 */
@@ -746,16 +339,318 @@ static void update_srom(struct eth_device *dev, bd_t *bis)
 		0x0000, 0x0000, 0x0000, 0x4e07,	/* 3c */
 	};
 	uchar enetaddr[6];
+	int i;
 
 	/* Ethernet Addr... */
 	if (!eth_env_get_enetaddr("ethaddr", enetaddr))
 		return;
+
 	eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0];
 	eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2];
 	eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4];
 
-	for (i=0; i<0x40; i++) {
+	for (i = 0; i < 0x40; i++)
 		write_srom(dev, DE4X5_APROM, i, eeprom[i]);
+}
+#endif /* UPDATE_SROM */
+
+static void send_setup_frame(struct eth_device *dev, bd_t *bis)
+{
+	char setup_frame[SETUP_FRAME_LEN];
+	char *pa = &setup_frame[0];
+	int i;
+
+	memset(pa, 0xff, SETUP_FRAME_LEN);
+
+	for (i = 0; i < ETH_ALEN; i++) {
+		*(pa + (i & 1)) = dev->enetaddr[i];
+		if (i & 0x01)
+			pa += 4;
+	}
+
+	for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
+		if (i < TOUT_LOOP)
+			continue;
+
+		printf("%s: tx error buffer not ready\n", dev->name);
+		return;
+	}
+
+	tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)&setup_frame[0]));
+	tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN);
+	tx_ring[tx_new].status = cpu_to_le32(T_OWN);
+
+	dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
+
+	for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
+		if (i < TOUT_LOOP)
+			continue;
+
+		printf("%s: tx buffer not ready\n", dev->name);
+		return;
+	}
+
+	if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
+		printf("TX error status2 = 0x%08X\n",
+		       le32_to_cpu(tx_ring[tx_new].status));
+	}
+
+	tx_new = (tx_new + 1) % NUM_TX_DESC;
+}
+
+static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
+{
+	int status = -1;
+	int i;
+
+	if (length <= 0) {
+		printf("%s: bad packet size: %d\n", dev->name, length);
+		goto done;
+	}
+
+	for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
+		if (i < TOUT_LOOP)
+			continue;
+
+		printf("%s: tx error buffer not ready\n", dev->name);
+		goto done;
+	}
+
+	tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)packet));
+	tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
+	tx_ring[tx_new].status = cpu_to_le32(T_OWN);
+
+	dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
+
+	for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
+		if (i < TOUT_LOOP)
+			continue;
+
+		printf(".%s: tx buffer not ready\n", dev->name);
+		goto done;
+	}
+
+	if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
+		tx_ring[tx_new].status = 0x0;
+		goto done;
+	}
+
+	status = length;
+
+done:
+	tx_new = (tx_new + 1) % NUM_TX_DESC;
+	return status;
+}
+
+static int dc21x4x_recv(struct eth_device *dev)
+{
+	int length = 0;
+	u32 status;
+
+	while (true) {
+		status = le32_to_cpu(rx_ring[rx_new].status);
+
+		if (status & R_OWN)
+			break;
+
+		if (status & RD_LS) {
+			/* Valid frame status. */
+			if (status & RD_ES) {
+				/* There was an error. */
+				printf("RX error status = 0x%08X\n", status);
+			} else {
+				/* A valid frame received. */
+				length = (le32_to_cpu(rx_ring[rx_new].status)
+					  >> 16);
+
+				/* Pass the packet up to the protocol layers */
+				net_process_received_packet
+					(net_rx_packets[rx_new], length - 4);
+			}
+
+			/*
+			 * Change buffer ownership for this frame,
+			 * back to the adapter.
+			 */
+			rx_ring[rx_new].status = cpu_to_le32(R_OWN);
+		}
+
+		/* Update entry information. */
+		rx_new = (rx_new + 1) % rx_ring_size;
+	}
+
+	return length;
+}
+
+static int dc21x4x_init(struct eth_device *dev, bd_t *bis)
+{
+	int i;
+	int devbusfn = (int)dev->priv;
+
+	/* Ensure we're not sleeping. */
+	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
+
+	reset_de4x5(dev);
+
+	if (dc2114x_inl(dev, DE4X5_STS) & (STS_TS | STS_RS)) {
+		printf("Error: Cannot reset ethernet controller.\n");
+		return -1;
+	}
+
+	dc2114x_outl(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
+
+	for (i = 0; i < NUM_RX_DESC; i++) {
+		rx_ring[i].status = cpu_to_le32(R_OWN);
+		rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
+		rx_ring[i].buf =
+			cpu_to_le32(phys_to_bus((u32)net_rx_packets[i]));
+		rx_ring[i].next = 0;
+	}
+
+	for (i = 0; i < NUM_TX_DESC; i++) {
+		tx_ring[i].status = 0;
+		tx_ring[i].des1 = 0;
+		tx_ring[i].buf = 0;
+		tx_ring[i].next = 0;
 	}
+
+	rx_ring_size = NUM_RX_DESC;
+	tx_ring_size = NUM_TX_DESC;
+
+	/* Write the end of list marker to the descriptor lists. */
+	rx_ring[rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER);
+	tx_ring[tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
+
+	/* Tell the adapter where the TX/RX rings are located. */
+	dc2114x_outl(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA);
+	dc2114x_outl(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA);
+
+	start_de4x5(dev);
+
+	tx_new = 0;
+	rx_new = 0;
+
+	send_setup_frame(dev, bis);
+
+	return 0;
+}
+
+static void dc21x4x_halt(struct eth_device *dev)
+{
+	int devbusfn = (int)dev->priv;
+
+	stop_de4x5(dev);
+	dc2114x_outl(dev, 0, DE4X5_SICR);
+
+	pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
+}
+
+static void read_hw_addr(struct eth_device *dev, bd_t *bis)
+{
+	u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
+	int i, j = 0;
+
+	for (i = 0; i < (ETH_ALEN >> 1); i++) {
+		tmp = read_srom(dev, DE4X5_APROM, (SROM_HWADD >> 1) + i);
+		*p = le16_to_cpu(tmp);
+		j += *p++;
+	}
+
+	if (!j || j == 0x2fffd) {
+		memset(dev->enetaddr, 0, ETH_ALEN);
+		debug("Warning: can't read HW address from SROM.\n");
+#ifdef UPDATE_SROM
+		update_srom(dev, bis);
+#endif
+	}
+}
+
+static struct pci_device_id supported[] = {
+	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
+	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
+	{ }
+};
+
+int dc21x4x_initialize(bd_t *bis)
+{
+	struct eth_device *dev;
+	unsigned short status;
+	unsigned char timer;
+	unsigned int iobase;
+	int card_number = 0;
+	pci_dev_t devbusfn;
+	unsigned int cfrv;
+	int idx = 0;
+
+	while (1) {
+		devbusfn = pci_find_devices(supported, idx++);
+		if (devbusfn == -1)
+			break;
+
+		/* Get the chip configuration revision register. */
+		pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
+
+		if ((cfrv & CFRV_RN) < DC2114x_BRK) {
+			printf("Error: The chip is not DC21143.\n");
+			continue;
+		}
+
+		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
+		status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+		pci_write_config_word(devbusfn, PCI_COMMAND, status);
+
+		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
+		if (!(status & PCI_COMMAND_MEMORY)) {
+			printf("Error: Can not enable MEMORY access.\n");
+			continue;
+		}
+
+		if (!(status & PCI_COMMAND_MASTER)) {
+			printf("Error: Can not enable Bus Mastering.\n");
+			continue;
+		}
+
+		/* Check the latency timer for values >= 0x60. */
+		pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
+
+		if (timer < 0x60) {
+			pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER,
+					      0x60);
+		}
+
+		/* read BAR for memory space access */
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
+		iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+		debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
+
+		dev = (struct eth_device *)malloc(sizeof(*dev));
+		if (!dev) {
+			printf("Can not allocalte memory of dc21x4x\n");
+			break;
+		}
+
+		memset(dev, 0, sizeof(*dev));
+
+		sprintf(dev->name, "dc21x4x#%d", card_number);
+
+		dev->iobase = pci_mem_to_phys(devbusfn, iobase);
+		dev->priv = (void *)devbusfn;
+		dev->init = dc21x4x_init;
+		dev->halt = dc21x4x_halt;
+		dev->send = dc21x4x_send;
+		dev->recv = dc21x4x_recv;
+
+		/* Ensure we're not sleeping. */
+		pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
+
+		udelay(10 * 1000);
+
+		read_hw_addr(dev, bis);
+
+		eth_register(dev);
+
+		card_number++;
+	}
+
+	return card_number;
 }
-#endif	/* UPDATE_SROM */
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 63f2086dec..60dfd17a74 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1288,9 +1288,9 @@ static int eqos_start(struct udevice *dev)
 		struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
 		rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
 					     (i * EQOS_MAX_PACKET_SIZE));
-		rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
+		rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
+		eqos->config->ops->eqos_flush_desc(rx_desc);
 	}
-	eqos->config->ops->eqos_flush_desc(eqos->descs);
 
 	writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
 	writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);
@@ -1419,7 +1419,8 @@ static int eqos_send(struct udevice *dev, void *packet, int length)
 	tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
 	eqos->config->ops->eqos_flush_desc(tx_desc);
 
-	writel((ulong)(tx_desc + 1), &eqos->dma_regs->ch0_txdesc_tail_pointer);
+	writel((ulong)(&(eqos->tx_descs[eqos->tx_desc_idx])),
+		&eqos->dma_regs->ch0_txdesc_tail_pointer);
 
 	for (i = 0; i < 1000000; i++) {
 		eqos->config->ops->eqos_inval_desc(tx_desc);
@@ -1442,6 +1443,7 @@ static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
 	debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
 
 	rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
+	eqos->config->ops->eqos_inval_desc(rx_desc);
 	if (rx_desc->des3 & EQOS_DESC3_OWN) {
 		debug("%s: RX packet not available\n", __func__);
 		return -EAGAIN;
@@ -1474,6 +1476,11 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
 	}
 
 	rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
+
+	rx_desc->des0 = 0;
+	mb();
+	eqos->config->ops->eqos_flush_desc(rx_desc);
+	eqos->config->ops->eqos_inval_buffer(packet, length);
 	rx_desc->des0 = (u32)(ulong)packet;
 	rx_desc->des1 = 0;
 	rx_desc->des2 = 0;
@@ -1482,7 +1489,7 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
 	 * writes to the rest of the descriptor too.
 	 */
 	mb();
-	rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
+	rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
 	eqos->config->ops->eqos_flush_desc(rx_desc);
 
 	writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
@@ -1536,6 +1543,9 @@ static int eqos_probe_resources_core(struct udevice *dev)
 	}
 	debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
 
+	eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf,
+			EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX);
+
 	debug("%s: OK\n", __func__);
 	return 0;
 
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index b4ad11d3fa..34a5a16cfe 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -21,10 +21,6 @@
 #define PCNET_DEBUG2(fmt,args...)	\
 	debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
 
-#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
-#error "Macro for PCnet chip version is not defined!"
-#endif
-
 /*
  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
@@ -183,14 +179,14 @@ int pcnet_initialize(bd_t *bis)
 		/*
 		 * Setup the PCI device.
 		 */
-		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &bar);
-		dev->iobase = pci_io_to_phys(devbusfn, bar);
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
+		dev->iobase = pci_mem_to_phys(devbusfn, bar);
 		dev->iobase &= ~0xf;
 
 		PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
 			     dev->name, devbusfn, (unsigned long)dev->iobase);
 
-		command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
+		command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 		pci_write_config_word(devbusfn, PCI_COMMAND, command);
 		pci_read_config_word(devbusfn, PCI_COMMAND, &status);
 		if ((status & command) != command) {
@@ -254,16 +250,12 @@ static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
 	case 0x2621:
 		chipname = "PCnet/PCI II 79C970A";	/* PCI */
 		break;
-#ifdef CONFIG_PCNET_79C973
 	case 0x2625:
 		chipname = "PCnet/FAST III 79C973";	/* PCI */
 		break;
-#endif
-#ifdef CONFIG_PCNET_79C975
 	case 0x2627:
 		chipname = "PCnet/FAST III 79C975";	/* PCI */
 		break;
-#endif
 	default:
 		printf("%s: PCnet version %#x not supported\n",
 		       dev->name, chip_version);
@@ -340,7 +332,9 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 		addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
 					       sizeof(*lp->uc));
 		flush_dcache_range(addr, addr + sizeof(*lp->uc));
-		addr = UNCACHED_SDRAM(addr);
+		addr = (unsigned long)map_physmem(addr,
+				roundup(sizeof(*lp->uc), ARCH_DMA_MINALIGN),
+				MAP_NOCACHE);
 		lp->uc = (struct pcnet_uncached_priv *)addr;
 
 		addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
index bb59629f81..1f08397291 100644
--- a/drivers/net/rtl8139.c
+++ b/drivers/net/rtl8139.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * rtl8139.c : U-Boot driver for the RealTek RTL8139
  *
@@ -8,71 +9,68 @@
  */
 
 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset
-
-  ported from the linux driver written by Donald Becker
-  by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
-
-  This software may be used and distributed according to the terms
-  of the GNU Public License, incorporated herein by reference.
-
-  changes to the original driver:
-  - removed support for interrupts, switching to polling mode (yuck!)
-  - removed support for the 8129 chip (external MII)
-
-*/
+ *
+ * ported from the linux driver written by Donald Becker
+ * by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
+ *
+ * changes to the original driver:
+ * - removed support for interrupts, switching to polling mode (yuck!)
+ * - removed support for the 8129 chip (external MII)
+ */
 
 /*********************************************************************/
 /* Revision History						     */
 /*********************************************************************/
 
 /*
-  28 Dec 2002	ken_yap@users.sourceforge.net (Ken Yap)
-     Put in virt_to_bus calls to allow Etherboot relocation.
-
-  06 Apr 2001	ken_yap@users.sourceforge.net (Ken Yap)
-     Following email from Hyun-Joon Cha, added a disable routine, otherwise
-     NIC remains live and can crash the kernel later.
-
-  4 Feb 2000	espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
-     Shuffled things around, removed the leftovers from the 8129 support
-     that was in the Linux driver and added a bit more 8139 definitions.
-     Moved the 8K receive buffer to a fixed, available address outside the
-     0x98000-0x9ffff range.  This is a bit of a hack, but currently the only
-     way to make room for the Etherboot features that need substantial amounts
-     of code like the ANSI console support.  Currently the buffer is just below
-     0x10000, so this even conforms to the tagged boot image specification,
-     which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000.  My
-     interpretation of this "reserved" is that Etherboot may do whatever it
-     likes, as long as its environment is kept intact (like the BIOS
-     variables).  Hopefully fixed rtl_poll() once and for all.	The symptoms
-     were that if Etherboot was left at the boot menu for several minutes, the
-     first eth_poll failed.  Seems like I am the only person who does this.
-     First of all I fixed the debugging code and then set out for a long bug
-     hunting session.  It took me about a week full time work - poking around
-     various places in the driver, reading Don Becker's and Jeff Garzik's Linux
-     driver and even the FreeBSD driver (what a piece of crap!) - and
-     eventually spotted the nasty thing: the transmit routine was acknowledging
-     each and every interrupt pending, including the RxOverrun and RxFIFIOver
-     interrupts.  This confused the RTL8139 thoroughly.	 It destroyed the
-     Rx ring contents by dumping the 2K FIFO contents right where we wanted to
-     get the next packet.  Oh well, what fun.
-
-  18 Jan 2000	mdc@thinguin.org (Marty Connor)
-     Drastically simplified error handling.  Basically, if any error
-     in transmission or reception occurs, the card is reset.
-     Also, pointed all transmit descriptors to the same buffer to
-     save buffer space.	 This should decrease driver size and avoid
-     corruption because of exceeding 32K during runtime.
-
-  28 Jul 1999	(Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
-     rtl_poll was quite broken: it used the RxOK interrupt flag instead
-     of the RxBufferEmpty flag which often resulted in very bad
-     transmission performace - below 1kBytes/s.
-
-*/
+ * 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
+ *    Put in virt_to_bus calls to allow Etherboot relocation.
+ *
+ * 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
+ *    Following email from Hyun-Joon Cha, added a disable routine, otherwise
+ *    NIC remains live and can crash the kernel later.
+ *
+ * 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
+ *    Shuffled things around, removed the leftovers from the 8129 support
+ *    that was in the Linux driver and added a bit more 8139 definitions.
+ *    Moved the 8K receive buffer to a fixed, available address outside the
+ *    0x98000-0x9ffff range. This is a bit of a hack, but currently the only
+ *    way to make room for the Etherboot features that need substantial amounts
+ *    of code like the ANSI console support. Currently the buffer is just below
+ *    0x10000, so this even conforms to the tagged boot image specification,
+ *    which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
+ *    interpretation of this "reserved" is that Etherboot may do whatever it
+ *    likes, as long as its environment is kept intact (like the BIOS
+ *    variables). Hopefully fixed rtl8139_recv() once and for all. The symptoms
+ *    were that if Etherboot was left at the boot menu for several minutes, the
+ *    first eth_poll failed. Seems like I am the only person who does this.
+ *    First of all I fixed the debugging code and then set out for a long bug
+ *    hunting session. It took me about a week full time work - poking around
+ *    various places in the driver, reading Don Becker's and Jeff Garzik's Linux
+ *    driver and even the FreeBSD driver (what a piece of crap!) - and
+ *    eventually spotted the nasty thing: the transmit routine was acknowledging
+ *    each and every interrupt pending, including the RxOverrun and RxFIFIOver
+ *    interrupts. This confused the RTL8139 thoroughly. It destroyed the
+ *    Rx ring contents by dumping the 2K FIFO contents right where we wanted to
+ *    get the next packet. Oh well, what fun.
+ *
+ * 18 Jan 2000 mdc@thinguin.org (Marty Connor)
+ *    Drastically simplified error handling. Basically, if any error
+ *    in transmission or reception occurs, the card is reset.
+ *    Also, pointed all transmit descriptors to the same buffer to
+ *    save buffer space. This should decrease driver size and avoid
+ *    corruption because of exceeding 32K during runtime.
+ *
+ * 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
+ *    rtl8139_recv was quite broken: it used the RxOK interrupt flag instead
+ *    of the RxBufferEmpty flag which often resulted in very bad
+ *    transmission performace - below 1kBytes/s.
+ *
+ */
 
 #include <common.h>
 #include <cpu_func.h>
+#include <linux/types.h>
 #include <malloc.h>
 #include <net.h>
 #include <netdev.h>
@@ -81,8 +79,8 @@
 
 #define RTL_TIMEOUT	100000
 
-/* PCI Tuning Parameters
-   Threshold is bytes transferred to chip before transmission starts. */
+/* PCI Tuning Parameters */
+/* Threshold is bytes transferred to chip before transmission starts. */
 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */
 #define RX_FIFO_THRESH	4	/* Rx buffer level before first PCI xfer.  */
 #define RX_DMA_BURST	4	/* Maximum PCI burst, '4' is 256 bytes */
@@ -99,173 +97,103 @@
 #define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
 
 /* Symbolic offsets to registers. */
-enum RTL8139_registers {
-	MAC0=0,			/* Ethernet hardware address. */
-	MAR0=8,			/* Multicast filter. */
-	TxStatus0=0x10,		/* Transmit status (four 32bit registers). */
-	TxAddr0=0x20,		/* Tx descriptors (also four 32bit). */
-	RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
-	ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
-	IntrMask=0x3C, IntrStatus=0x3E,
-	TxConfig=0x40, RxConfig=0x44,
-	Timer=0x48,		/* general-purpose counter. */
-	RxMissed=0x4C,		/* 24 bits valid, write clears. */
-	Cfg9346=0x50, Config0=0x51, Config1=0x52,
-	TimerIntrReg=0x54,	/* intr if gp counter reaches this value */
-	MediaStatus=0x58,
-	Config3=0x59,
-	MultiIntr=0x5C,
-	RevisionID=0x5E,	/* revision of the RTL8139 chip */
-	TxSummary=0x60,
-	MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
-	NWayExpansion=0x6A,
-	DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
-	NWayTestReg=0x70,
-	RxCnt=0x72,		/* packet received counter */
-	CSCR=0x74,		/* chip status and configuration register */
-	PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80,	/* undocumented */
-	/* from 0x84 onwards are a number of power management/wakeup frame
-	 * definitions we will probably never need to know about.  */
-};
-
-enum ChipCmdBits {
-	CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
-
-/* Interrupt register bits, using my own meaningful names. */
-enum IntrStatusBits {
-	PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
-	RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
-	TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
-};
-enum TxStatusBits {
-	TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
-	TxOutOfWindow=0x20000000, TxAborted=0x40000000,
-	TxCarrierLost=0x80000000,
-};
-enum RxStatusBits {
-	RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
-	RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
-	RxBadAlign=0x0002, RxStatusOK=0x0001,
-};
-
-enum MediaStatusBits {
-	MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
-	MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
-};
-
-enum MIIBMCRBits {
-	BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
-	BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
-};
-
-enum CSCRBits {
-	CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
-	CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
-	CSCR_LinkDownCmd=0x0f3c0,
-};
-
-/* Bits in RxConfig. */
-enum rx_mode_bits {
-	RxCfgWrap=0x80,
-	AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
-	AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
-};
+/* Ethernet hardware address. */
+#define RTL_REG_MAC0				0x00
+/* Multicast filter. */
+#define RTL_REG_MAR0				0x08
+/* Transmit status (four 32bit registers). */
+#define RTL_REG_TXSTATUS0			0x10
+/* Tx descriptors (also four 32bit). */
+#define RTL_REG_TXADDR0				0x20
+#define RTL_REG_RXBUF				0x30
+#define RTL_REG_RXEARLYCNT			0x34
+#define RTL_REG_RXEARLYSTATUS			0x36
+#define RTL_REG_CHIPCMD				0x37
+#define RTL_REG_CHIPCMD_CMDRESET		BIT(4)
+#define RTL_REG_CHIPCMD_CMDRXENB		BIT(3)
+#define RTL_REG_CHIPCMD_CMDTXENB		BIT(2)
+#define RTL_REG_CHIPCMD_RXBUFEMPTY		BIT(0)
+#define RTL_REG_RXBUFPTR			0x38
+#define RTL_REG_RXBUFADDR			0x3A
+#define RTL_REG_INTRMASK			0x3C
+#define RTL_REG_INTRSTATUS			0x3E
+#define RTL_REG_INTRSTATUS_PCIERR		BIT(15)
+#define RTL_REG_INTRSTATUS_PCSTIMEOUT		BIT(14)
+#define RTL_REG_INTRSTATUS_CABLELENCHANGE	BIT(13)
+#define RTL_REG_INTRSTATUS_RXFIFOOVER		BIT(6)
+#define RTL_REG_INTRSTATUS_RXUNDERRUN		BIT(5)
+#define RTL_REG_INTRSTATUS_RXOVERFLOW		BIT(4)
+#define RTL_REG_INTRSTATUS_TXERR		BIT(3)
+#define RTL_REG_INTRSTATUS_TXOK			BIT(2)
+#define RTL_REG_INTRSTATUS_RXERR		BIT(1)
+#define RTL_REG_INTRSTATUS_RXOK			BIT(0)
+#define RTL_REG_TXCONFIG			0x40
+#define RTL_REG_RXCONFIG			0x44
+#define RTL_REG_RXCONFIG_RXCFGWRAP		BIT(7)
+#define RTL_REG_RXCONFIG_ACCEPTERR		BIT(5)
+#define RTL_REG_RXCONFIG_ACCEPTRUNT		BIT(4)
+#define RTL_REG_RXCONFIG_ACCEPTBROADCAST	BIT(3)
+#define RTL_REG_RXCONFIG_ACCEPTMULTICAST	BIT(2)
+#define RTL_REG_RXCONFIG_ACCEPTMYPHYS		BIT(1)
+#define RTL_REG_RXCONFIG_ACCEPTALLPHYS		BIT(0)
+/* general-purpose counter. */
+#define RTL_REG_TIMER				0x48
+/* 24 bits valid, write clears. */
+#define RTL_REG_RXMISSED			0x4C
+#define RTL_REG_CFG9346				0x50
+#define RTL_REG_CONFIG0				0x51
+#define RTL_REG_CONFIG1				0x52
+/* intr if gp counter reaches this value */
+#define RTL_REG_TIMERINTRREG			0x54
+#define RTL_REG_MEDIASTATUS			0x58
+#define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE	BIT(7)
+#define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE	BIT(6)
+#define RTL_REG_MEDIASTATUS_MSRSPEED10		BIT(3)
+#define RTL_REG_MEDIASTATUS_MSRLINKFAIL		BIT(2)
+#define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG	BIT(1)
+#define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG	BIT(0)
+#define RTL_REG_CONFIG3				0x59
+#define RTL_REG_MULTIINTR			0x5C
+/* revision of the RTL8139 chip */
+#define RTL_REG_REVISIONID			0x5E
+#define RTL_REG_TXSUMMARY			0x60
+#define RTL_REG_MII_BMCR			0x62
+#define RTL_REG_MII_BMSR			0x64
+#define RTL_REG_NWAYADVERT			0x66
+#define RTL_REG_NWAYLPAR			0x68
+#define RTL_REG_NWAYEXPANSION			0x6A
+#define RTL_REG_DISCONNECTCNT			0x6C
+#define RTL_REG_FALSECARRIERCNT			0x6E
+#define RTL_REG_NWAYTESTREG			0x70
+/* packet received counter */
+#define RTL_REG_RXCNT				0x72
+/* chip status and configuration register */
+#define RTL_REG_CSCR				0x74
+#define RTL_REG_PHYPARM1			0x78
+#define RTL_REG_TWISTERPARM			0x7c
+/* undocumented */
+#define RTL_REG_PHYPARM2			0x80
+/*
+ * from 0x84 onwards are a number of power management/wakeup frame
+ * definitions we will probably never need to know about.
+ */
 
+#define RTL_STS_RXMULTICAST			BIT(15)
+#define RTL_STS_RXPHYSICAL			BIT(14)
+#define RTL_STS_RXBROADCAST			BIT(13)
+#define RTL_STS_RXBADSYMBOL			BIT(5)
+#define RTL_STS_RXRUNT				BIT(4)
+#define RTL_STS_RXTOOLONG			BIT(3)
+#define RTL_STS_RXCRCERR			BIT(2)
+#define RTL_STS_RXBADALIGN			BIT(1)
+#define RTL_STS_RXSTATUSOK			BIT(0)
+
+static unsigned int cur_rx, cur_tx;
 static int ioaddr;
-static unsigned int cur_rx,cur_tx;
 
 /* The RTL8139 can only transmit from a contiguous, aligned memory block.  */
-static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
-static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
-
-static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
-static int read_eeprom(int location, int addr_len);
-static void rtl_reset(struct eth_device *dev);
-static int rtl_transmit(struct eth_device *dev, void *packet, int length);
-static int rtl_poll(struct eth_device *dev);
-static void rtl_disable(struct eth_device *dev);
-static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, int join)
-{
-	return (0);
-}
-
-static struct pci_device_id supported[] = {
-       {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
-       {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
-       {}
-};
-
-int rtl8139_initialize(bd_t *bis)
-{
-	pci_dev_t devno;
-	int card_number = 0;
-	struct eth_device *dev;
-	u32 iobase;
-	int idx=0;
-
-	while(1){
-		/* Find RTL8139 */
-		if ((devno = pci_find_devices(supported, idx++)) < 0)
-			break;
-
-		pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
-		iobase &= ~0xf;
-
-		debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
-
-		dev = (struct eth_device *)malloc(sizeof *dev);
-		if (!dev) {
-			printf("Can not allocate memory of rtl8139\n");
-			break;
-		}
-		memset(dev, 0, sizeof(*dev));
-
-		sprintf (dev->name, "RTL8139#%d", card_number);
-
-		dev->priv = (void *) devno;
-		dev->iobase = (int)bus_to_phys(iobase);
-		dev->init = rtl8139_probe;
-		dev->halt = rtl_disable;
-		dev->send = rtl_transmit;
-		dev->recv = rtl_poll;
-		dev->mcast = rtl_bcast_addr;
-
-		eth_register (dev);
-
-		card_number++;
-
-		pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
-
-		udelay (10 * 1000);
-	}
-
-	return card_number;
-}
-
-static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
-{
-	int i;
-	int addr_len;
-	unsigned short *ap = (unsigned short *)dev->enetaddr;
-
-	ioaddr = dev->iobase;
-
-	/* Bring the chip out of low-power mode. */
-	outb(0x00, ioaddr + Config1);
-
-	addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
-	for (i = 0; i < 3; i++)
-		*ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
-
-	rtl_reset(dev);
-
-	if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
-		printf("Cable not connected or other link failure\n");
-		return -1 ;
-	}
-
-	return 0;
-}
+static unsigned char tx_buffer[TX_BUF_SIZE] __aligned(4);
+static unsigned char rx_ring[RX_BUF_LEN + 16] __aligned(4);
 
 /* Serial EEPROM section. */
 
@@ -278,51 +206,57 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
 #define EE_DATA_READ	0x01	/* EEPROM chip data out. */
 #define EE_ENB		(0x80 | EE_CS)
 
-/*
-	Delay between EEPROM clock transitions.
-	No extra delay is needed with 33MHz PCI, but 66MHz may change this.
-*/
-
-#define eeprom_delay()	inl(ee_addr)
-
 /* The EEPROM commands include the alway-set leading bit. */
-#define EE_WRITE_CMD	(5)
-#define EE_READ_CMD	(6)
-#define EE_ERASE_CMD	(7)
+#define EE_WRITE_CMD	5
+#define EE_READ_CMD	6
+#define EE_ERASE_CMD	7
 
-static int read_eeprom(int location, int addr_len)
+static void rtl8139_eeprom_delay(uintptr_t regbase)
 {
-	int i;
+	/*
+	 * Delay between EEPROM clock transitions.
+	 * No extra delay is needed with 33MHz PCI, but 66MHz may change this.
+	 */
+	inl(regbase + RTL_REG_CFG9346);
+}
+
+static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len)
+{
+	unsigned int read_cmd = location | (EE_READ_CMD << addr_len);
+	uintptr_t ee_addr = ioaddr + RTL_REG_CFG9346;
 	unsigned int retval = 0;
-	long ee_addr = ioaddr + Cfg9346;
-	int read_cmd = location | (EE_READ_CMD << addr_len);
+	u8 dataval;
+	int i;
 
 	outb(EE_ENB & ~EE_CS, ee_addr);
 	outb(EE_ENB, ee_addr);
-	eeprom_delay();
+	rtl8139_eeprom_delay(ioaddr);
 
 	/* Shift the read command bits out. */
 	for (i = 4 + addr_len; i >= 0; i--) {
-		int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
+		dataval = (read_cmd & BIT(i)) ? EE_DATA_WRITE : 0;
 		outb(EE_ENB | dataval, ee_addr);
-		eeprom_delay();
+		rtl8139_eeprom_delay(ioaddr);
 		outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
-		eeprom_delay();
+		rtl8139_eeprom_delay(ioaddr);
 	}
+
 	outb(EE_ENB, ee_addr);
-	eeprom_delay();
+	rtl8139_eeprom_delay(ioaddr);
 
 	for (i = 16; i > 0; i--) {
 		outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
-		eeprom_delay();
-		retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
+		rtl8139_eeprom_delay(ioaddr);
+		retval <<= 1;
+		retval |= inb(ee_addr) & EE_DATA_READ;
 		outb(EE_ENB, ee_addr);
-		eeprom_delay();
+		rtl8139_eeprom_delay(ioaddr);
 	}
 
 	/* Terminate the EEPROM access. */
 	outb(~EE_CS, ee_addr);
-	eeprom_delay();
+	rtl8139_eeprom_delay(ioaddr);
+
 	return retval;
 }
 
@@ -331,149 +265,174 @@ static const unsigned int rtl8139_rx_config =
 	(RX_FIFO_THRESH << 13) |
 	(RX_DMA_BURST << 8);
 
-static void set_rx_mode(struct eth_device *dev) {
-	unsigned int mc_filter[2];
-	int rx_mode;
+static void rtl8139_set_rx_mode(struct eth_device *dev)
+{
 	/* !IFF_PROMISC */
-	rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
-	mc_filter[1] = mc_filter[0] = 0xffffffff;
+	unsigned int rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST |
+			       RTL_REG_RXCONFIG_ACCEPTMULTICAST |
+			       RTL_REG_RXCONFIG_ACCEPTMYPHYS;
 
-	outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);
+	outl(rtl8139_rx_config | rx_mode, ioaddr + RTL_REG_RXCONFIG);
 
-	outl(mc_filter[0], ioaddr + MAR0 + 0);
-	outl(mc_filter[1], ioaddr + MAR0 + 4);
+	outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 0);
+	outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 4);
 }
 
-static void rtl_reset(struct eth_device *dev)
+static void rtl8139_hw_reset(struct eth_device *dev)
 {
+	u8 reg;
 	int i;
 
-	outb(CmdReset, ioaddr + ChipCmd);
-
-	cur_rx = 0;
-	cur_tx = 0;
+	outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD);
 
 	/* Give the chip 10ms to finish the reset. */
-	for (i=0; i<100; ++i){
-		if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
-		udelay (100); /* wait 100us */
+	for (i = 0; i < 100; i++) {
+		reg = inb(ioaddr + RTL_REG_CHIPCMD);
+		if (!(reg & RTL_REG_CHIPCMD_CMDRESET))
+			break;
+
+		udelay(100);
 	}
+}
+
+static void rtl8139_reset(struct eth_device *dev)
+{
+	int i;
+
+	cur_rx = 0;
+	cur_tx = 0;
 
+	rtl8139_hw_reset(dev);
 
 	for (i = 0; i < ETH_ALEN; i++)
-		outb(dev->enetaddr[i], ioaddr + MAC0 + i);
+		outb(dev->enetaddr[i], ioaddr + RTL_REG_MAC0 + i);
 
 	/* Must enable Tx/Rx before setting transfer thresholds! */
-	outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
-	outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
-		ioaddr + RxConfig);		/* accept no frames yet!  */
-	outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
-
-	/* The Linux driver changes Config1 here to use a different LED pattern
-	 * for half duplex or full/autodetect duplex (for full/autodetect, the
-	 * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
-	 * TX/RX, Link100, Link10).  This is messy, because it doesn't match
-	 * the inscription on the mounting bracket.  It should not be changed
-	 * from the configuration EEPROM default, because the card manufacturer
-	 * should have set that to match the card.  */
-
-	debug_cond(DEBUG_RX,
-		"rx ring address is %lX\n",(unsigned long)rx_ring);
-	flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
-	outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
+	outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
+	     ioaddr + RTL_REG_CHIPCMD);
+
+	/* accept no frames yet! */
+	outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
+	outl((TX_DMA_BURST << 8) | 0x03000000, ioaddr + RTL_REG_TXCONFIG);
+
+	/*
+	 * The Linux driver changes RTL_REG_CONFIG1 here to use a different
+	 * LED pattern for half duplex or full/autodetect duplex (for
+	 * full/autodetect, the outputs are TX/RX, Link10/100, FULL, while
+	 * for half duplex it uses TX/RX, Link100, Link10).  This is messy,
+	 * because it doesn't match the inscription on the mounting bracket.
+	 * It should not be changed from the configuration EEPROM default,
+	 * because the card manufacturer should have set that to match the
+	 * card.
+	 */
+	debug_cond(DEBUG_RX, "rx ring address is %p\n", rx_ring);
 
-	/* If we add multicast support, the MAR0 register would have to be
-	 * initialized to 0xffffffffffffffff (two 32 bit accesses).  Etherboot
-	 * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast.	*/
+	flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
+	outl(phys_to_bus((int)rx_ring), ioaddr + RTL_REG_RXBUF);
 
-	outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
+	/*
+	 * If we add multicast support, the RTL_REG_MAR0 register would have
+	 * to be initialized to 0xffffffffffffffff (two 32 bit accesses).
+	 * Etherboot only needs broadcast (for ARP/RARP/BOOTP/DHCP) and
+	 * unicast.
+	 */
+	outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
+	     ioaddr + RTL_REG_CHIPCMD);
 
-	outl(rtl8139_rx_config, ioaddr + RxConfig);
+	outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
 
 	/* Start the chip's Tx and Rx process. */
-	outl(0, ioaddr + RxMissed);
+	outl(0, ioaddr + RTL_REG_RXMISSED);
 
-	/* set_rx_mode */
-	set_rx_mode(dev);
+	rtl8139_set_rx_mode(dev);
 
 	/* Disable all known interrupts by setting the interrupt mask. */
-	outw(0, ioaddr + IntrMask);
+	outw(0, ioaddr + RTL_REG_INTRMASK);
 }
 
-static int rtl_transmit(struct eth_device *dev, void *packet, int length)
+static int rtl8139_send(struct eth_device *dev, void *packet, int length)
 {
-	unsigned int status;
-	unsigned long txstatus;
 	unsigned int len = length;
+	unsigned long txstatus;
+	unsigned int status;
 	int i = 0;
 
 	ioaddr = dev->iobase;
 
-	memcpy((char *)tx_buffer, (char *)packet, (int)length);
+	memcpy(tx_buffer, packet, length);
 
 	debug_cond(DEBUG_TX, "sending %d bytes\n", len);
 
-	/* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
-	 * bytes are sent automatically for the FCS, totalling to 64 bytes). */
-	while (len < ETH_ZLEN) {
+	/*
+	 * Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
+	 * bytes are sent automatically for the FCS, totalling to 64 bytes).
+	 */
+	while (len < ETH_ZLEN)
 		tx_buffer[len++] = '\0';
-	}
 
 	flush_cache((unsigned long)tx_buffer, length);
-	outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
-	outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
-		ioaddr + TxStatus0 + cur_tx*4);
+	outl(phys_to_bus((unsigned long)tx_buffer),
+	     ioaddr + RTL_REG_TXADDR0 + cur_tx * 4);
+	outl(((TX_FIFO_THRESH << 11) & 0x003f0000) | len,
+	     ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4);
 
 	do {
-		status = inw(ioaddr + IntrStatus);
-		/* Only acknlowledge interrupt sources we can properly handle
-		 * here - the RxOverflow/RxFIFOOver MUST be handled in the
-		 * rtl_poll() function.	 */
-		outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
-		if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
+		status = inw(ioaddr + RTL_REG_INTRSTATUS);
+		/*
+		 * Only acknlowledge interrupt sources we can properly
+		 * handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/
+		 * RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the
+		 * rtl8139_recv() function.
+		 */
+		status &= RTL_REG_INTRSTATUS_TXOK | RTL_REG_INTRSTATUS_TXERR |
+			  RTL_REG_INTRSTATUS_PCIERR;
+		outw(status, ioaddr + RTL_REG_INTRSTATUS);
+		if (status)
+			break;
+
 		udelay(10);
 	} while (i++ < RTL_TIMEOUT);
 
-	txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
-
-	if (status & TxOK) {
-		cur_tx = (cur_tx + 1) % NUM_TX_DESC;
+	txstatus = inl(ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4);
 
+	if (!(status & RTL_REG_INTRSTATUS_TXOK)) {
 		debug_cond(DEBUG_TX,
-			"tx done, status %hX txstatus %lX\n",
-			status, txstatus);
+			   "tx timeout/error (%d usecs), status %hX txstatus %lX\n",
+			   10 * i, status, txstatus);
 
-		return length;
-	} else {
-
-		debug_cond(DEBUG_TX,
-			"tx timeout/error (%d usecs), status %hX txstatus %lX\n",
-			10*i, status, txstatus);
-
-		rtl_reset(dev);
+		rtl8139_reset(dev);
 
 		return 0;
 	}
+
+	cur_tx = (cur_tx + 1) % NUM_TX_DESC;
+
+	debug_cond(DEBUG_TX, "tx done, status %hX txstatus %lX\n",
+		   status, txstatus);
+
+	return length;
 }
 
-static int rtl_poll(struct eth_device *dev)
+static int rtl8139_recv(struct eth_device *dev)
 {
-	unsigned int status;
-	unsigned int ring_offs;
+	const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
+				    RTL_REG_INTRSTATUS_RXOVERFLOW |
+				    RTL_REG_INTRSTATUS_RXOK;
 	unsigned int rx_size, rx_status;
-	int length=0;
+	unsigned int ring_offs;
+	unsigned int status;
+	int length = 0;
 
 	ioaddr = dev->iobase;
 
-	if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
+	if (inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY)
 		return 0;
-	}
 
-	status = inw(ioaddr + IntrStatus);
+	status = inw(ioaddr + RTL_REG_INTRSTATUS);
 	/* See below for the rest of the interrupt acknowledges.  */
-	outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
+	outw(status & ~rxstat, ioaddr + RTL_REG_INTRSTATUS);
 
-	debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status);
+	debug_cond(DEBUG_RX, "%s: int %hX ", __func__, status);
 
 	ring_offs = cur_rx % RX_BUF_LEN;
 	/* ring_offs is guaranteed being 4-byte aligned */
@@ -481,52 +440,137 @@ static int rtl_poll(struct eth_device *dev)
 	rx_size = rx_status >> 16;
 	rx_status &= 0xffff;
 
-	if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
-	    (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
+	if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT |
+			  RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR |
+			  RTL_STS_RXBADALIGN)) ||
+	    (rx_size < ETH_ZLEN) ||
+	    (rx_size > ETH_FRAME_LEN + 4)) {
 		printf("rx error %hX\n", rx_status);
-		rtl_reset(dev); /* this clears all interrupts still pending */
+		/* this clears all interrupts still pending */
+		rtl8139_reset(dev);
 		return 0;
 	}
 
 	/* Received a good packet */
 	length = rx_size - 4;	/* no one cares about the FCS */
-	if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
-		int semi_count = RX_BUF_LEN - ring_offs - 4;
+	if (ring_offs + 4 + rx_size - 4 > RX_BUF_LEN) {
 		unsigned char rxdata[RX_BUF_LEN];
+		int semi_count = RX_BUF_LEN - ring_offs - 4;
 
 		memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
-		memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
+		memcpy(&rxdata[semi_count], rx_ring,
+		       rx_size - 4 - semi_count);
 
 		net_process_received_packet(rxdata, length);
 		debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
-			semi_count, rx_size-4-semi_count);
+			   semi_count, rx_size - 4 - semi_count);
 	} else {
 		net_process_received_packet(rx_ring + ring_offs + 4, length);
-		debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size-4);
+		debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size - 4);
 	}
 	flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
 
-	cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
-	outw(cur_rx - 16, ioaddr + RxBufPtr);
-	/* See RTL8139 Programming Guide V0.1 for the official handling of
-	 * Rx overflow situations.  The document itself contains basically no
-	 * usable information, except for a few exception handling rules.  */
-	outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
+	cur_rx = ROUND(cur_rx + rx_size + 4, 4);
+	outw(cur_rx - 16, ioaddr + RTL_REG_RXBUFPTR);
+	/*
+	 * See RTL8139 Programming Guide V0.1 for the official handling of
+	 * Rx overflow situations. The document itself contains basically
+	 * no usable information, except for a few exception handling rules.
+	 */
+	outw(status & rxstat, ioaddr + RTL_REG_INTRSTATUS);
+
 	return length;
 }
 
-static void rtl_disable(struct eth_device *dev)
+static int rtl8139_init(struct eth_device *dev, bd_t *bis)
 {
-	int i;
+	unsigned short *ap = (unsigned short *)dev->enetaddr;
+	int addr_len, i;
+	u8 reg;
 
 	ioaddr = dev->iobase;
 
-	/* reset the chip */
-	outb(CmdReset, ioaddr + ChipCmd);
+	/* Bring the chip out of low-power mode. */
+	outb(0x00, ioaddr + RTL_REG_CONFIG1);
 
-	/* Give the chip 10ms to finish the reset. */
-	for (i=0; i<100; ++i){
-		if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
-		udelay (100); /* wait 100us */
+	addr_len = rtl8139_read_eeprom(0, 8) == 0x8129 ? 8 : 6;
+	for (i = 0; i < 3; i++)
+		*ap++ = le16_to_cpu(rtl8139_read_eeprom(i + 7, addr_len));
+
+	rtl8139_reset(dev);
+
+	reg = inb(ioaddr + RTL_REG_MEDIASTATUS);
+	if (reg & RTL_REG_MEDIASTATUS_MSRLINKFAIL) {
+		printf("Cable not connected or other link failure\n");
+		return -1;
 	}
+
+	return 0;
+}
+
+static void rtl8139_stop(struct eth_device *dev)
+{
+	ioaddr = dev->iobase;
+
+	rtl8139_hw_reset(dev);
+}
+
+static int rtl8139_bcast_addr(struct eth_device *dev, const u8 *bcast_mac,
+			      int join)
+{
+	return 0;
+}
+
+static struct pci_device_id supported[] = {
+	{ PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139 },
+	{ PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139 },
+	{ }
+};
+
+int rtl8139_initialize(bd_t *bis)
+{
+	struct eth_device *dev;
+	int card_number = 0;
+	pci_dev_t devno;
+	int idx = 0;
+	u32 iobase;
+
+	while (1) {
+		/* Find RTL8139 */
+		devno = pci_find_devices(supported, idx++);
+		if (devno < 0)
+			break;
+
+		pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
+		iobase &= ~0xf;
+
+		debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
+
+		dev = (struct eth_device *)malloc(sizeof(*dev));
+		if (!dev) {
+			printf("Can not allocate memory of rtl8139\n");
+			break;
+		}
+		memset(dev, 0, sizeof(*dev));
+
+		sprintf(dev->name, "RTL8139#%d", card_number);
+
+		dev->priv = (void *)devno;
+		dev->iobase = (int)bus_to_phys(iobase);
+		dev->init = rtl8139_init;
+		dev->halt = rtl8139_stop;
+		dev->send = rtl8139_send;
+		dev->recv = rtl8139_recv;
+		dev->mcast = rtl8139_bcast_addr;
+
+		eth_register(dev);
+
+		card_number++;
+
+		pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
+
+		udelay(10 * 1000);
+	}
+
+	return card_number;
 }
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 257b0385c2..45ecd6a263 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -10,84 +10,239 @@
 #include <malloc.h>
 #include <net.h>
 #include <miiphy.h>
+#include <linux/io.h>
+#include <linux/types.h>
 
 #include "smc911x.h"
 
-u32 pkt_data_pull(struct eth_device *dev, u32 addr) \
-	__attribute__ ((weak, alias ("smc911x_reg_read")));
-void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) \
-	__attribute__ ((weak, alias ("smc911x_reg_write")));
+struct chip_id {
+	u16 id;
+	char *name;
+};
 
-static void smc911x_handle_mac_address(struct eth_device *dev)
+struct smc911x_priv {
+#ifndef CONFIG_DM_ETH
+	struct eth_device	dev;
+#endif
+	phys_addr_t		iobase;
+	const struct chip_id	*chipid;
+	unsigned char		enetaddr[6];
+};
+
+static const struct chip_id chip_ids[] =  {
+	{ CHIP_89218, "LAN89218" },
+	{ CHIP_9115, "LAN9115" },
+	{ CHIP_9116, "LAN9116" },
+	{ CHIP_9117, "LAN9117" },
+	{ CHIP_9118, "LAN9118" },
+	{ CHIP_9211, "LAN9211" },
+	{ CHIP_9215, "LAN9215" },
+	{ CHIP_9216, "LAN9216" },
+	{ CHIP_9217, "LAN9217" },
+	{ CHIP_9218, "LAN9218" },
+	{ CHIP_9220, "LAN9220" },
+	{ CHIP_9221, "LAN9221" },
+	{ 0, NULL },
+};
+
+#define DRIVERNAME "smc911x"
+
+#if defined (CONFIG_SMC911X_32_BIT) && \
+	defined (CONFIG_SMC911X_16_BIT)
+#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
+	CONFIG_SMC911X_16_BIT shall be set"
+#endif
+
+#if defined (CONFIG_SMC911X_32_BIT)
+static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
+{
+	return readl(priv->iobase + offset);
+}
+
+static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
+{
+	writel(val, priv->iobase + offset);
+}
+#elif defined (CONFIG_SMC911X_16_BIT)
+static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
+{
+	return (readw(priv->iobase + offset) & 0xffff) |
+	       (readw(priv->iobase + offset + 2) << 16);
+}
+static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
+{
+	writew(val & 0xffff, priv->iobase + offset);
+	writew(val >> 16, priv->iobase + offset + 2);
+}
+#else
+#error "SMC911X: undefined bus width"
+#endif /* CONFIG_SMC911X_16_BIT */
+
+static u32 smc911x_get_mac_csr(struct smc911x_priv *priv, u8 reg)
+{
+	while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+	smc911x_reg_write(priv, MAC_CSR_CMD,
+			MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
+	while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+
+	return smc911x_reg_read(priv, MAC_CSR_DATA);
+}
+
+static void smc911x_set_mac_csr(struct smc911x_priv *priv, u8 reg, u32 data)
+{
+	while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+	smc911x_reg_write(priv, MAC_CSR_DATA, data);
+	smc911x_reg_write(priv, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
+	while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+}
+
+static int smc911x_detect_chip(struct smc911x_priv *priv)
+{
+	unsigned long val, i;
+
+	val = smc911x_reg_read(priv, BYTE_TEST);
+	if (val == 0xffffffff) {
+		/* Special case -- no chip present */
+		return -1;
+	} else if (val != 0x87654321) {
+		printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
+		return -1;
+	}
+
+	val = smc911x_reg_read(priv, ID_REV) >> 16;
+	for (i = 0; chip_ids[i].id != 0; i++) {
+		if (chip_ids[i].id == val) break;
+	}
+	if (!chip_ids[i].id) {
+		printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
+		return -1;
+	}
+
+	priv->chipid = &chip_ids[i];
+
+	return 0;
+}
+
+static void smc911x_reset(struct smc911x_priv *priv)
+{
+	int timeout;
+
+	/*
+	 *  Take out of PM setting first
+	 *  Device is already wake up if PMT_CTRL_READY bit is set
+	 */
+	if ((smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY) == 0) {
+		/* Write to the bytetest will take out of powerdown */
+		smc911x_reg_write(priv, BYTE_TEST, 0x0);
+
+		timeout = 10;
+
+		while (timeout-- &&
+			!(smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY))
+			udelay(10);
+		if (timeout < 0) {
+			printf(DRIVERNAME
+				": timeout waiting for PM restore\n");
+			return;
+		}
+	}
+
+	/* Disable interrupts */
+	smc911x_reg_write(priv, INT_EN, 0);
+
+	smc911x_reg_write(priv, HW_CFG, HW_CFG_SRST);
+
+	timeout = 1000;
+	while (timeout-- && smc911x_reg_read(priv, E2P_CMD) & E2P_CMD_EPC_BUSY)
+		udelay(10);
+
+	if (timeout < 0) {
+		printf(DRIVERNAME ": reset timeout\n");
+		return;
+	}
+
+	/* Reset the FIFO level and flow control settings */
+	smc911x_set_mac_csr(priv, FLOW, FLOW_FCPT | FLOW_FCEN);
+	smc911x_reg_write(priv, AFC_CFG, 0x0050287F);
+
+	/* Set to LED outputs */
+	smc911x_reg_write(priv, GPIO_CFG, 0x70070000);
+}
+
+static void smc911x_handle_mac_address(struct smc911x_priv *priv)
 {
 	unsigned long addrh, addrl;
-	uchar *m = dev->enetaddr;
+	unsigned char *m = priv->enetaddr;
 
 	addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
 	addrh = m[4] | (m[5] << 8);
-	smc911x_set_mac_csr(dev, ADDRL, addrl);
-	smc911x_set_mac_csr(dev, ADDRH, addrh);
+	smc911x_set_mac_csr(priv, ADDRL, addrl);
+	smc911x_set_mac_csr(priv, ADDRH, addrh);
 
 	printf(DRIVERNAME ": MAC %pM\n", m);
 }
 
-static int smc911x_eth_phy_read(struct eth_device *dev,
+static int smc911x_eth_phy_read(struct smc911x_priv *priv,
 				u8 phy, u8 reg, u16 *val)
 {
-	while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
+	while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
 		;
 
-	smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 |
+	smc911x_set_mac_csr(priv, MII_ACC, phy << 11 | reg << 6 |
 				MII_ACC_MII_BUSY);
 
-	while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
+	while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
 		;
 
-	*val = smc911x_get_mac_csr(dev, MII_DATA);
+	*val = smc911x_get_mac_csr(priv, MII_DATA);
 
 	return 0;
 }
 
-static int smc911x_eth_phy_write(struct eth_device *dev,
+static int smc911x_eth_phy_write(struct smc911x_priv *priv,
 				u8 phy, u8 reg, u16  val)
 {
-	while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
+	while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
 		;
 
-	smc911x_set_mac_csr(dev, MII_DATA, val);
-	smc911x_set_mac_csr(dev, MII_ACC,
+	smc911x_set_mac_csr(priv, MII_DATA, val);
+	smc911x_set_mac_csr(priv, MII_ACC,
 		phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
 
-	while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
+	while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
 		;
 	return 0;
 }
 
-static int smc911x_phy_reset(struct eth_device *dev)
+static int smc911x_phy_reset(struct smc911x_priv *priv)
 {
 	u32 reg;
 
-	reg = smc911x_reg_read(dev, PMT_CTRL);
+	reg = smc911x_reg_read(priv, PMT_CTRL);
 	reg &= ~0xfffff030;
 	reg |= PMT_CTRL_PHY_RST;
-	smc911x_reg_write(dev, PMT_CTRL, reg);
+	smc911x_reg_write(priv, PMT_CTRL, reg);
 
 	mdelay(100);
 
 	return 0;
 }
 
-static void smc911x_phy_configure(struct eth_device *dev)
+static void smc911x_phy_configure(struct smc911x_priv *priv)
 {
 	int timeout;
 	u16 status;
 
-	smc911x_phy_reset(dev);
+	smc911x_phy_reset(priv);
 
-	smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET);
+	smc911x_eth_phy_write(priv, 1, MII_BMCR, BMCR_RESET);
 	mdelay(1);
-	smc911x_eth_phy_write(dev, 1, MII_ADVERTISE, 0x01e1);
-	smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_ANENABLE |
+	smc911x_eth_phy_write(priv, 1, MII_ADVERTISE, 0x01e1);
+	smc911x_eth_phy_write(priv, 1, MII_BMCR, BMCR_ANENABLE |
 				BMCR_ANRESTART);
 
 	timeout = 5000;
@@ -96,7 +251,7 @@ static void smc911x_phy_configure(struct eth_device *dev)
 		if ((timeout--) == 0)
 			goto err_out;
 
-		if (smc911x_eth_phy_read(dev, 1, MII_BMSR, &status) != 0)
+		if (smc911x_eth_phy_read(priv, 1, MII_BMSR, &status) != 0)
 			goto err_out;
 	} while (!(status & BMSR_LSTATUS));
 
@@ -108,65 +263,65 @@ err_out:
 	printf(DRIVERNAME ": autonegotiation timed out\n");
 }
 
-static void smc911x_enable(struct eth_device *dev)
+static void smc911x_enable(struct smc911x_priv *priv)
 {
 	/* Enable TX */
-	smc911x_reg_write(dev, HW_CFG, 8 << 16 | HW_CFG_SF);
+	smc911x_reg_write(priv, HW_CFG, 8 << 16 | HW_CFG_SF);
 
-	smc911x_reg_write(dev, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
+	smc911x_reg_write(priv, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
 
-	smc911x_reg_write(dev, TX_CFG, TX_CFG_TX_ON);
+	smc911x_reg_write(priv, TX_CFG, TX_CFG_TX_ON);
 
 	/* no padding to start of packets */
-	smc911x_reg_write(dev, RX_CFG, 0);
+	smc911x_reg_write(priv, RX_CFG, 0);
 
-	smc911x_set_mac_csr(dev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
+	smc911x_set_mac_csr(priv, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
 				MAC_CR_HBDIS);
-
 }
 
-static int smc911x_init(struct eth_device *dev, bd_t * bd)
+static int smc911x_init_common(struct smc911x_priv *priv)
 {
-	struct chip_id *id = dev->priv;
+	const struct chip_id *id = priv->chipid;
 
 	printf(DRIVERNAME ": detected %s controller\n", id->name);
 
-	smc911x_reset(dev);
+	smc911x_reset(priv);
 
 	/* Configure the PHY, initialize the link state */
-	smc911x_phy_configure(dev);
+	smc911x_phy_configure(priv);
 
-	smc911x_handle_mac_address(dev);
+	smc911x_handle_mac_address(priv);
 
 	/* Turn on Tx + Rx */
-	smc911x_enable(dev);
+	smc911x_enable(priv);
 
 	return 0;
 }
 
-static int smc911x_send(struct eth_device *dev, void *packet, int length)
+static int smc911x_send_common(struct smc911x_priv *priv,
+			       void *packet, int length)
 {
 	u32 *data = (u32*)packet;
 	u32 tmplen;
 	u32 status;
 
-	smc911x_reg_write(dev, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG |
+	smc911x_reg_write(priv, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG |
 				TX_CMD_A_INT_LAST_SEG | length);
-	smc911x_reg_write(dev, TX_DATA_FIFO, length);
+	smc911x_reg_write(priv, TX_DATA_FIFO, length);
 
 	tmplen = (length + 3) / 4;
 
 	while (tmplen--)
-		pkt_data_push(dev, TX_DATA_FIFO, *data++);
+		smc911x_reg_write(priv, TX_DATA_FIFO, *data++);
 
 	/* wait for transmission */
-	while (!((smc911x_reg_read(dev, TX_FIFO_INF) &
+	while (!((smc911x_reg_read(priv, TX_FIFO_INF) &
 					TX_FIFO_INF_TSUSED) >> 16));
 
 	/* get status. Ignore 'no carrier' error, it has no meaning for
 	 * full duplex operation
 	 */
-	status = smc911x_reg_read(dev, TX_STATUS_FIFO) &
+	status = smc911x_reg_read(priv, TX_STATUS_FIFO) &
 			(TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL |
 			TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
 
@@ -183,117 +338,296 @@ static int smc911x_send(struct eth_device *dev, void *packet, int length)
 	return -1;
 }
 
-static void smc911x_halt(struct eth_device *dev)
+static void smc911x_halt_common(struct smc911x_priv *priv)
 {
-	smc911x_reset(dev);
-	smc911x_handle_mac_address(dev);
+	smc911x_reset(priv);
+	smc911x_handle_mac_address(priv);
 }
 
-static int smc911x_rx(struct eth_device *dev)
+static int smc911x_recv_common(struct smc911x_priv *priv, u32 *data)
 {
-	u32 *data = (u32 *)net_rx_packets[0];
 	u32 pktlen, tmplen;
 	u32 status;
 
-	if ((smc911x_reg_read(dev, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) {
-		status = smc911x_reg_read(dev, RX_STATUS_FIFO);
-		pktlen = (status & RX_STS_PKT_LEN) >> 16;
+	status = smc911x_reg_read(priv, RX_FIFO_INF);
+	if (!(status & RX_FIFO_INF_RXSUSED))
+		return 0;
 
-		smc911x_reg_write(dev, RX_CFG, 0);
+	status = smc911x_reg_read(priv, RX_STATUS_FIFO);
+	pktlen = (status & RX_STS_PKT_LEN) >> 16;
 
-		tmplen = (pktlen + 3) / 4;
-		while (tmplen--)
-			*data++ = pkt_data_pull(dev, RX_DATA_FIFO);
+	smc911x_reg_write(priv, RX_CFG, 0);
 
-		if (status & RX_STS_ES)
-			printf(DRIVERNAME
-				": dropped bad packet. Status: 0x%08x\n",
-				status);
-		else
-			net_process_received_packet(net_rx_packets[0], pktlen);
+	tmplen = (pktlen + 3) / 4;
+	while (tmplen--)
+		*data++ = smc911x_reg_read(priv, RX_DATA_FIFO);
+
+	if (status & RX_STS_ES) {
+		printf(DRIVERNAME
+			": dropped bad packet. Status: 0x%08x\n",
+			status);
+		return 0;
 	}
 
-	return 0;
+	return pktlen;
 }
 
+#ifndef CONFIG_DM_ETH
+
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 /* wrapper for smc911x_eth_phy_read */
 static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
 			       int reg)
 {
-	u16 val = 0;
 	struct eth_device *dev = eth_get_dev_by_name(bus->name);
-	if (dev) {
-		int retval = smc911x_eth_phy_read(dev, phy, reg, &val);
-		if (retval < 0)
-			return retval;
-		return val;
-	}
-	return -ENODEV;
+	struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+	u16 val = 0;
+	int ret;
+
+	if (!dev || !priv)
+		return -ENODEV;
+
+	ret = smc911x_eth_phy_read(priv, phy, reg, &val);
+	if (ret < 0)
+		return ret;
+
+	return val;
 }
+
 /* wrapper for smc911x_eth_phy_write */
 static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
 				int reg, u16 val)
 {
 	struct eth_device *dev = eth_get_dev_by_name(bus->name);
-	if (dev)
-		return smc911x_eth_phy_write(dev, phy, reg, val);
-	return -ENODEV;
+	struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+
+	if (!dev || !priv)
+		return -ENODEV;
+
+	return smc911x_eth_phy_write(priv, phy, reg, val);
+}
+
+static int smc911x_initialize_mii(struct smc911x_priv *priv)
+{
+	struct mii_dev *mdiodev = mdio_alloc();
+	int ret;
+
+	if (!mdiodev)
+		return -ENOMEM;
+
+	strncpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN);
+	mdiodev->read = smc911x_miiphy_read;
+	mdiodev->write = smc911x_miiphy_write;
+
+	ret = mdio_register(mdiodev);
+	if (ret < 0) {
+		mdio_free(mdiodev);
+		return ret;
+	}
+
+	return 0;
+}
+#else
+static int smc911x_initialize_mii(struct smc911x_priv *priv)
+{
+	return 0;
 }
 #endif
 
+static int smc911x_init(struct eth_device *dev, bd_t *bd)
+{
+	struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+
+	return smc911x_init_common(priv);
+}
+
+static void smc911x_halt(struct eth_device *dev)
+{
+	struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+
+	smc911x_halt_common(priv);
+}
+
+static int smc911x_send(struct eth_device *dev, void *packet, int length)
+{
+	struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+
+	return smc911x_send_common(priv, packet, length);
+}
+
+static int smc911x_recv(struct eth_device *dev)
+{
+	struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
+	u32 *data = (u32 *)net_rx_packets[0];
+	int ret;
+
+	ret = smc911x_recv_common(priv, data);
+	if (ret)
+		net_process_received_packet(net_rx_packets[0], ret);
+
+	return ret;
+}
+
 int smc911x_initialize(u8 dev_num, int base_addr)
 {
 	unsigned long addrl, addrh;
-	struct eth_device *dev;
+	struct smc911x_priv *priv;
+	int ret;
 
-	dev = malloc(sizeof(*dev));
-	if (!dev) {
-		return -1;
-	}
-	memset(dev, 0, sizeof(*dev));
+	priv = calloc(1, sizeof(*priv));
+	if (!priv)
+		return -ENOMEM;
 
-	dev->iobase = base_addr;
+	priv->iobase = base_addr;
+	priv->dev.iobase = base_addr;
 
 	/* Try to detect chip. Will fail if not present. */
-	if (smc911x_detect_chip(dev)) {
-		free(dev);
-		return 0;
+	ret = smc911x_detect_chip(priv);
+	if (ret) {
+		ret = 0;	/* Card not detected is not an error */
+		goto err_detect;
 	}
 
-	addrh = smc911x_get_mac_csr(dev, ADDRH);
-	addrl = smc911x_get_mac_csr(dev, ADDRL);
+	addrh = smc911x_get_mac_csr(priv, ADDRH);
+	addrl = smc911x_get_mac_csr(priv, ADDRL);
 	if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) {
 		/* address is obtained from optional eeprom */
-		dev->enetaddr[0] = addrl;
-		dev->enetaddr[1] = addrl >>  8;
-		dev->enetaddr[2] = addrl >> 16;
-		dev->enetaddr[3] = addrl >> 24;
-		dev->enetaddr[4] = addrh;
-		dev->enetaddr[5] = addrh >> 8;
+		priv->enetaddr[0] = addrl;
+		priv->enetaddr[1] = addrl >>  8;
+		priv->enetaddr[2] = addrl >> 16;
+		priv->enetaddr[3] = addrl >> 24;
+		priv->enetaddr[4] = addrh;
+		priv->enetaddr[5] = addrh >> 8;
+		memcpy(priv->dev.enetaddr, priv->enetaddr, 6);
 	}
 
-	dev->init = smc911x_init;
-	dev->halt = smc911x_halt;
-	dev->send = smc911x_send;
-	dev->recv = smc911x_rx;
-	sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);
+	priv->dev.init = smc911x_init;
+	priv->dev.halt = smc911x_halt;
+	priv->dev.send = smc911x_send;
+	priv->dev.recv = smc911x_recv;
+	sprintf(priv->dev.name, "%s-%hu", DRIVERNAME, dev_num);
 
-	eth_register(dev);
+	eth_register(&priv->dev);
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-	int retval;
-	struct mii_dev *mdiodev = mdio_alloc();
-	if (!mdiodev)
-		return -ENOMEM;
-	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
-	mdiodev->read = smc911x_miiphy_read;
-	mdiodev->write = smc911x_miiphy_write;
-
-	retval = mdio_register(mdiodev);
-	if (retval < 0)
-		return retval;
-#endif
+	ret = smc911x_initialize_mii(priv);
+	if (ret)
+		goto err_mii;
 
 	return 1;
+
+err_mii:
+	eth_unregister(&priv->dev);
+err_detect:
+	free(priv);
+	return ret;
+}
+
+#else	/* ifdef CONFIG_DM_ETH */
+
+static int smc911x_start(struct udevice *dev)
+{
+	struct eth_pdata *plat = dev_get_platdata(dev);
+	struct smc911x_priv *priv = dev_get_priv(dev);
+
+	memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
+
+	return smc911x_init_common(priv);
+}
+
+static void smc911x_stop(struct udevice *dev)
+{
+	struct smc911x_priv *priv = dev_get_priv(dev);
+
+	smc911x_halt_common(priv);
+}
+
+static int smc911x_send(struct udevice *dev, void *packet, int length)
+{
+	struct smc911x_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = smc911x_send_common(priv, packet, length);
+
+	return ret ? 0 : -ETIMEDOUT;
+}
+
+static int smc911x_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+	struct smc911x_priv *priv = dev_get_priv(dev);
+	u32 *data = (u32 *)net_rx_packets[0];
+	int ret;
+
+	ret = smc911x_recv_common(priv, data);
+	if (ret)
+		*packetp = (void *)data;
+
+	return ret ? ret : -EAGAIN;
+}
+
+static int smc911x_bind(struct udevice *dev)
+{
+	return device_set_name(dev, dev->name);
 }
+
+static int smc911x_probe(struct udevice *dev)
+{
+	struct smc911x_priv *priv = dev_get_priv(dev);
+	unsigned long addrh, addrl;
+	int ret;
+
+	/* Try to detect chip. Will fail if not present. */
+	ret = smc911x_detect_chip(priv);
+	if (ret)
+		return ret;
+
+	addrh = smc911x_get_mac_csr(priv, ADDRH);
+	addrl = smc911x_get_mac_csr(priv, ADDRL);
+	if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) {
+		/* address is obtained from optional eeprom */
+		priv->enetaddr[0] = addrl;
+		priv->enetaddr[1] = addrl >>  8;
+		priv->enetaddr[2] = addrl >> 16;
+		priv->enetaddr[3] = addrl >> 24;
+		priv->enetaddr[4] = addrh;
+		priv->enetaddr[5] = addrh >> 8;
+	}
+
+	return 0;
+}
+
+static int smc911x_ofdata_to_platdata(struct udevice *dev)
+{
+	struct smc911x_priv *priv = dev_get_priv(dev);
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+
+	pdata->iobase = devfdt_get_addr(dev);
+	priv->iobase = pdata->iobase;
+
+	return 0;
+}
+
+static const struct eth_ops smc911x_ops = {
+	.start	= smc911x_start,
+	.send	= smc911x_send,
+	.recv	= smc911x_recv,
+	.stop	= smc911x_stop,
+};
+
+static const struct udevice_id smc911x_ids[] = {
+	{ .compatible = "smsc,lan9115" },
+	{ }
+};
+
+U_BOOT_DRIVER(smc911x) = {
+	.name		= "eth_smc911x",
+	.id		= UCLASS_ETH,
+	.of_match	= smc911x_ids,
+	.bind		= smc911x_bind,
+	.ofdata_to_platdata = smc911x_ofdata_to_platdata,
+	.probe		= smc911x_probe,
+	.ops		= &smc911x_ops,
+	.priv_auto_alloc_size = sizeof(struct smc911x_priv),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+	.flags		= DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index 3145fbde2b..ce66900f4c 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -8,47 +8,6 @@
 #ifndef _SMC911X_H_
 #define _SMC911X_H_
 
-#include <linux/types.h>
-
-#define DRIVERNAME "smc911x"
-
-#if defined (CONFIG_SMC911X_32_BIT) && \
-	defined (CONFIG_SMC911X_16_BIT)
-#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
-	CONFIG_SMC911X_16_BIT shall be set"
-#endif
-
-#if defined (CONFIG_SMC911X_32_BIT)
-static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
-{
-	return *(volatile u32*)(dev->iobase + offset);
-}
-u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
-	__attribute__((weak, alias("__smc911x_reg_read")));
-
-static inline void __smc911x_reg_write(struct eth_device *dev,
-					u32 offset, u32 val)
-{
-	*(volatile u32*)(dev->iobase + offset) = val;
-}
-void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
-	__attribute__((weak, alias("__smc911x_reg_write")));
-#elif defined (CONFIG_SMC911X_16_BIT)
-static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
-{
-	volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
-	return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
-}
-static inline void smc911x_reg_write(struct eth_device *dev,
-					u32 offset, u32 val)
-{
-	*(volatile u16 *)(dev->iobase + offset) = (u16)val;
-	*(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
-}
-#else
-#error "SMC911X: undefined bus width"
-#endif /* CONFIG_SMC911X_16_BIT */
-
 /* Below are the register offsets and bit definitions
  * of the Lan911x memory space
  */
@@ -380,120 +339,4 @@ static inline void smc911x_reg_write(struct eth_device *dev,
 #define CHIP_9220	0x9220
 #define CHIP_9221	0x9221
 
-struct chip_id {
-	u16 id;
-	char *name;
-};
-
-static const struct chip_id chip_ids[] =  {
-	{ CHIP_89218, "LAN89218" },
-	{ CHIP_9115, "LAN9115" },
-	{ CHIP_9116, "LAN9116" },
-	{ CHIP_9117, "LAN9117" },
-	{ CHIP_9118, "LAN9118" },
-	{ CHIP_9211, "LAN9211" },
-	{ CHIP_9215, "LAN9215" },
-	{ CHIP_9216, "LAN9216" },
-	{ CHIP_9217, "LAN9217" },
-	{ CHIP_9218, "LAN9218" },
-	{ CHIP_9220, "LAN9220" },
-	{ CHIP_9221, "LAN9221" },
-	{ 0, NULL },
-};
-
-static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
-{
-	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
-		;
-	smc911x_reg_write(dev, MAC_CSR_CMD,
-			MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
-	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
-		;
-
-	return smc911x_reg_read(dev, MAC_CSR_DATA);
-}
-
-static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
-{
-	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
-		;
-	smc911x_reg_write(dev, MAC_CSR_DATA, data);
-	smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
-	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
-		;
-}
-
-static int smc911x_detect_chip(struct eth_device *dev)
-{
-	unsigned long val, i;
-
-	val = smc911x_reg_read(dev, BYTE_TEST);
-	if (val == 0xffffffff) {
-		/* Special case -- no chip present */
-		return -1;
-	} else if (val != 0x87654321) {
-		printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
-		return -1;
-	}
-
-	val = smc911x_reg_read(dev, ID_REV) >> 16;
-	for (i = 0; chip_ids[i].id != 0; i++) {
-		if (chip_ids[i].id == val) break;
-	}
-	if (!chip_ids[i].id) {
-		printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
-		return -1;
-	}
-
-	dev->priv = (void *)&chip_ids[i];
-
-	return 0;
-}
-
-static void smc911x_reset(struct eth_device *dev)
-{
-	int timeout;
-
-	/*
-	 *  Take out of PM setting first
-	 *  Device is already wake up if PMT_CTRL_READY bit is set
-	 */
-	if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) {
-		/* Write to the bytetest will take out of powerdown */
-		smc911x_reg_write(dev, BYTE_TEST, 0x0);
-
-		timeout = 10;
-
-		while (timeout-- &&
-			!(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
-			udelay(10);
-		if (timeout < 0) {
-			printf(DRIVERNAME
-				": timeout waiting for PM restore\n");
-			return;
-		}
-	}
-
-	/* Disable interrupts */
-	smc911x_reg_write(dev, INT_EN, 0);
-
-	smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
-
-	timeout = 1000;
-	while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
-		udelay(10);
-
-	if (timeout < 0) {
-		printf(DRIVERNAME ": reset timeout\n");
-		return;
-	}
-
-	/* Reset the FIFO level and flow control settings */
-	smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
-	smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
-
-	/* Set to LED outputs */
-	smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
-}
-
 #endif
diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile
index 779e2528b7..4a34813804 100644
--- a/examples/standalone/Makefile
+++ b/examples/standalone/Makefile
@@ -5,10 +5,13 @@
 
 extra-y        := hello_world
 extra-$(CONFIG_SMC91111)           += smc91111_eeprom
-extra-$(CONFIG_SMC911X)            += smc911x_eeprom
 extra-$(CONFIG_SPI_FLASH_ATMEL)    += atmel_df_pow2
 extra-$(CONFIG_PPC)                += sched
 
+ifndef CONFIG_DM_ETH
+extra-$(CONFIG_SMC911X)            += smc911x_eeprom
+endif
+
 #
 # Some versions of make do not handle trailing white spaces properly;
 # leading to build failures. The problem was found with GNU Make 3.80.
diff --git a/examples/standalone/smc911x_eeprom.c b/examples/standalone/smc911x_eeprom.c
index 2c05ed902d..270588bcf5 100644
--- a/examples/standalone/smc911x_eeprom.c
+++ b/examples/standalone/smc911x_eeprom.c
@@ -18,8 +18,158 @@
 #include <console.h>
 #include <exports.h>
 #include <linux/ctype.h>
+#include <linux/types.h>
 #include "../drivers/net/smc911x.h"
 
+#define DRIVERNAME "smc911x"
+
+#if defined (CONFIG_SMC911X_32_BIT) && \
+	defined (CONFIG_SMC911X_16_BIT)
+#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
+	CONFIG_SMC911X_16_BIT shall be set"
+#endif
+
+struct chip_id {
+	u16 id;
+	char *name;
+};
+
+static const struct chip_id chip_ids[] =  {
+	{ CHIP_89218, "LAN89218" },
+	{ CHIP_9115, "LAN9115" },
+	{ CHIP_9116, "LAN9116" },
+	{ CHIP_9117, "LAN9117" },
+	{ CHIP_9118, "LAN9118" },
+	{ CHIP_9211, "LAN9211" },
+	{ CHIP_9215, "LAN9215" },
+	{ CHIP_9216, "LAN9216" },
+	{ CHIP_9217, "LAN9217" },
+	{ CHIP_9218, "LAN9218" },
+	{ CHIP_9220, "LAN9220" },
+	{ CHIP_9221, "LAN9221" },
+	{ 0, NULL },
+};
+
+#if defined (CONFIG_SMC911X_32_BIT)
+static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+{
+	return *(volatile u32*)(dev->iobase + offset);
+}
+
+static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
+{
+	*(volatile u32*)(dev->iobase + offset) = val;
+}
+#elif defined (CONFIG_SMC911X_16_BIT)
+static u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+{
+	volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
+	return (*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16);
+}
+static void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
+{
+	*(volatile u16 *)(dev->iobase + offset) = (u16)val;
+	*(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
+}
+#else
+#error "SMC911X: undefined bus width"
+#endif /* CONFIG_SMC911X_16_BIT */
+
+static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
+{
+	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+	smc911x_reg_write(dev, MAC_CSR_CMD,
+			MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
+	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+
+	return smc911x_reg_read(dev, MAC_CSR_DATA);
+}
+
+static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
+{
+	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+	smc911x_reg_write(dev, MAC_CSR_DATA, data);
+	smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
+	while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
+		;
+}
+
+static int smc911x_detect_chip(struct eth_device *dev)
+{
+	unsigned long val, i;
+
+	val = smc911x_reg_read(dev, BYTE_TEST);
+	if (val == 0xffffffff) {
+		/* Special case -- no chip present */
+		return -1;
+	} else if (val != 0x87654321) {
+		printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
+		return -1;
+	}
+
+	val = smc911x_reg_read(dev, ID_REV) >> 16;
+	for (i = 0; chip_ids[i].id != 0; i++) {
+		if (chip_ids[i].id == val) break;
+	}
+	if (!chip_ids[i].id) {
+		printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
+		return -1;
+	}
+
+	dev->priv = (void *)&chip_ids[i];
+
+	return 0;
+}
+
+static void smc911x_reset(struct eth_device *dev)
+{
+	int timeout;
+
+	/*
+	 *  Take out of PM setting first
+	 *  Device is already wake up if PMT_CTRL_READY bit is set
+	 */
+	if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) {
+		/* Write to the bytetest will take out of powerdown */
+		smc911x_reg_write(dev, BYTE_TEST, 0x0);
+
+		timeout = 10;
+
+		while (timeout-- &&
+			!(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
+			udelay(10);
+		if (timeout < 0) {
+			printf(DRIVERNAME
+				": timeout waiting for PM restore\n");
+			return;
+		}
+	}
+
+	/* Disable interrupts */
+	smc911x_reg_write(dev, INT_EN, 0);
+
+	smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
+
+	timeout = 1000;
+	while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
+		udelay(10);
+
+	if (timeout < 0) {
+		printf(DRIVERNAME ": reset timeout\n");
+		return;
+	}
+
+	/* Reset the FIFO level and flow control settings */
+	smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
+	smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
+
+	/* Set to LED outputs */
+	smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
+}
+
 /**
  *	smsc_ctrlc - detect press of CTRL+C (common ctrlc() isnt exported!?)
  */
diff --git a/include/configs/malta.h b/include/configs/malta.h
index bb8a44433e..d41b80c7dc 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -16,7 +16,6 @@
 #define CONFIG_PCI_GT64120
 #define CONFIG_PCI_MSC01
 #define CONFIG_PCNET
-#define CONFIG_PCNET_79C973
 #define PCNET_HAS_PROM
 
 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS	0
diff --git a/include/netdev.h b/include/netdev.h
index 68a3fceab6..f2d21c45d0 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -125,6 +125,7 @@ int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
 /*
  * Allow FEC to fine-tune MII configuration on boards which require this.
  */
+struct eth_device;
 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int));
 #endif
 
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 7a5da9d822..19c9218060 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1292,8 +1292,6 @@ CONFIG_PCI_SYS_BUS
 CONFIG_PCI_SYS_PHYS
 CONFIG_PCI_SYS_SIZE
 CONFIG_PCNET
-CONFIG_PCNET_79C973
-CONFIG_PCNET_79C975
 CONFIG_PEN_ADDR_BIG_ENDIAN
 CONFIG_PERIF1_FREQ
 CONFIG_PERIF2_FREQ
@@ -4077,9 +4075,6 @@ CONFIG_TSECV2_1
 CONFIG_TSEC_TBI
 CONFIG_TSEC_TBICR_SETTINGS
 CONFIG_TULIP
-CONFIG_TULIP_FIX_DAVICOM
-CONFIG_TULIP_SELECT_MEDIA
-CONFIG_TULIP_USE_IO
 CONFIG_TWL6030_INPUT
 CONFIG_TWL6030_POWER
 CONFIG_TWR